JPS62200935A - Pcm interface block - Google Patents

Abstract

PURPOSE:To attain the correspondence with use of NRZ codes entirely by connecting a (p).(q) or (r).(q) conversion MUX block to an interface block in the inside of the unit. CONSTITUTION:p=2MHz, q=8MHz are selected in the (p).(q) conversion MUX block M12, r=34MHz, q=8MHz are selected in the 1st (r)-(q) conversion MUX block M23A, r=34MHz, q=8MHz are selected in the 2nd (r)-(q) conversion MUX block M23B, q=8MHz is selected in the (q) interface block 8MINF and r=34MHz is selected in the (r) interface block 34MINF in the 8MINF, the D/I MUX has a D/I MUX block in chained lines in figure. Further, a control section CONT is provided. Thus, the interface block used in combination with the M23MUX block and the M12MUX block and used as units.

Description

[Detailed Description of the Invention] [Summary] For example, the first
multiplexing and decoding of 8 MHz signal and 34 MHz signal
In a PCM multiplexing system that performs second multiplexing and decoding between the signals, the MU that performs the multiplexing and decoding
It constitutes an interface block used in combination with the X block, and performs B/U conversion in the MUX block and U
Part of the /B conversion.

A PCM interface block is disclosed in which the interface block itself can be omitted.

[Industrial application field]

The present invention is a PCM interface block.

Especially 1 for example 2MH2:l! M12MUX block for 8MHz multiplexing/decoding, 8MHz;=34M)lz
This invention relates to a PCM interface block used in combination with an M23 MUX block for multiplexing and decoding.

[Conventional technology]

Conventionally, as shown in FIG. The 8MHz signal is connected to M23 (8
(Conversion between MHz and 34MHz) Multiplexed into a 34MHz signal by MUX unit 2, (iii) Line 3
(iv) is decoded into an 8 MHz signal by the M23MUX unit 4, and (v) is decoded into a 2M)1z signal by the M12MUX units 5-0 to 5-3.

When configuring such a system, conventionally, the method shown in Fig. 8 (A
) with the M12MUX unit as shown in the figure.

It was designed to be used in combination with an M23 MUX unit as shown in FIG. 8(B). In addition, in FIG. 8, reference numeral 6 is a rack for M12MUX unit, and on the rack 6 there is a M12MUX unit with a 2m block as one unit.
Four 2MUX units 1 are mounted. Also, reference numeral 7 is a rack for the M23MUX unit, and the rack 7
Above, M23M, which is made up of one set of blocks as one unit.
Four UX units 2 (or 3) are mounted.

Each M12MLIX block and M23MUX block 07 has an AMI signal interface to a circuit outside the block, and is configured so that processing is performed within the block using an NRZ signal.

Therefore, in the example of FIG. 7, in Ml 2MUX unit l-0, 2MHz (AMI) is 2MHz
z (NRZ), 2M/8M conversion is performed, 8MHz (NRZ) is converted to 8MHz (AMl), and the signal is guided to the M23 MUX unit 2. Also M2
In 3MUX unit 2.

8MHz (AM) is converted to 8MHz (NRZ), 8M/34M conversion is performed, and 34MHz (NRZ)
) is converted to 34MHz (AMI).

It will be output to line 3'.

[Problem that the invention seeks to solve]

In the above conventional case, Ml 2MUX unit and M23
Separate rack with MUX unit! 3! This is not desirable if the racks cannot be used effectively depending on the system scale.

In addition, in the example shown in FIG. 7, 8MHz on the M23MUX unit side of the M12MUX unit 1-0
(NRZ)-8MHz (AMI) conversion and M23MU
Pair M12M U X -L -1 in X unit 2
- 8 MHz (AM 1) on the net side - = 8 MHz
Although H2 (NRZ) conversion can be omitted.

They are built into each unit and cannot be omitted.

Also, if it is omitted, the M23MUX unit side of the Ml 2MUX unit 1-0 or the M2MUX unit side of the Ml 2MUX unit 1-0 or the
This becomes a problem when it is necessary to directly connect the M12 MUX unit side of the M12 MUX unit 2 to an external line.

(Means for Solving the Problems) The present invention provides an interface block configured to solve the above-mentioned problems, and FIG. 1 shows the principle of the present invention showing the manner in which the interface block is used. A configuration diagram is shown.

In Figure 1, 8 indicates a rack, and 9 indicates a 2MHz/34M
H2 conversion unit, 10 is 2MHz/8MHz conversion unit, 11 is first 8MHz/34MH2 conversion unit, 12 is second 8MHz-34MHz conversion unit, 13 is 2MH28MH!・34MHz conversion unit,
14 represents D/I n knit. Further, M12 in the figure is a p'q conversion MUX block.

Compatible with p=2MHz and q=8MHz.

M23A is a first r-q conversion MUX block, and corresponds to r=34 MHz and q=8 MHz.

M23B is a second r-q conversion MUX block 07 and corresponds to r=34 MHz and q=8 MHz.

8MINF is a q interface block according to the present invention, and corresponds to Q=8MHz.

34MINF is an r interface block according to the present invention, and corresponds to r=34MHz.

D/IMUX is a D/I MUX block.

It has the configuration within the chain line shown in FIG. 1(H).

Further, C0NT represents a control section.

[Effect]

In the case shown in FIG.
Although species units are shown, they are not limited to this. However, all the units have substantially the same size and shape, and are selectively placed at the position shown as rM13J on the rack 8 shown in FIG. 1(A), if necessary.

2For example, if unit 9 is placed,
The unit 9 provides the transmitting side configuration shown on the left side of FIG. 7 or the receiving side configuration shown on the right side of the figure.

In addition, in the nine illustrated units 9 to 14.

Each block is assembled into a single unit.

For this reason, the conversion means described for conversion between the AMI signal and the NRZ signal in connection with FIG. 7 is omitted. In other words, (i) When connecting block rM12J to the paired block rM13AJ side in unit 9, NRZ signal-AMI signal conversion is omitted, and (i
f) When connecting block rM13AJ to the paired block “M12” side in unit 9, the AMI signal→N
RZ signal conversion is omitted, and all processing is performed within the unit 9 using NRZ signals (the interface between the unit 9 and external circuits is the AMI signal). The same applies to each unit IO to 14.

〔Example〕

Figure 2 (A), (B), (C), (D)
, (f!-1) or f! -14) is shown in Figure 1 (B)
, (C), (D), (E), and (F) are system configuration diagrams corresponding to the units shown in FIG.

In the case shown in Figure 2 (A), 2MHz and 34M
Conversion to and from Hz is performed. In the case shown in FIG. 2(B), conversion between 2MH2 and 8MHz is performed.

In the case shown in Figure 2 (C), 8MHz and 34M
Conversion to and from Hz is performed. Conversion between +8 MHz and 34 MHz is also performed in the one shown in FIG. 2(D). Figure 2 (f!-1) or 1! -14) is.

34MHz is a mixture of 2 MHz and 8 MHz.
This supports conversion between .

FIG. 3 shows the configuration of an embodiment of the unit corresponding to FIG. 2 (E-11). The illustrated block rM12J, r
8MINFJ, rM23J, rcONT" corresponds to FIG.

The functions of the main parts in the figure are as follows. That is.

■ B/U Bipolar, unipolar conversion.

■ R, L, B, loopback signals from the opposite station are looped back to each channel on the lower order group side of the own station. That is, a signal that has entered channel CHI from the opposing station is sent back to the opposing station as is on channel CHI.

■ II DB-311 Signal conversion is performed using the DB-3 code rule.

■ PLL r) Converts the toothless signal sent from the MUX section into a normal signal.

■ MUX Multiplexes 4CH signals into one.

■　DMUX' Separate one signal into 4CH.

■ SCR Select a certain polynomial and perform conversion.

■ DSCR Select a certain polynomial and perform inverse transformation.

■L, L, B, turn back to the higher order group side by operating the switch on the own station side. That is, the signal that enters the channel CHI of the own station is looped back by the higher-order group of the own station and returns to the channel CHI.

As can be seen from the illustration in FIG.
They communicate using z (NRZ) signals. For this reason, the exit on this side of the M23MUX block does not have B/U conversion or U/B conversion. M12
The same holds true for the M23 MUX block in the MUX block.

However, the side of the M23MUX block mentioned above for the Ml 2MUX block, the M23MUX block of the M12MUX block,
If the side to the UX block is directly connected to a line, it is necessary to have an AMI code for the line.

For this purpose, interface blocks (8MINF blocks in the illustrated case) are prepared as shown in the lower left of FIG. Then, in the interface block, communication is performed using the NRZ code on the M23MUX block and the like.

FIG. 4 shows the first r-q conversion MUX block “M23AM
A more detailed example configuration of the "UX block" is shown below.

The functions of the main parts in the figure are as follows. That is.

■ R, L, B, Same as Figure 3.

- STF C0NT PC Removes the teeth from the clock CLK by the signal from the PC and sends it out as the reception clock RCLK.

■ PL C0NT This signal allows P
Select either C or internal DUMY PC.

■ DUMY Input a signal from the PC clock CLK to STF C0NT that makes the tooth removal rate constant.

■ PGS Kurofuku Generator. 34.368MH
Create a lock as necessary using zCLOCK.

■ Used when inserting data into a variable slot in the VIN PCM frame format.

■ Alarm A on PMTS PCM LINE
When LM is detected, a remote alarm is sent to the opposite station in a PCM frame.

■Receives and receives remote alarms from the RMTR opposing station.

■ Extract the variable slot data in the opposite way to Vout Vin.

[Phase] 5YNC synchronization signal detection.

■ 5YNCERR Detects out of synchronization.

@DIG f! The bit error in RRPCM is 10-
' to 10-8.

@AIS Signals from opposite station all l”
Detect.

Q　SCR,0SCI? Same as Figure 3.

■ Same as HDB-3 Figure 3.

FIG. 5 shows a more detailed configuration of an embodiment of the p'q conversion MUX block rM12J, and FIG. 6 shows the configuration of the q interface.
A more detailed example configuration of block r8MINFJ is shown. The external circuit is shown on the left side of the figure. Moreover, MEM represents memory.

〔Effect of the invention〕

As explained above, according to one aspect of the present invention, an interface block used in combination with an M23 MUX block, an M12 MUX block, etc. is configured.

They are assembled into a unit and used, and all communications within the unit are made possible using the NRZ code.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a system configuration diagram, FIG. 3 is an example configuration of a unit corresponding to FIG. 2 (E-11), and FIG. A more detailed example configuration of the q-transform MUX block. FIG. 5 shows a more detailed configuration of an embodiment of the p'q conversion MUX block, FIG. 6 shows a more detailed configuration of an embodiment of the q interface block, FIG. 7 shows a system configuration diagram, and FIG. 8 shows a conventional configuration. An explanatory diagram explaining the case is shown. In the figure, numeral 8 is a rack, 9 to 14 are each a unit, rM
12J is a p'q conversion MUX block, [M23AJ is the first rq conversion MUX block o7. rM23BJ is the second rq conversion MUX block Dy7. r8MINFJ is a q interface block. r34INFJ is the r interface block. rD/IMUXJ represents a D/IMUX block.

Claims (1)

[Claims] A pMHz signal and a q (where q>p) MHz signal (
However, in a PCM multiplex system that handles r>q) MHz signals, a p/q conversion MUX block that is connected to the external circuit with a pMHz AMI signal and connected to the internal circuit with a qMHz NRZ signal. an r/q conversion MUX block that is connected to the external circuit with an rMHz AMI signal and connected to the internal circuit with a qMHz NRZ signal; and an r/q conversion MUX block that is connected to the external circuit with an AMI signal and connected to the internal circuit. At least an interface block connected to the MU with an NRZ signal is prepared, and the interface block is connected to the p/q conversion MU.
X block or the above r/q conversion MUX block,
A PCM interface block, which is connected to the internal circuit side of the interface block to form a PCM interface block.