KR0182679B1 - Matching circuit between spm and pcm - Google Patents

Abstract

The matching circuit is for matching signals between the SPM device and the PCM stage so that the PCM stage can be monitored using the SPM apparatus. The circuit includes: a first PCM line matching section for matching processing with a reception signal transmission line on the PCM stage; A second PCM line matching unit performing matching processing with a transmission signal transmission line; A first converter converting the signal output from the first PCM line matcher into a 2048 Kbps signal; A second converter for converting a signal output from the second PCM line matcher into a 2048 Kbps signal; A third converter converting the signal output from the first converter into a signal of 64 Kbps and transmitting the signal to the SPM device; A fourth converter for converting the signal output from the second converter into a 64Kbps signal and transmitting the signal to the SPM device; A frame sink (FS) signal clock signal generator; And an output control signal generator for generating a signal for controlling the output of the first and second converters.

Description

Matching circuit between SPM device and PCM stage

1 is a block diagram illustrating a matching circuit between an SP device and a PC stage according to the present invention.

2 is a detailed circuit diagram according to the present invention for the matching circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

100: SPM (SS7 Signaling Protocol Monitor) device

101: CPU (Central Processor Unit)

102: clock signal generator 110: matching circuit

120: PCM (Pulse Code Modulation) stage

201: first PCM line matching unit 202: second PCM line matching unit

211: first PCM / 2048K converter 212: second PCM / 2048K converter

221: output control signal generator

231: frame sink and clock signal generator

241: 2048K / 64K converter

The present invention relates to a matching circuit between an SPM device (hereinafter referred to as SPM device) and PCM (hereinafter referred to as PCM (pulse code modulation)).

SPM device is SS7 (Signaling System No.7) protocol monitor device, and the stability of physical path (Level 1 of No. 7 layer) including nailed-up path should be guaranteed when setting up signal link in TDX exchange system. It is a proposed device to efficiently monitor the reliability and status on the same path (or signal link). Therefore, these SPM devices are implemented to monitor the signal link reliability and status of the signaling terminal (ST), time switch, and PCM, which constitute the nailed-up path of No.7 signal link of the TDX series. However, when monitoring the PCM stage by using the SPM device, there is a problem that can not be directly matched because the signal formats available to each other is different.

Accordingly, an object of the present invention is to provide a matching circuit for matching signals between the SPM device and the PCM terminal so that the PCM stage can be monitored using the SPM device.

The apparatus according to the present invention is a matching circuit for matching between the SPM device and the PCM terminal for monitoring the No.7 protocol, wherein the line and the matching processing on the PCM stage are capable of receiving a received signal (RX) transmitted on the PCM stage. A first PCM line matching unit for doing; A second PCM line matching unit for matching processing with the line on the PCM stage so as to receive the transmission signal TX transmitted on the PCM stage; A first PCM / 2048K conversion unit for converting the PCM received signal output from the first PCM line matching unit into a 2048 Kbps signal; A second PCM / 2048K conversion unit for converting the PCM transmission signal output from the second PCM line matching unit to a 2048 Kbps signal; 2048K / 64K conversion unit for converting the 2048Kbps transmission signal (TXD) to 64Kbps signal to be transmitted to the SPM device; Frame synchronization is performed to the first and second PCM / 2048K converters and the 2048K / 64K converters by the master clock signal MCLK transmitted from the SPM device and the reference clock signal RCLK transmitted from the first or second PCM / 2048K converters. A frame sync and clock signal generator for generating an FS) signal and first and second predetermined clock signals; Signals for controlling the output of the first and second PCM / 2048K converters by the first and second predetermined clock signals generated from the frame sink and clock signal generator and the address / data signals provided from the frame sink signal and the SPM device. Characterized in that it comprises an output control signal generator for generating a.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a matching circuit between an SPM device and a PCM stage according to the present invention, a CPU 101 and a main clock signal (hereinafter referred to as MCLK) generator 102 for controlling the overall functions of the SPM device. It is composed of a SPM device 100, PCM stage 120, the matching circuit 110 for matching the signal between the SPM device 100 and PCM stage 120 configured to include.

FIG. 2 is a detailed circuit diagram according to the present invention for the matching circuit shown in FIG. 1, and includes a first PCM line matching unit 201 and a PCM stage (1) for matching with a reception signal (RX) transmission line of the PCM stage 120. The first PCM / 2048K conversion unit 211 for converting the PCM signal transmitted from the second PCM line matching unit 202 and the first PCM line matching unit 201 to 2048 Kbps to match the transmission signal TX transmission line of 120. ), A signal for controlling the outputs of the second PCM / 2048K converter 212 and the first and second PCM / 2048K converters 211 and 212 for converting the PCM signal transmitted from the second PCM line matcher 202 to 2048 Kbps. 2M using the MCLK signal provided from the output control signal generator 221 and the SPM device 100 and the reference clock signal RCLK provided from the first and second PCM / 2048K converters 211 and 212 as input signals. And a frame sink and clock signal generator 231 for generating the 4M clock signal and the frame sync signal, and the SPM device 100. 2048 Kbps signals provided by the first and second PCM / 2048K converters 211 and 212 are converted to 64 Kbps signals by the null information and the clock signals (2M and 4M clock signals) provided from the frame sync and clock signal generator 231. 2048K / 64K conversion unit 241 for transmitting to the SPM device 100.

Next, the operation of the matching circuit shown in FIG. 2 will be described in detail with reference to FIG. 1.

The first PCM line matching unit 201 performs a line matching process so that the PCMINO + and PCMINO− signals transmitted through the reception signal RX transmission line included in the PCM terminal 120 are applied into the matching circuit 110. The PCM signal line-aligned by the first PCM line matching unit 201 is transmitted to the first PCM / 2048K conversion unit 211.

The second PCM line matching unit 202 performs a line matching process so that the PCMIN1 + and PCMIN− signals transmitted through the transmission signal TX transmission line included in the PCM terminal 120 are applied into the matching circuit 110. The PCM code, which has been line-matched in this way, is transmitted to the second PCM / 2048K converter 212.

The first PCM / 2048K converter 211 may include dummy signals CSTLO 0 through 3 provided from the output control signal generator 221 and a frame sink FS provided by the frame sink and clock signal generator 231. A PCM signal controlled by the 2M clock signal and transmitted from the first PCM line matching unit 201 is converted into a 2048 Kbps reception signal RXD and output. The output received signal RXD is transmitted to the 2048K / 64K converter 241 which will be described later.

The second PCM / 2048K converter 212 may include dummy signals CSTLO 0 through 3 provided from the output control signal generator 221 and a frame sink FS provided by the frame sink and clock signal generator 231. The PCM signal controlled by the 2M clock signal and transmitted from the first PCM line matching unit 201 is converted into a 2048 Kbps transmission signal TXD and output. The output transmission signal TXD is transmitted to the 2048K / 64K converter 241 which will be described later. The first and second PCM / 2048K conversion units 211 and 212 may be implemented as a conference of European Postal and Telecommunications administration (CEPT) digital trunk transceiver.

The 2048K / 64K converter 241 converts the 2048Kbps signal transmitted from the first and second PCM / 2048K converters 211 and 212 into a 64Kbps signal and outputs the 64Kbps signal. In synchronization with the frame sync and 2M clock signal, a 2048 Kbps signal is converted into a 64 Kbps signal and output. At this time, the output 64Kbps signal (a 64Kbps clock signal and a transmission / reception signal) is transmitted using a channel corresponding to the channel (CH) information provided from the CPU 101 provided in the SPM apparatus 100. The 2048K / 64K converter 241 may be implemented as a field programmable gate array (FPGA).

The frame sink and clock signal generator 231 is a MCLK signal of 16.384M transmitted from the clock signal generator 102 in the SPM apparatus 100 and an 8M signal transmitted from the first and second PCM / 2048K converters 211 and 212. The clock signal and frame sync FS corresponding to 2M and 4M are generated using the reference clock signal RCLK as an input signal.

The output control signal generator 221 includes an address / data signal provided from the CPU 101 in the SPM apparatus 100 and clock signals (2M and 4M clock signals) transmitted from the frame sync and clock signal generator 231. The above-described dummy signals of CSTLO 0 to 3 are output by the frame sync signal.

As described above, the present invention provides a signal for matching the signal of the SPM device and the signal of the PCM terminal so that the SPM device can monitor the signal transmitted and received to the PCM terminal, the signal transmitted and received to the PCM terminal This has the advantage of smooth monitoring.

Claims (3)

In the matching circuit for matching between the SPM device 100 and the PCM stage 120 to monitor the protocol No.7, the PCM to receive the received signal (RX) transmitted on the PCM stage 120 A first PCM line matching unit 201 for matching with the line on the stage 120; A second PCM line matching unit (202) for performing matching processing with a line on the PCM terminal (120) to receive a transmission signal (TX) transmitted on the PCM terminal (120); A first PCM / 2048K conversion unit 211 for converting the PCM received signal output from the first PCM line matching unit 201 into a 2048 Kbps signal; A second PCM / 2048K conversion unit 212 for converting the PCM transmission signal output from the second PCM line matching unit 202 into a 2048 Kbps signal; The SPM device converts a 2048 Kbps received signal (RXD) transmitted from the first PCM / 2048K converter 211 and a 2048 Kbps transmitted signal (TXD) transmitted from the second PCM / 2048K converter 212 into a 64 Kbps signal. 2048K / 64K converter 241 for transmitting to (100); The first and second PCM / 2048K converters by the master clock signal MCLK transmitted from the SPM device 100 and the reference clock signal RCLK transmitted from the first or second PCM / 2048K converters 211 and 212. A frame sync and clock signal generator 231 for generating a frame sync (FS) signal and first and second predetermined clock signals to the 211 and 212 and the 2048K / 64K converter 241; The first and second PCMs may be generated by the first and second predetermined clock signals and the frame sync signal generated by the frame sync and clock signal generator 231 and the address / data signals provided by the SPM device 100. And an output control signal generator (221) for generating a signal for controlling the outputs of the / 2048K converters (211,212). The matching circuit of claim 1, wherein the 2048K / 64K converter 241 is implemented as a field programmable gate array. The method of claim 1, wherein the first predetermined clock signal generated by the frame sink and clock signal generator 231 is a 2M clock signal, and the second predetermined clock signal is a 4M clock signal. Matching circuit between the SPM and PCM stage.