JPH1011390A - Microprocessor-applied device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor-applied system which decreases the number of wires between a processor device and a memory device or input/ output device, or between printed boards and can interchange information with many memory devices or input/output devices. SOLUTION: A microprocessor device 11 is connected to a 1st bus 13, which is supplied with at least an address signal and a data signal among input/output signals of the microprocessor device 11. A parallel-serial conversion device 19 is connected to the 1st bus 13 and converts a parallel signal supplied to the 1st bus 13 into a serial signal and supplies it to a serial signal transmission line 20. The signal of this serial signal transmission line 20 is supplied to a serial-parallel conversion device 21 and reconverted into a parallel signal, which is supplied to a 2nd bus 17. To this 2nd bus 17, the memory device 14 and/or input/output device 15 is connected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor application device, and more particularly, to a connection between devices.

[0002]

2. Description of the Related Art Conventionally, in a microprocessor application system, when data is transmitted and received between a processor device and a memory device or an input / output device, connection of an address bus signal, a data bus signal, and an input / output control signal is required. is necessary. Generally, these address bus signals, data bus signals, and input / output control signals are composed of a plurality of bits, and therefore, the number of these signal lines is required to correspond to the number of bits of each signal. When transmitting such a data signal composed of a plurality of bits, in order to reduce the number of signal lines, a method of converting a parallel signal into a serial signal using a shift register or the like and transmitting the signal through a small number of signal lines is also used. I have.

[0003]

However, in such a microprocessor application system, an address bus signal, a data bus signal and an input / output control signal are generally provided between the processor device and the memory device or the input / output device. For transmission, it is necessary to wire a bus composed of a large number of signal lines, and there is a drawback that the device becomes complicated and large.

Further, in such a microprocessor application system, circuits and components are usually divided and mounted on a plurality of printed boards, and the wiring between the printed boards is also made by a large number of signal lines as described above. The connection has to be made, which has the disadvantage that the device becomes complicated and the wiring work becomes complicated.

Accordingly, an object of the present invention is to reduce the number of wires between a processor device and a memory device or an input / output device, or between printed boards, and to reduce noise and the like in such a microprocessor application system. It is intended to transmit a signal without being performed.

[0006]

According to the present invention, a microprocessor device is connected, a first bus including at least an address signal and a data signal bus among output signals of the microprocessor device, and a first bus. A parallel-serial converter connected to the first bus, a serial signal line transmitting an output signal of the parallel-serial converter, a serial-parallel converter supplied with a signal of the serial signal line, A microprocessor application device is provided, wherein the parallel signal line of the serial-parallel conversion device is connected, and a second bus to which a memory device or an input / output device is connected is provided.

Further, according to the present invention, the microprocessor application device is supplied with the address signal and the data signal transmitted through the first bus, and has a predetermined functional relationship with these signals. A first redundant signal generating means for generating one redundant signal and supplying the redundant signal as an additional input signal to the parallel-serial conversion device; and a parallel output signal of the serial-parallel conversion device. A second redundant signal generating means for receiving a data signal and generating a second redundant signal having the predetermined functional relationship with these signals;
Means for comparing the second redundant signal generated by the redundant signal generating means with the first redundant signal in the parallel output signal of the serial-parallel converter. A microprocessor application device is obtained.

Further, according to the present invention, the microprocessor-applied device may further comprise a parallel-to-serial converter, wherein the number of bits of a parallel input signal is different from the number of bits of a parallel output signal of the serial-to-parallel converter. One transmission / reception of the parallel-serial conversion device corresponds to plural transmissions / receptions of the serial-parallel conversion device, or plural transmission / receptions of the parallel-serial conversion device corresponds to one transmission / reception of the serial-parallel conversion device. The microprocessor application device described above, characterized by comprising means for conversion.

Further, according to the present invention, the microprocessor application device is supplied with the address signal and the data signal transmitted by the first bus, and converts these signals into an output signal having a smaller number of bits. Encoding means for supplying the input signal to the parallel-serial conversion device as an input signal, and an output signal of the serial-parallel conversion device being supplied and performing reverse conversion on the encoding means to perform the second conversion. And a decoding means for supplying the data to the bus.

Further, according to the present invention, in a microprocessor application device comprising a plurality of printed boards on which circuits and components are wired and mounted, the microprocessor is wired to a first board among the plurality of printed boards, and at least an address is provided. A first bus including a signal bus and a data signal bus, a second bus wired to a second board among the plurality of printed boards, and including at least an address signal bus and a data signal bus; A first and a second parallel-serial converter connected to the second bus; and a signal line interconnecting the first and the second parallel-serial converter. A microprocessor application device is obtained.

With the above configuration, in the microprocessor application device of the present invention, the number of signal transmission wires between the processor device and the memory device or the input / output device or between the printed circuit boards is converted from parallel to serial. It can be reduced by using a device and a serial-to-parallel converter. In addition, since the address signal and the data signal are parallel-to-serial converted integrally, by changing the address signal, it is possible to reduce the number of transmission lines and increase the memory capacity. Signals can be transmitted to and from a device or an input / output device.

Further, in order to transmit the address signal and the data signal together with the parallel-serial conversion and the redundant signal generated by the redundant signal generating means,
It is possible to prevent a signal transmission error due to external noise or a failure inside the circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a microprocessor application device according to the present invention. In FIG. 1, a microprocessor 11 has a first input / output bus 12 for inputting / outputting an address signal, a data signal, and an input / output control signal each consisting of a plurality of bits of binary information.
Is connected to the bus 13. Here, the input / output bus 12
Are bidirectional signals that can also be used as input signals of the processor device 11. A memory device 14, which constitutes a microprocessor application device together with the microprocessor 11, a plurality of input / output devices 15,
16 are connected to the second bus 17. Similarly to the first bus 13, the second bus 17 includes a plurality of transmission lines for transmitting an address signal, a data signal, and an input / output control signal, each of which includes a plurality of bits of binary information.

The signal on the first bus 13 is supplied via an input bus 18 to a first shift register 19 constituting a parallel-serial converter in parallel. The serial output of the first shift register 19 is supplied via a serial signal transmission line 20 to a second shift register 21 constituting a serial-parallel converter. Second shift register 2
1 is output to the second bus 1 via the output bus 22.
7 is connected. The first shift register 19 and the second shift register 21 have a clock pulse generator 2
3 supplies a shift clock via a clock signal line 24.

Next, the operation of the microprocessor application apparatus thus configured will be described.

Address signals, data signals, and input / output control signals, which are input / output signals of the microprocessor 11, are supplied as parallel signals to the first bus 13 via the input / output bus 12. These parallel signals are supplied to the first shift register 19.
Is converted into a serial signal and transmitted via one serial signal transmission line 20. The signal transmitted via the serial signal transmission path 20 is converted into a parallel signal again by the second shift register 21 and supplied to the second bus 17 via the output bus 22. Therefore, the microprocessor 11, the memory device 14, the plurality of input / output devices 15, 1
6 can be transmitted by one signal line, the number of wirings can be reduced, the device can be downsized, and the number of wiring steps can be reduced. Generally, in a microprocessor application device having a complicated system configuration, a microprocessor 11 and a memory device 14, or input / output devices 15, 16
Are not necessarily arranged on the same printed circuit board but arranged on different printed circuit boards. In this case, wiring required for connection between the printed circuit boards is realized by a cable or a connector. Reducing the number of signal lines has a great effect on cost reduction and space reduction.

FIG. 2 is a block diagram more generally showing the embodiment of the present invention. In this figure, parts corresponding to the embodiment of FIG. 1 are denoted by the same reference numerals. Blocks indicated by reference numerals 19 and 21 in the figure are shown as general parallel-serial converters and serial-parallel converters including devices using ordinary memory devices in addition to shift registers. Parallel-
The input side of the serial converter 19 and the output side of the serial-parallel converter 21 are connected to signal lines of, for example, 8 bits. Block 1
Reference numerals 4 and 15 denote memory devices or input / output devices.

FIG. 3 is a block diagram showing the configuration of a parallel-serial converter 19 corresponding to the first shift register of FIG. 1 and the input / output section thereof. Similarly, portions corresponding to the embodiment of FIG. 1 are the same. Numbered. Here, on the serial output side of the parallel-serial converter 19,
Three lines of the serial output 20-1, the serial input 20-2, and the clock signal 24 are connected.

In FIG. 2, a parallel-serial converter 19 receives the output signal 12 of the processor device 11 as a parallel signal, replaces it with a time-division bit string having a width of 1 bit or a plurality of bits, and transmits the signal to a transmission line 20. Output. Further, the serial / parallel converter 21 functions to sequentially input the bit string on the transmission path 20 and return to a parallel signal.

In the parallel-serial converter 19 shown in FIG. 3, the output signal 12 of the processor device 11 is stored as a parallel signal by the parallel-serial converter 19 as a shift register. The stored signal is shifted by the clock signal 24. The signal immediately before overflow from the end of the shift register is output on the transmission line 20-1 as a serial output.

A memory device or input / output device 14,
When data is input from the device 15, the serial input is sequentially shifted by a clock signal 24 to a parallel-serial converter 19 as a shift register via a transmission path 20-2. Then, when all the signals are arranged in the shift register, they are supplied to the processor device 11 as input signals.

FIG. 4 is a block diagram showing another embodiment of the present invention.

In this embodiment, the structure shown in FIG.
, A second redundant signal generator 42 and a comparator 43 are added. First redundant signal generator 41
Is supplied with the output signal 12 of the processor device 11 as its input signal, and outputs the first redundant signal 4 as its output signal.
11 which is converted to a parallel-serial converter 19
, As its parallel input signal. That is, the first redundant signal generator 41 outputs one or more bits as a redundant signal as a result of a function operation that receives a part or all of the address bus signal, the data bus signal, and the input / output control signal. The output signal 11 including the redundant signal of the processor device 11 and the redundant signal 411 combined with the output signal 12 of the processor device 11 are supplied to the parallel-serial converter 19. The parallel output signal 21 extracted at the output side of the serial / parallel converter 21 includes a redundant signal 412 corresponding to the first redundant signal 411 in addition to the output signal 12 of the processor device 11.

The second redundant signal generator 42 receives the output signal 22 of the serial / parallel converter 21 supplied to the memory device or the input / output devices 14 and 15 as its input signal and outputs the second redundant signal as the second redundant signal. A signal 421 is generated. That is, the second redundant signal generator 42 outputs one or more bits as a function operation result to which a part or all of the address bus signal, data bus signal, and input / output control signal restored by the serial / parallel converter 21 are input. Is output as a redundant signal. Here, the first and second
It is assumed that exactly the same operation is performed in the function operations of the redundant signal generators 41 and 42.

The comparator 43 outputs the first redundant signal 412 and the second
And outputs the result to an output 431. That is, the redundant signal sent from the processor is compared with the redundant signal generated in the memory device or the input / output device.

The operation of the microprocessor application apparatus having the above configuration will be described.

As described above, the first redundant signal generator 4
The first and second redundant signal generators 42 generate the same function.
That is, the relationship between the output signal 12 of the processor device and the first redundant signal 411 is the same as the relationship between the input / output signal 22 of the memory device or the input / output device and the second redundant signal 421. On the other hand, the restored first redundant signal 412 is the processor device 1 if there is no disturbance such as noise or a device failure.
It has the same value as the first redundant signal 411 on the first side. That is, the redundant signal 412 and the redundant signal 421 are equal, and the comparison result output 431 has a value indicating that the signal values match.

Conversely, a disturbance or device failure is caused by the redundant signal 412.
Or an abnormality of the input / output signal 22 of the memory device or the input / output device, which causes a mismatch between the redundant signal 412 and the redundant signal 421. As a result, the comparison result output 43
1 is a value indicating a mismatch. The comparison result output 431 can be used as an indication of mismatch to the outside or an abnormality detection signal returned to the processor device 11.

As described above, in this embodiment, a signal having a wide bit width can be transmitted to a transmission path having a narrow bit width in a time-division manner. It takes a long time. Given a disturbance that occurs at a particular moment, such a configuration increases the probability of being affected by data transmission. However, the present embodiment has an effect of improving the reliability in such a case.

FIGS. 5 and 6 are block diagrams showing still another embodiment of the microprocessor application device of the present invention. In the embodiments described above, the bit width of the input / output signal 12 of the processor device 11 and the bit width of the input / output signal 22 of the memory device or the input / output device are the same. I have. Accordingly, the parallel-serial converter 19 and the serial-
The parallel converter 21 also has the same basic structure but a different configuration scale.

In the embodiment shown in FIG. 5, information to be transmitted / received by the processor device 11 is stored in the memory device or the input / output device 1.
In steps 4 and 15, the data is transmitted and received in a plurality of times. Alternatively, in the embodiment of FIG. 6, multiple transmissions and receptions of the processor device 11 correspond to one transmission and reception of the memory device or the input / output devices 14 and 15.

According to such an embodiment, when the width of the input / output signals of the processor device 11 and the memory or the input / output devices 14 and 15 is different, the bit width of the information is converted while suppressing an increase in the amount of hardware. There is an effect that can be done.

FIG. 7 is a block diagram showing still another embodiment of the microprocessor application device of the present invention. In this embodiment, an encoding device 61 and a decoding device 62 are added to the configuration shown in FIG. Encoding device 6
The input side of 1 is connected to the input / output signal 12 of the processor device 11, and the output side is connected to the output signal line 611 for compressing the input / output signal 12 into a signal having a small number of bits and outputting the signal. The decoding device 62 receives the output signal 211 of the serial-parallel conversion device 21 as an input signal,
These are decoded to make the input / output signal 22 having a larger number of bits.
Convert to The input / output signal 22 is supplied to the memory or the input / output devices 14 and 15.

The encoding device 61 receives the input / output signal 12 of the processor device 11 as input, performs encoding, and outputs a compressed input / output signal 611 of the processor device. The decoding device 62 receives the compressed input / output signal 211 of the memory device or the input / output device, performs decoding, and outputs the input / output signal 22 of the memory device or the input / output device.

FIG. 2 shows another configuration of this embodiment.
Is substantially the same as the configuration of the microprocessor application device shown in FIG. 1, but the number of bits of the input signal of the parallel-serial converter 19 and the serial-parallel converter 21
2 in that the number of bits of the output signal is smaller than the number of bits of the input / output signal of the processor device 11 or the memory or the input / output devices 14 and 15.

According to this embodiment, since information is compressed by encoding, the amount of information passing through the transmission path 20 is reduced. Therefore, there is an effect that the information transmission time is shortened or the amount of information transmitted at the same time is increased.

[0038]

According to the present invention, together with a data signal,
By performing parallel-serial conversion including address signals, the amount of signal lines connected from the processor device to the memory device or the input / output device is reduced, and information between many memory devices or the input / output device is reduced by using fewer signal lines. Exchange becomes possible.

Further, according to the present invention, by adding a redundant signal to the information from the processor device, there is an effect that it is possible to determine whether or not the information has been correctly transmitted on the memory device or the input / output device side.

Further, according to the present invention, when the data bus on the processor device side is large and the data bus on the memory device or input / output device side is small, or vice versa, the hardware required for bus width conversion can be reduced. This has the effect.

Further, according to the present invention, since the amount of information is reduced by encoding information to be transmitted, the number of transmissions or the transmission time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a microprocessor application device according to the present invention.

FIG. 2 is a block diagram showing a more general configuration of a microprocessor application device according to the present invention.

FIG. 3 is a block diagram showing a configuration of a part of the microprocessor application device shown in FIG. 2 in more detail;

FIG. 4 is a block diagram showing another embodiment of the microprocessor application device of the present invention.

FIG. 5 is a block diagram showing still another embodiment of the microprocessor application device of the present invention.

FIG. 6 is a block diagram showing still another embodiment of the microprocessor application device of the present invention.

FIG. 7 is a block diagram showing still another embodiment of the microprocessor application device of the present invention.

[Explanation of symbols]

Reference Signs List 11 microprocessor 12 input / output bus 13 first bus 14 memory device 15 input / output device 16 input / output device 17 second bus 18 input bus 19 first shift register (parallel-serial conversion device) 20 serial signal transmission path 21 Second shift register (serial-parallel converter) 22 output bus 23 clock pulse generator 24 clock signal line 41 first redundant signal generator 42 second redundant signal generator 43 comparator 61 encoding device 62 decoding apparatus

Claims (5)

[Claims] A microprocessor device is connected, a first bus including at least an address signal and a data signal bus of input / output signals of the microprocessor device, and a parallel bus connected to the first bus. A serial conversion device, a serial signal transmission line for transmitting an output signal of the parallel-serial conversion device, a serial-parallel conversion device to which a signal of the serial signal transmission line is supplied, and a parallel connection of the serial-parallel conversion device. A microprocessor application device, comprising: a signal line connected thereto; and a second bus connected to a memory device or an input / output device. 2. The microprocessor application device is supplied with the address signal and the data signal transmitted by the first bus, and generates a first redundant signal having a predetermined functional relationship with these signals. A first redundant signal generating means for supplying this as an additional input signal of the parallel-serial conversion device, and the address signal and the data signal among the parallel output signals of the serial-parallel conversion device, A second redundant signal generating means for generating a second redundant signal having a predetermined functional relationship with respect to these signals; and a second redundant signal generated by the second redundant signal generating means. 2. The microcomputer according to claim 1, further comprising: means for comparing with the first redundant signal in a parallel output signal of the serial-parallel converter. Processor application equipment. 3. The parallel-serial converter according to claim 1, wherein the number of bits of the parallel input signal of the parallel-serial converter is different from the number of bits of the parallel output signal of the serial-parallel converter. Means for converting one transmission / reception to a plurality of transmissions / receptions of the serial-parallel conversion device or a plurality of transmissions / receptions of the parallel-serial conversion device to one transmission / reception of the serial-parallel conversion device. The microprocessor application device according to claim 1, wherein: 4. The microprocessor application device is supplied with the address signal and the data signal transmitted by the first bus, converts these signals into an output signal having a smaller number of bits, and converts the output signal into the parallel signal. Encoding means for supplying an input signal to the serial conversion apparatus, and decoding which is supplied with an output signal of the serial-parallel conversion apparatus and performs reverse conversion on the encoding means and supplies the same to the second bus 2. The microprocessor application device according to claim 1, further comprising: a conversion unit. 5. A microprocessor application device comprising a plurality of printed circuit boards on which circuits and components are wired and mounted, wherein at least an address signal bus and a data signal bus are wired on a first board of the plurality of printed boards. A first bus including at least one of a plurality of printed circuit boards, a second bus including at least an address signal bus and a data signal bus, and a second bus including at least an address signal bus and a data signal bus. A microprocessor application comprising: connected first and second parallel-serial converters; and a serial signal transmission line interconnecting the first and second parallel-serial converters. apparatus.