JPH0744473A - Signal transmission reception circuit - Google Patents
Signal transmission reception circuitInfo
- Publication number
- JPH0744473A JPH0744473A JP5189594A JP18959493A JPH0744473A JP H0744473 A JPH0744473 A JP H0744473A JP 5189594 A JP5189594 A JP 5189594A JP 18959493 A JP18959493 A JP 18959493A JP H0744473 A JPH0744473 A JP H0744473A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- side circuit
- voltage
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は信号授受回路に関し、例
えば、通信機や計算機等に使用されている2個の構成要
素間で複数の信号を並列に授受するための入出力構成に
適用し得るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission / reception circuit, and is applied to, for example, an input / output configuration for exchanging a plurality of signals in parallel between two constituent elements used in a communication device or a computer. I will get it.
【0002】[0002]
【従来の技術】通信機や計算機の動作の高速化に伴い、
複数の構成要素間で授受する信号の速度を高速にするこ
とも求められ、複数の構成要素間で信号を並列化して授
受することも広く行なわれている。例えば、2個の集積
回路間(や集積回路内の2構成要素間や2個のプリント
配線基板間)においても、1単位信号(例えばバイトや
ワード)を複数(例えば8本)の信号線によって並列に
授受することが行なわれる。2. Description of the Related Art As communication devices and computers operate faster,
It is also required to increase the speed of signals transmitted and received between a plurality of constituent elements, and it is widely practiced to parallelize and transmit a signal between a plurality of constituent elements. For example, even between two integrated circuits (or between two components in the integrated circuit or between two printed wiring boards), one unit signal (for example, byte or word) is transmitted by a plurality of (for example, eight) signal lines. Transfers are made in parallel.
【0003】従来、部分又は全体が集積回路で構成され
ている送信側(出力側)回路から、部分又は全体が集積
回路で構成されている受信側(入力側)回路に、複数の
信号を並列に授受する方法としては、以下のような方法
があった。Conventionally, a plurality of signals are paralleled from a transmission side (output side) circuit, which is partially or wholly formed by an integrated circuit, to a reception side (input side) circuit, which is partially or entirely formed by an integrated circuit. The following methods were available for sending and receiving to and from.
【0004】第1の方法は、TTL論理集積回路(例え
ばテキサスインスツルメント社製SN74LS244 )やECL
論理集積回路(例えばモトローラ社製MC10176 )につい
て多く適用されている方法であり、1本の信号線の電位
が受信側回路の基準電位に対して高いか低いかによって
各信号をそれぞれ伝達する方法である。第2の方法は、
差動入力型ECL論理集積回路(例えばモトローラ社製
MC10116 )について多く適用されている方法であり、2
本の信号線を対とし、この2本の信号線の電位差によっ
て並列信号の各信号をそれぞれ伝達する方法である。The first method is a TTL logic integrated circuit (for example, SN74LS244 manufactured by Texas Instruments) or ECL.
This method is often applied to logic integrated circuits (for example, MC10176 manufactured by Motorola Co.), and each signal is transmitted depending on whether the potential of one signal line is higher or lower than the reference potential of the receiving side circuit. is there. The second method is
Differential input type ECL logic integrated circuit (for example, manufactured by Motorola)
MC10116), which is a method that is often applied.
This is a method in which two signal lines are paired and each of the parallel signals is transmitted by the potential difference between the two signal lines.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、従来の
第1の複数信号授受方法は、1本の信号線によって各信
号を伝送するため、信号線に重畳される雑音や受信側回
路の基準電位に重畳される雑音に対して弱いという課題
を有する。特に、高速化を実現するために信号振幅を小
さく選定した場合には、雑音の影響を受け易く、伝送距
離を短くしなければならないという制約が生じていた。However, according to the first conventional method of transmitting and receiving a plurality of signals, since each signal is transmitted by one signal line, the noise superimposed on the signal line and the reference potential of the receiving side circuit are reduced. It has a problem that it is weak against the superimposed noise. In particular, when the signal amplitude is selected to be small in order to realize high speed, it is susceptible to noise, and there is a restriction that the transmission distance must be shortened.
【0006】これに対して、第2の複数信号授受方法
は、1対の信号線の電位差として各信号を伝送するの
で、1対の信号線に共通に重畳される雑音に対して強
く、その結果、高速化を実現するために信号振幅を小さ
くする場合には有利な方法である。しかしながら、この
第2の複数信号授受方法では、信号線が授受する信号数
の2倍必要であり、信号数が多ければ多いほど信号線数
も多くなる。その結果、信号線の引き回しが繁雑になり
易い。また、送信側回路や受信側回路の入出力端子数を
増大させ、これら回路(例えば集積回路パッケージ)の
物理的大きさを大きくしてしまい、さらに、入出力端子
が多い分だけ消費電力も増大させる。On the other hand, the second method of transmitting and receiving a plurality of signals transmits each signal as the potential difference between the pair of signal lines, and therefore is strong against the noise commonly superimposed on the pair of signal lines. As a result, this is an advantageous method when the signal amplitude is reduced in order to realize high speed. However, in the second method of transmitting and receiving a plurality of signals, the number of signals transmitted and received by the signal lines is required to be twice, and the larger the number of signals, the larger the number of signal lines. As a result, the routing of the signal line tends to be complicated. In addition, the number of input / output terminals of the transmitting side circuit and the receiving side circuit is increased, and the physical size of these circuits (for example, an integrated circuit package) is increased, and the power consumption is increased due to the large number of input / output terminals. Let
【0007】本発明は、以上の点を考慮してなされたも
のであり、送信側回路や受信側回路間で複数の信号を雑
音の影響をほとんど受けずに並列にしかも少ない信号線
で授受することができる信号授受回路を提供しようとし
たものである。The present invention has been made in consideration of the above points, and transmits and receives a plurality of signals in parallel between a transmitting side circuit and a receiving side circuit with little influence of noise and with a small number of signal lines. It is an object of the present invention to provide a signal transmitting / receiving circuit capable of performing the above.
【0008】[0008]
【課題を解決するための手段】かかる課題を解決するた
め、本発明においては、複数の信号線で接続されている
送信側回路及び受信側回路間で複数の信号を並列に授受
する信号授受回路を、以下のように構成した。In order to solve such a problem, in the present invention, a signal transfer circuit for transferring a plurality of signals in parallel between a transmitting side circuit and a receiving side circuit connected by a plurality of signal lines. Was configured as follows.
【0009】すなわち、送信側回路及び受信側回路間
を、授受する信号数より1だけ多い信号線で接続する。
そして、送信側回路に、対応する信号線を入力信号に応
じて駆動する信号数に対応した複数の出力駆動回路と、
各出力駆動回路からの信号電圧と所定の電圧関係がある
基準電圧を発生して1個の信号線に出力する基準電圧発
生回路とを設けた。また、受信側回路に、1個の信号線
からの基準電圧と、対応する出力駆動回路に接続された
信号線からの信号電圧とを比較する電圧比較器を信号数
に対応した数だけ設けた。That is, the transmission side circuit and the reception side circuit are connected by a signal line that is larger than the number of signals to be transmitted and received by one.
Then, the transmission side circuit, a plurality of output drive circuits corresponding to the number of signals for driving the corresponding signal line according to the input signal,
A reference voltage generating circuit for generating a reference voltage having a predetermined voltage relationship with the signal voltage from each output drive circuit and outputting the reference voltage to one signal line is provided. Further, the receiving side circuit is provided with a number of voltage comparators for comparing the reference voltage from one signal line with the signal voltage from the signal line connected to the corresponding output drive circuit, in a number corresponding to the number of signals. .
【0010】[0010]
【作用】本発明において、送信側回路の各出力駆動回路
は入力された信号に応じて対応する信号線を駆動し、基
準電圧発生回路は各出力駆動回路からの信号電圧と所定
の電圧関係がある基準電圧を発生して1個の信号線に出
力する。受信側回路において、電圧比較器は、1個の信
号線からの基準電圧と、対応する出力駆動回路に接続さ
れた信号線からの信号電圧とを比較することで対応する
出力駆動回路に入力された信号を再生する。In the present invention, each output drive circuit of the transmission side circuit drives the corresponding signal line in accordance with the input signal, and the reference voltage generation circuit has a predetermined voltage relationship with the signal voltage from each output drive circuit. It generates a certain reference voltage and outputs it to one signal line. In the receiving side circuit, the voltage comparator is inputted to the corresponding output drive circuit by comparing the reference voltage from one signal line with the signal voltage from the signal line connected to the corresponding output drive circuit. Signal is played back.
【0011】これにより、複数の信号を雑音の影響をほ
とんど受けずに並列にしかも少ない信号線で授受するこ
とができるようになる。As a result, a plurality of signals can be transmitted / received in parallel and with a small number of signal lines with little influence of noise.
【0012】[0012]
【実施例】以下、本発明を、デジタル信号の授受回路に
適用した一実施例を図面を参照しながら詳述する。ここ
で、図1がこの実施例の構成を示すブロック図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital signal transfer circuit will be described in detail below with reference to the drawings. Here, FIG. 1 is a block diagram showing the configuration of this embodiment.
【0013】図1において、この実施例は、4個のデジ
タル信号A、B、C、Dを送信側回路(出力側回路)1
が受信側回路(入力側回路)2に伝送し、受信側回路2
がそれぞれデジタル信号E(A)、F(B)、G
(C)、H(D)として受信するものである。In FIG. 1, in this embodiment, four digital signals A, B, C and D are sent to a transmitting side circuit (output side circuit) 1
Is transmitted to the receiving side circuit (input side circuit) 2, and the receiving side circuit 2
Are digital signals E (A), F (B), G
(C) and H (D).
【0014】送信側回路1は、各送信デジタル信号A、
B、C、Dにそれぞれ対応した出力駆動回路4、5、
6、7と、これら出力駆動回路4〜7の出力電圧の基準
を与える基準電圧発生回路3とからなっている。一方、
受信側回路2は、4個の電圧比較器8、9、10、11
を有する。The transmission side circuit 1 is configured to transmit each transmission digital signal A,
Output drive circuits 4, 5, respectively corresponding to B, C, D
6 and 7, and a reference voltage generation circuit 3 which gives a reference for the output voltage of these output drive circuits 4 to 7. on the other hand,
The receiving side circuit 2 has four voltage comparators 8, 9, 10, 11
Have.
【0015】出力駆動回路4の出力端子は、自己が搭載
されている送信側回路1の出力端子12を介して信号線
22の一端に接続されており、信号線22の他端は、受
信側回路2の入力端子17を介して電圧比較器8の比較
入力端子に接続されている。同様に、他の各出力駆動回
路5、6、7の出力端子は、送信側回路1の対応する出
力端子13、14、15を介して対応する信号線23、
24、25の一端に接続されており、信号線23、2
4、25の他端は、受信側回路2の対応する入力端子1
8、19、20を介して対応する電圧比較器9、10、
11の比較入力端子に接続されている。The output terminal of the output drive circuit 4 is connected to one end of the signal line 22 via the output terminal 12 of the transmission side circuit 1 on which the output drive circuit 4 is mounted, and the other end of the signal line 22 is connected to the reception side. It is connected to the comparison input terminal of the voltage comparator 8 via the input terminal 17 of the circuit 2. Similarly, the output terminals of the other output drive circuits 5, 6, and 7 are connected via the corresponding output terminals 13, 14, and 15 of the transmission side circuit 1 to the corresponding signal lines 23,
The signal lines 23, 2 are connected to one end of 24, 25.
The other ends of 4 and 25 are the corresponding input terminals 1 of the receiving side circuit 2.
Via the corresponding voltage comparators 9, 10,
It is connected to 11 comparison input terminals.
【0016】基準電圧発生回路3の出力端子は、上述し
たように、出力駆動回路4〜7の基準入力端子に接続さ
れていると共に、送信側回路1の出力端子16を介して
信号線26の一端に接続されており、信号線26の他端
は、受信側回路2の入力端子21を介して全ての電圧比
較器8〜11の基準入力端子に接続されている。As described above, the output terminal of the reference voltage generating circuit 3 is connected to the reference input terminals of the output drive circuits 4 to 7, and the signal line 26 is connected via the output terminal 16 of the transmitting side circuit 1. It is connected to one end, and the other end of the signal line 26 is connected to the reference input terminals of all the voltage comparators 8 to 11 via the input terminal 21 of the receiving side circuit 2.
【0017】以上のように、この実施例においては、送
信側回路1及び受信側回路2は、伝送されるデジタル信
号A(E)、B(F)、C(G)、D(H)の数より1
だけ多い5本の信号線22〜26によって接続されてい
る。As described above, in this embodiment, the transmission side circuit 1 and the reception side circuit 2 receive the transmitted digital signals A (E), B (F), C (G), and D (H). 1 from the number
Only five signal lines 22 to 26 are connected.
【0018】次に、以上の構成を有する実施例の信号授
受回路の動作を説明する。なお、ここでは、信号線(伝
送路)22〜25のレベルがECL集積回路の標準レベ
ルに従うとして説明する。Next, the operation of the signal transmission / reception circuit of the embodiment having the above configuration will be described. Note that the levels of the signal lines (transmission paths) 22 to 25 will be described here as conforming to the standard level of the ECL integrated circuit.
【0019】各出力駆動回路4、5、6、7には、基準
電圧発生回路3から例えば−1.3Vである基準電圧が
与えられており、各出力駆動回路4、5、6、7は、こ
の基準電圧を利用して、入力された対応するデジタル信
号A、B、C、Dが論理”1”の場合には対応する出力
端子12、13、14、15に−0.9Vの信号電圧を
出力し、他方、入力された対応するデジタル信号A、
B、C、Dが論理”0”の場合には対応する出力端子1
2、13、14、15に−1.7Vの信号電圧を出力す
る。基準電圧発生回路3が発生した−1.3Vの基準電
圧は、出力端子16に出力される。A reference voltage of, for example, -1.3 V is applied from the reference voltage generating circuit 3 to each of the output drive circuits 4, 5, 6, and 7, and each of the output drive circuits 4, 5, 6, 7 is By using this reference voltage, when the corresponding digital signals A, B, C, D inputted are logic "1", the signals of -0.9V are outputted to the corresponding output terminals 12, 13, 14, 15. Outputs a voltage, while the corresponding digital signal A input,
When B, C and D are logic "0", the corresponding output terminal 1
A signal voltage of -1.7 V is output to 2, 13, 14, and 15. The −1.3 V reference voltage generated by the reference voltage generation circuit 3 is output to the output terminal 16.
【0020】送信側回路1の出力端子12、13、1
4、15の電圧(授受信号対応電圧)はそれぞれ、信号
線22、23、24、25、及び、受信側回路2の入力
端子17、18、19、20を介して、各電圧比較器
8、9、10、11の比較入力端子に印加される。一
方、送信側回路1の出力端子16の電圧(基準電圧)
は、信号線26、受信側回路2の入力端子21を順次介
して、全ての電圧比較器8、9、10、11の基準入力
端子に印加される。Output terminals 12, 13, 1 of the transmission side circuit 1
The voltages of 4 and 15 (voltages corresponding to transmission / reception signals) are respectively transmitted through the signal lines 22, 23, 24, 25 and the input terminals 17, 18, 19, 20 of the receiving side circuit 2 to the voltage comparators 8, It is applied to the comparison input terminals of 9, 10, and 11. On the other hand, the voltage of the output terminal 16 of the transmission side circuit 1 (reference voltage)
Is applied to the reference input terminals of all the voltage comparators 8, 9, 10, 11 via the signal line 26 and the input terminal 21 of the receiving side circuit 2 in order.
【0021】各電圧比較器8、9、10、11はそれぞ
れ、例えば、比較入力端子に印加された電圧(授受信号
対応電圧:−0.9V又は−1.7V)が基準入力端子
に印加された電圧(基準電圧:−1.3V)より大きい
ときに、論理”1”のデジタル信号E、F、G、Hを受
信デジタル信号として出力し、比較入力端子に印加され
た電圧が基準入力端子に印加された電圧より小さいとき
に、論理”0”のデジタル信号E、F、G、Hを受信デ
ジタル信号として出力する。In each of the voltage comparators 8, 9, 10 and 11, for example, the voltage applied to the comparison input terminal (the voltage corresponding to the transfer signal: -0.9V or -1.7V) is applied to the reference input terminal. Output voltage (reference voltage: -1.3V), the logic "1" digital signals E, F, G, and H are output as received digital signals, and the voltage applied to the comparison input terminal is the reference input terminal. When the voltage is smaller than the voltage applied to, the digital signals E, F, G, and H of logic "0" are output as reception digital signals.
【0022】例えば、送信側回路1の出力駆動回路4に
論理”1”のデジタル信号Aが入力されると、出力端子
12には−0.9Vの信号電圧が出力され、この電圧が
信号線22及び受信側回路2の入力端子17を介して電
圧比較器8の比較入力端子に印加され、送信側回路1か
ら伝送されてきた基準電圧−1.3Vと比較され、電圧
比較器8からはデジタル信号Aと同一論理”1”のデジ
タル信号Eが出力される。For example, when a digital signal A of logic "1" is input to the output drive circuit 4 of the transmission side circuit 1, a signal voltage of -0.9V is output to the output terminal 12, and this voltage is output to the signal line. 22 and the input terminal 17 of the receiving side circuit 2 are applied to the comparison input terminal of the voltage comparator 8 and are compared with the reference voltage −1.3 V transmitted from the transmitting side circuit 1, and from the voltage comparator 8. A digital signal E having the same logic "1" as the digital signal A is output.
【0023】なお、この伝送の際に、信号線22及び2
6に雑音が混入されたとしても、これら信号線22及び
26には実際上ほぼ同一に雑音が混入され、これら信号
線22及び26の電位差は雑音が混入されても、されな
い場合とほぼ同一である。従って、電圧比較器8からは
雑音が混入されない場合と同一論理のデジタル信号Eを
出力する。During this transmission, the signal lines 22 and 2
Even if noise is mixed in 6, noise is mixed in the signal lines 22 and 26 substantially in the same manner, and the potential difference between the signal lines 22 and 26 is substantially the same as the case where noise is mixed in. is there. Therefore, the voltage comparator 8 outputs the digital signal E having the same logic as that when noise is not mixed.
【0024】以上のようにして、送信側回路1の複数の
デジタル信号A、B、C、Dに対応して、受信側回路2
においてはデジタル信号E、F、G、Hが再生される。As described above, the receiving side circuit 2 corresponds to the plurality of digital signals A, B, C and D of the transmitting side circuit 1.
In, the digital signals E, F, G and H are reproduced.
【0025】従って、上記実施例によれば、本来の授受
信号A〜Dに加えて、送信側回路1から受信側回路2に
基準電圧(参照信号)を送信するようにしたので、従来
に比べて雑音(送信側及び受信側間のアース電位差を含
む)に影響されずに本来の授受信号を伝送することがで
き、受信デジタル信号E〜Hを利用する回路部分の誤動
作等を未然に防止することができる。Therefore, according to the above-described embodiment, the reference voltage (reference signal) is transmitted from the transmission side circuit 1 to the reception side circuit 2 in addition to the original transmission / reception signals A to D. The original transmission / reception signal can be transmitted without being affected by noise (including the ground potential difference between the transmission side and the reception side), and malfunctions of the circuit portion using the reception digital signals E to H can be prevented in advance. be able to.
【0026】因に、従来の第1の複数信号授受方法で
は、信号線に混入した雑音や、送信側回路及び受信側回
路間のアース電位差をキャンセルすることができなかっ
たが、この実施例によれば、電圧比較により信号線に混
入した雑音をキャンセルでき、また、基準電圧の送信に
よって送信側回路及び受信側回路間のアース電位差が問
題とならなくなる。By the way, in the first conventional method of transmitting and receiving a plurality of signals, the noise mixed in the signal line and the ground potential difference between the transmitting side circuit and the receiving side circuit could not be canceled. According to this, the noise mixed in the signal line can be canceled by the voltage comparison, and the ground potential difference between the transmission side circuit and the reception side circuit does not become a problem due to the transmission of the reference voltage.
【0027】また、上記実施例によれば、少ない信号線
数によって上述の効果(伝送品質の向上)を得ている。
従来の第2の複数信号授受方法でも、伝送品質の向上と
いう効果が得られる。しかし、従来の第2の複数信号授
受方法で例えば4個の信号を授受するためには8本の信
号線が必要であるが、この実施例では上述のように5本
の信号線で済む。その結果、信号線の引き回しが簡単に
なり、また、送信側回路や受信側回路の入出力端子数を
減少できてその回路構成を簡単、小型なものにでき、消
費電力も少なくできる。Further, according to the above embodiment, the above effect (improvement of transmission quality) is obtained with a small number of signal lines.
The second conventional multi-signal transmission / reception method also has the effect of improving the transmission quality. However, although eight signal lines are required for transmitting / receiving, for example, four signals in the second conventional plural signal transmitting / receiving method, this embodiment requires only five signal lines as described above. As a result, it is possible to easily route the signal line, reduce the number of input / output terminals of the transmitting side circuit and the receiving side circuit, simplify the circuit structure, and reduce the power consumption.
【0028】なお、上記実施例においては、授受する信
号数が4個であるものを示したが、8個、16個等の任
意の信号数に本発明は対応できる。また、信号レベルが
ECLのほかTTL等の他のデジタル信号レベルでも同
様に本発明を適用できる。Although the number of signals to be transmitted and received is four in the above embodiment, the present invention can be applied to any number of signals such as eight and sixteen. Further, the present invention can be similarly applied to the case where the signal level is not only ECL but also another digital signal level such as TTL.
【0029】また、上記実施例においては、授受する信
号がデジタル信号の場合を示したが、アナログ信号でも
本発明の技術思想を適用できる。この場合には、出力駆
動回路(4〜7)として直線的な入出力特性を有する増
幅器を適用し、電圧比較器(8〜11)の代りに差動増
幅器(なお、特許請求の範囲ではこの差動増幅器も電圧
比較器と呼んでいる)を適用すれば良い。Further, although the case where the signal to be transmitted and received is a digital signal has been shown in the above embodiment, the technical idea of the present invention can be applied to an analog signal. In this case, an amplifier having a linear input / output characteristic is applied as the output drive circuit (4 to 7), and a differential amplifier (in the claims, this is used instead of the voltage comparator (8 to 11)). The differential amplifier is also called a voltage comparator).
【0030】さらに、上記実施例においては、送信側回
路1及び受信側回路2と、集積回路との関係の関係を言
及しなかったが、以下のような種々の関係で信号授受回
路を実現しても良い。Further, in the above embodiment, the relationship between the transmitting side circuit 1 and the receiving side circuit 2 and the integrated circuit was not mentioned, but the signal transmitting / receiving circuit is realized by various relationships as follows. May be.
【0031】(1) 基準電圧発生回路3や出力駆動回路4
〜7や電圧比較器8〜11の部分構成要素が個別の集積
回路チップで実現されていても良い。このような場合、
送信側回路1及び受信側回路2は、例えばプリント配線
基板(の一部)が相当する。 (2) 送信側回路1全体及び受信側回路2全体がそれぞ
れ、集積回路チップで構成されていても良い。(3) 送信
側回路1が集積回路チップの出力部に設けられ、受信側
回路2が他の集積回路チップの入力部に設けられたもの
であっても良い。(1) Reference voltage generation circuit 3 and output drive circuit 4
7 and the partial components of the voltage comparators 8 to 11 may be realized by individual integrated circuit chips. In such cases,
The transmitter circuit 1 and the receiver circuit 2 correspond to (a part of) a printed wiring board, for example. (2) The entire transmitting side circuit 1 and the entire receiving side circuit 2 may each be configured by an integrated circuit chip. (3) The transmitting side circuit 1 may be provided in the output section of the integrated circuit chip, and the receiving side circuit 2 may be provided in the input section of another integrated circuit chip.
【0032】集積回路の利用態様(2) 及び(3) の場合、
送信側回路1において、基準電圧発生回路3から出力駆
動回路4、5、6、7に基準電圧を与えることは必ずし
も必要ではなく、集積回路上の素子定数が揃うことを利
用して、出力端子16の基準電圧(参照信号)と出力端
子12、13、14、15の出力電圧の関係の精度を保
つことは容易に実行できる。In the cases (2) and (3) of using the integrated circuit,
In the transmission side circuit 1, it is not always necessary to apply the reference voltage from the reference voltage generation circuit 3 to the output drive circuits 4, 5, 6, and 7, and it is possible to utilize the fact that the element constants on the integrated circuit are uniform, It is easy to maintain the accuracy of the relationship between the 16 reference voltages (reference signals) and the output voltages of the output terminals 12, 13, 14, and 15.
【0033】集積回路実現上、入出力端子数が少ないこ
とが望ましいが、本発明によれば、かかる要求に答える
ことができる。In order to realize an integrated circuit, it is desirable that the number of input / output terminals is small, but the present invention can meet such a requirement.
【0034】なお、通信機や計算機等の構成要素間で信
号を並列化して伝送する装置を意識して本発明がなされ
たものであるが、本発明は、互いに無関係な複数の信号
を並列に授受するものにも適用し得るものである。Although the present invention has been made in consideration of a device for parallelizing and transmitting a signal between constituent elements such as a communication device and a computer, the present invention parallelizes a plurality of unrelated signals. It can also be applied to what is given and received.
【0035】図1は、最も単純な構成を示したものであ
り、本発明はこれに限定されない。例えば、上記実施例
においては、受信側回路2が1個のものを示したが、信
号線22〜26を分岐させて、1個の送信側回路1から
複数の受信側回路2に信号を伝送する場合にも本発明を
適用できる。また、1個の送信側回路1及び受信側回路
2が、基準電圧を異にする複数組の出力駆動回路や電圧
比較器を備えていても良く、この場合には基準電圧もそ
の数だけ伝送することを要する。この場合は、図1に示
した構成が複数存在するのと等価であり、特徴はやはり
図1で示されている。FIG. 1 shows the simplest configuration, and the present invention is not limited to this. For example, in the above embodiment, one receiving side circuit 2 is shown, but the signal lines 22 to 26 are branched to transmit a signal from one transmitting side circuit 1 to a plurality of receiving side circuits 2. The present invention can be applied to the case. Further, one transmission side circuit 1 and one reception side circuit 2 may be provided with a plurality of sets of output drive circuits and voltage comparators having different reference voltages. In this case, the reference voltage is also transmitted by that number. Need to do. In this case, it is equivalent to having a plurality of configurations shown in FIG. 1, and the features are also shown in FIG.
【0036】[0036]
【発明の効果】以上のように、本発明によれば、送信側
回路において、各出力駆動回路が入力された信号に応じ
て対応する信号線を駆動し、基準電圧発生回路が各出力
駆動回路からの信号電圧と所定の電圧関係がある基準電
圧を発生して1個の信号線に出力し、受信側回路におい
て、各電圧比較器が、1個の信号線からの基準電圧と、
対応する出力駆動回路に接続された信号線からの信号電
圧とを比較することで対応する出力駆動回路に入力され
た信号を再生するようにしたので、複数の信号を雑音の
影響をほとんど受けずに並列にしかも少ない信号線で送
信側回路及び受信側回路間で授受することができる。As described above, according to the present invention, in the transmission side circuit, each output drive circuit drives the corresponding signal line according to the input signal, and the reference voltage generation circuit causes each output drive circuit to operate. Generates a reference voltage having a predetermined voltage relationship with the signal voltage from and outputs to one signal line, and in the receiving side circuit, each voltage comparator has a reference voltage from one signal line,
Since the signal input to the corresponding output drive circuit is reproduced by comparing it with the signal voltage from the signal line connected to the corresponding output drive circuit, multiple signals are hardly affected by noise. It is possible to transmit and receive between the transmitting side circuit and the receiving side circuit in parallel with a small number of signal lines.
【図1】実施例の構成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of an embodiment.
1…送信側回路、2…受信側回路、3…基準電圧発生回
路、4〜7…出力駆動回路、8〜11…電圧比較器、2
2〜26…信号線。1 ... Transmission side circuit, 2 ... Reception side circuit, 3 ... Reference voltage generation circuit, 4-7 ... Output drive circuit, 8-11 ... Voltage comparator, 2
2 to 26 ... Signal lines.
Claims (1)
路及び受信側回路間で、複数の信号を並列に授受する信
号授受回路において、 上記送信側回路及び上記受信側回路間を、授受する信号
数より1だけ多い信号線で接続すると共に、 上記送信側回路に、 上記信号線を入力信号に応じて駆動する信号数に対応し
た複数の出力駆動回路と、上記各出力駆動回路からの信
号電圧と所定の電圧関係がある基準電圧を発生して1個
の上記信号線に出力する基準電圧発生回路とを設け、 上記受信側回路に、 1個の上記信号線からの基準電圧と、対応する上記出力
駆動回路に接続された上記信号線からの信号電圧とを比
較する電圧比較器を信号数に対応した数だけ設けたこと
を特徴とする信号授受回路。1. A signal transfer circuit for transferring a plurality of signals in parallel between a transmission side circuit and a reception side circuit connected by a plurality of signal lines, wherein the transmission side circuit and the reception side circuit are exchanged. The number of signals is one more than the number of signals to be connected, and a plurality of output drive circuits corresponding to the number of signals that drive the signal lines according to input signals are connected to the transmission side circuit, A reference voltage generating circuit for generating a reference voltage having a predetermined voltage relationship with a signal voltage and outputting the reference voltage to one of the signal lines is provided, and the reference voltage from one of the signal lines is provided in the reception side circuit, 2. A signal transfer circuit, characterized in that a number of voltage comparators for comparing a signal voltage from the signal line connected to the corresponding output drive circuit are provided in a number corresponding to the number of signals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5189594A JPH0744473A (en) | 1993-07-30 | 1993-07-30 | Signal transmission reception circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5189594A JPH0744473A (en) | 1993-07-30 | 1993-07-30 | Signal transmission reception circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0744473A true JPH0744473A (en) | 1995-02-14 |
Family
ID=16243933
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5189594A Pending JPH0744473A (en) | 1993-07-30 | 1993-07-30 | Signal transmission reception circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0744473A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7167536B2 (en) | 2001-05-30 | 2007-01-23 | Elpida Memory, Inc. | Signal receiving circuit, semiconductor device and system |
KR100713784B1 (en) * | 1999-07-14 | 2007-05-07 | 후지쯔 가부시끼가이샤 | Receiver, transceiver circuit, signal transmission method and signal transmission system |
WO2021229716A1 (en) * | 2020-05-13 | 2021-11-18 | 株式会社ソシオネクスト | Interface circuit and interface device |
-
1993
- 1993-07-30 JP JP5189594A patent/JPH0744473A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100713784B1 (en) * | 1999-07-14 | 2007-05-07 | 후지쯔 가부시끼가이샤 | Receiver, transceiver circuit, signal transmission method and signal transmission system |
US7167536B2 (en) | 2001-05-30 | 2007-01-23 | Elpida Memory, Inc. | Signal receiving circuit, semiconductor device and system |
WO2021229716A1 (en) * | 2020-05-13 | 2021-11-18 | 株式会社ソシオネクスト | Interface circuit and interface device |
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