CN118132497A - Method for controlling command transmission and synchronous acquisition in array signal processing system - Google Patents
Method for controlling command transmission and synchronous acquisition in array signal processing system Download PDFInfo
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- CN118132497A CN118132497A CN202410340162.3A CN202410340162A CN118132497A CN 118132497 A CN118132497 A CN 118132497A CN 202410340162 A CN202410340162 A CN 202410340162A CN 118132497 A CN118132497 A CN 118132497A
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Abstract
The invention relates to the technical field of communication, in particular to a method for controlling command transmission and synchronous acquisition in an array signal processing system. The command, the trigger and the synchronization are uniformly coded into specific data to be sent out through a data line, and the data transmission is synchronized with a reference clock. Compared with the traditional method requiring multiple signals such as bus connection, triggering, synchronization and the like, the method greatly reduces the required signal lines.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a method for controlling command transmission and synchronous acquisition in an array signal processing system.
Background
Higher channel numbers are required in array signal processing systems, such as active antenna designs, massive MIMO, and advanced beamforming techniques, requiring a large number of ADC and DAC elements for synchronous input or output. Limited by board dimensions, the number of channels a single board can design is limited. In large array systems, many cards are typically required to achieve multi-channel acquisition or transmission. How to transmit instructions to the boards and ensure clock synchronization and data synchronization between the boards are key to the normal operation of the system. Conventional multi-board synchronization requires sharing of signals such as trigger signals, synchronization signals, reference clocks, etc. among boards, and command transmission is accomplished via a bus, such as the PXI/PXIE system (fig. 5).
In some applications, signals such as instructions, synchronization, etc., cannot be transferred over a system bus or more signal lines, subject to space, configuration, etc. Such as: in some systems, to ensure analog signal quality, acquisition modules are mounted close to the antenna elements, and multiple acquisition modules in a large array are dispersed near different antenna elements and cannot transmit instructions through the backplane bus. At this time, the instruction is transmitted by using a decentralized bus connection (fig. 6). In some applications, however, no more signal connections can be made due to the small space (e.g., on-board, etc.).
Disclosure of Invention
The invention provides a command transmission and synchronous acquisition control method in an array signal processing system, and provides a method for realizing command transmission and synchronization in the array signal processing system by matching a single-channel signal with a clock so as to meet the command transmission and synchronous acquisition requirements in the array signal processing system.
In order to achieve the purpose of the invention, the technical scheme adopted is as follows: a command transmission and synchronous acquisition control method in an array signal processing system comprises the following steps:
S1, a reference clock of a main control module is driven to generate multiple paths of reference clock signals, data of the main control module is driven to generate multiple paths of data signals, and clock lines and data lines are respectively connected to a front end board;
S2, transmitting a first specific coded data sequence to each front end board, taking a clock reference signal as a decoding clock of the group of specific coded data, and extracting an instruction in the first coded data sequence to configure working parameters of the front end board after the front end board decodes the group of specific coded signals;
s3, transmitting a second specific coded data sequence to each front end board, wherein the clock reference signal is used as a decoding clock of the group of specific coded data, and the front end board generates a synchronizing signal after decoding the group of specific coded signals, so that the clocks on each front end board are synchronized with the reference clock;
S4, transmitting a third specific coding data sequence to each front end board, wherein the clock reference signal is used as a decoding clock of the group of specific coding data, after the front end board decodes the group of specific coding signals, a trigger signal is generated, and the sampling clock of the front end board collects the rising edge of the trigger signal to start ADC collection or DAC output, so that synchronous collection is realized.
As an optimization of the present invention, the first specific coded data sequence, the second specific coded data sequence, and the third specific coded data sequence are coded using a method including, but not limited to, 8b/10b coding.
As an optimization scheme of the invention, the start of instruction transmission, the end of instruction transmission and the idle state are marked by a certain code.
As an optimization scheme of the invention, the main control module is connected with the front end board card through a USB TYPE C cable.
As an optimization scheme of the invention, the main control module is respectively connected with the front end board card through a clock line and a data line, so that instruction transmission and synchronous control are realized.
As an optimization scheme of the invention, the main control module takes the FPGA as a control chip, and the FPGA of the front end board decodes the FPGA.
The invention has the positive effects that: 1) The main control module is respectively connected with the front end board through a clock line and a data line, so that instruction transmission and synchronous control are realized. The command, the trigger and the synchronization are uniformly coded into specific data to be sent out through a data line, and the data transmission is synchronized with a reference clock. Compared with the traditional method requiring multiple signals such as bus connection, triggering, synchronization and the like, the method greatly reduces the required signal lines, does not need buses, reduces the interference between the signal lines, and has the advantages of simple wiring and wide application scene;
2) The invention provides a method for realizing instruction transmission and synchronization in an array signal processing system by matching a single-channel signal with a clock, which meets the requirements of instruction transmission and synchronous acquisition in the array signal processing system.
Drawings
For a clearer description of the technical solutions of embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered limiting in scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a diagram showing the connection relationship between channel acquisition instruction transmission and synchronization in the present invention;
FIG. 2 is a diagram showing the connection between command transmission and synchronization signals according to the present invention;
FIG. 3 is a diagram illustrating the transmission of code implementation instructions and synchronization in accordance with the present invention;
FIG. 4 is a timing diagram of a synchronization pulse generation process;
FIG. 5 is a diagram illustrating transmission and synchronization of PXI bus multi-board card commands;
FIG. 6 is a diagram of distributed connection system command transmission and synchronization.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in examples of the present invention, and it is apparent that the described examples are only some examples, but not all examples, of the present invention, and that other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present invention.
As shown in fig. 1, the invention discloses a method for controlling command transmission and synchronous acquisition in an array signal processing system, which mainly comprises 1 main control module and a plurality of front end boards (multi-channel ADC or DAC boards), wherein the main control module is respectively connected with the front end boards through a clock line and a data line to realize command transmission and synchronous control. As shown in fig. 2, the command, trigger and synchronization are all uniformly coded into specific data to be sent out through a data line, and the data transmission is synchronous with the reference clock. Compared with the traditional method requiring multiple signals such as bus connection, triggering, synchronization and the like, the method greatly reduces the required signal lines.
The method comprises the following specific steps:
S1, a reference clock of a main control module is driven to generate multiple paths of reference clock signals, data of the main control module is driven to generate multiple paths of data signals, and clock lines and data lines are respectively connected to a front end board;
S2, transmitting specific coding data sequences to each front end board, taking a clock reference signal as a decoding clock of the specific coding data, and extracting instructions in the specific coding signals after the FPGA of the front end board decodes the specific coding signals to configure working parameters of the front end board;
S3, transmitting different specific coded data sequences in the step S2 to each front end board, wherein the clock reference signal is used as a decoding clock of the specific coded data, and after the FPGA of the front end board decodes the specific coded signal, a synchronizing signal is generated, so that the clock on each front end board is synchronized with the reference clock, and the generated synchronizing signal is also synchronized with the reference clock due to the synchronization of the coded data and the reference clock, so that the synchronization of the clocks of each board and the reference clock is realized.
S4, transmitting specific coded data sequences different from the step S2 and the step S3 to each front end board, wherein the clock reference signal is used as a decoding clock of the specific coded data, after the FPGA of the front end board decodes the specific coded signals, a trigger signal is generated, and the sampling clock of the front end board collects the rising edge of the trigger signal to start ADC collection or DAC output, so that synchronous collection is realized. Namely, step S2 is an instruction, step S3 is a control clock synchronization, and step S4 is a control acquisition synchronization.
The embodiment realizes 512 channel array signal acquisition and processing, and is composed of 8 front end boards of a main control module respectively, each front end board completes 64 channel acquisition, and the main control module is connected with the front end boards through USB TYPE C cables, as shown in FIG. 1. The data transmission coding adopts 8b/10b coding, and through 8b/10b coding, the transmitted data string can be ensured to be correctly restored at the receiving end, besides, the receiving end can be helped to restore by utilizing a plurality of special codes (K codes), and the transmission error of the data bit can be found in early stage, so that the error is restrained from continuously occurring. In this embodiment, the transmission is started by the K28.1 id command, the transmission is ended by the K28.3 id data, the K28.6 is used as the synchronization, the K28.7 is used as the trigger, and the K28.5 is used as the idle state. When no signal is transmitted on the data line, K28.5 is sent to ensure dc balance. The coding transmission scheme is shown in fig. 3.
The specific implementation comprises the following steps:
step 1: the master control module takes an FPGA as a control chip, a 10MHz reference clock is driven to generate 9 paths of homologous clocks, 8 paths of clocks are taken as reference clocks of a front end board, and 1 path of clocks REFCLK0 are taken as reference clocks of the master control module FPGA. The FPGA takes REFCLK0 as a reference to generate DATA DATA output, and the main control module takes 10MHz as a reference to send the coded instruction through a DATA line. And the acquisition board completes the configuration of the working parameters after receiving the instruction.
Step 2: in step 2, the instruction DATA is 8b/10b encoded and then output through DATA via serial-parallel conversion. DATA outputs the instruction DATA with reference to the REFCLK0 falling edge. And the front end board receives the instruction and then carries out corresponding parameter configuration.
Step 3: k28.6 is serially output through DATA after parallel and serial conversion. After the front end board receives the synchronizing signal, the front end board generates a synchronizing pulse to control the clock generating chip to synchronize the output clock with the reference clock. As shown in fig. 4.
Step 4: k28.7 is serially output through DATA after parallel and serial conversion. After the front end board receives the synchronous signal, a trigger signal is generated to start the ADC to start synchronous acquisition. The timing relationship is the same as that of fig. 4.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical solution of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (6)
1. The method for controlling the command transmission and synchronous acquisition in the array signal processing system is characterized by comprising the following steps:
S1, a reference clock of a main control module is driven to generate multiple paths of reference clock signals, data of the main control module is driven to generate multiple paths of data signals, and clock lines and data lines are respectively connected to a front end board;
S2, transmitting a first specific coded data sequence to each front end board, taking a clock reference signal as a decoding clock of the group of specific coded data, and extracting an instruction in the first coded data sequence to configure working parameters of the front end board after the front end board decodes the group of specific coded signals;
s3, transmitting a second specific coded data sequence to each front end board, wherein the clock reference signal is used as a decoding clock of the group of specific coded data, and the front end board generates a synchronizing signal after decoding the group of specific coded signals, so that the clocks on each front end board are synchronized with the reference clock;
S4, transmitting a third specific coding data sequence to each front end board, wherein the clock reference signal is used as a decoding clock of the group of specific coding data, after the front end board decodes the group of specific coding signals, a trigger signal is generated, and the sampling clock of the front end board collects the rising edge of the trigger signal to start ADC collection or DAC output, so that synchronous collection is realized.
2. A method of controlling transmission and synchronous acquisition of instructions in an array signal processing system according to claim 1 wherein the first specific coded data sequence, the second specific coded data sequence, and the third specific coded data sequence are encoded using codes including, but not limited to, 8b/10 b.
3. The method of claim 2, wherein the start of command transmission, the end of command transmission, and the idle state are identified by a certain code.
4. The method for controlling command transmission and synchronous acquisition in an array signal processing system according to claim 1, wherein the main control module is connected to the front end board through a USB TYPE C cable.
5. The method for controlling command transmission and synchronous acquisition in an array signal processing system according to claim 4, wherein the main control module is connected to the front end board through a clock line and a data line, respectively, so as to realize command transmission and synchronous control.
6. The method for controlling command transmission and synchronous acquisition in an array signal processing system according to claim 5, wherein the main control module uses an FPGA as a control chip, and the FPGA of the front end board decodes the command.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410340162.3A CN118132497A (en) | 2024-03-25 | 2024-03-25 | Method for controlling command transmission and synchronous acquisition in array signal processing system |
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| CN202410340162.3A CN118132497A (en) | 2024-03-25 | 2024-03-25 | Method for controlling command transmission and synchronous acquisition in array signal processing system |
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