JP2513415B2 - Parallel / serial signal conversion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used as one of electronic circuit elements. The present invention is used as a parallel / serial signal conversion circuit for converting parallel data into serial data according to a certain conversion rule.

[0002]

2. Description of the Related Art An electronic device uses a parallel / serial signal conversion circuit for converting parallel data in the device into serial data when transmitting a data signal to a communication line or to another device. It is standard that the parallel data has an n-th power of 2 such as 8 bits, 16 bits, and 32 bits, and the serial data has a plurality of standard signal formats corresponding to the parallel data. The bit transmission rate (bit rate or frequency) of serial data differs for each standard signal format. The format of the signal of a specific pattern added to the serial data for frame identification or as a synchronization pattern is also different.

Regarding the conventional parallel-serial signal conversion circuit, Japanese Patent Application Laid-Open No. 61-116440 and Japanese Patent Application Laid-Open No. 6-116440.
It is disclosed in Japanese Patent Application Laid-Open No. 3-262938, Japanese Patent Application Laid-Open No. 1-233845.

[0004]

The conventional parallel-serial signal conversion circuit is fixed for each conversion rule. Therefore, parallel / serial signal conversion requires a different circuit for each conversion rule, and different designs must be made according to the counterpart circuit.

The present invention has been made against such a background, and an object of the present invention is to provide a device capable of coping with any of a plurality of parallel-serial signal conversion rules with a single circuit.

[0006]

SUMMARY OF THE INVENTION The present invention provides a parallel serial system having a clock signal generating circuit for generating a clock signal and a memory circuit for receiving parallel data and outputting serial data in synchronization with the clock signal. The signal conversion circuit includes a signal processing circuit inserted in the parallel data input circuit and a ROM for giving a control program to the signal processing circuit. The signal processing circuit passes parallel signals in accordance with the read output of the ROM. The ROM includes a means for adding a specific pattern signal and a means for controlling the clock signal generation circuit, and the ROM holds a control program for a plurality of parallel-serial signal conversion rules and sets the plurality of conversion rules by setting. Is configured to read a control program corresponding to one of the .

The specific pattern signal is a frame identification signal (F) and / or a synchronization signal (S), and the means for controlling the clock signal generating circuit preferably includes means for controlling the clock signal frequency.

[0008]

A ROM stores a plurality of control programs corresponding to a plurality of parallel / serial signal conversion rules. One of the control programs can be read by setting the control terminal of the ROM, and the read output is given to the signal processing circuit. The signal processing circuit generates a specific pattern for frame identification or synchronization in accordance with this control program, and the state of the generated clock signal (clock signal frequency) to the clock signal generation circuit.
Control.

By changing the setting of the ROM or by exchanging the ROM, a plurality of conversion rules can be dealt with by one circuit, so that it is not necessary to make a new design according to the other circuit. is there. The circuit of the present invention can be marketed as a general-purpose product.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

The embodiment of the present invention comprises a clock signal generating circuit 4 for generating a clock signal, and a memory circuit 3 for inputting parallel data and outputting serial data in synchronization with the clock signal. Characteristically, the signal processing circuit 1 inserted in the parallel data input circuit, and R for giving a control program to the signal processing circuit 1
OM2, the signal processing circuit 1 includes means for adding a specific pattern signal to the parallel data passing according to the read output of the ROM 2, and means for controlling the clock signal generating circuit 4, and the ROM 2 includes a plurality of parallel signals. It is configured to hold a control program for the serial signal conversion rule and read the control program corresponding to one of the plurality of conversion rules by setting.

The specific pattern signal is a frame identification signal (F) and / or a synchronization signal (S), and the means for controlling the clock signal generating circuit 4 includes means for controlling the clock signal frequency.

FIGS. 2A and 2B are views showing examples of serial data types according to the embodiment of the present invention. In the case of the serial data type (A) shown in FIG. 9A, F is a frame synchronization signal and A is data. In the case of the serial data type (B) shown in FIG. 2B, F is a frame identification signal, S ₁ and S ₂ are synchronization signals, and D is data.

Even if the input parallel data is data in 32-bit units, the output serial data has a different type due to the difference in conversion rule as described above.

The present invention is characterized in that one circuit can handle a plurality of conversion rules even if the type of output serial data is different, and the following operation is performed.

The signal processing circuit 1 inputs a clock signal and parallel data from the outside, and inserts a synchronization pattern set by the data of the ROM 2 into an arbitrary position of the input parallel data. Further, the signal processing circuit 1 performs serial-parallel conversion by the clock signal from the outside and the number of bits of the synchronization pattern to be added, and generates a conversion clock for the memory circuit 3 that outputs a signal as serial data. The clock frequency of the signal generating circuit 4 is set. The memory circuit 3 converts the parallel data to which the synchronization pattern is added into serial data by the clock signal of the clock signal generation circuit 4 and outputs the serial data.

As described above, according to the present invention, it is possible to insert an arbitrary pattern at an arbitrary position by reading the synchronous pattern and the synchronous pattern insertion position stored in the ROM. It is possible to add several kinds of data stored in memory, set the stored address information, and decode it by the signal processing circuit to add even if the position and pattern content of the synchronization pattern are different.

[0018]

As described above, according to the present invention, the circuit configuration is not changed even if the position and the pattern content of the synchronization pattern added when converting the parallel data into the serial data and transmitting the data are different. There is an effect that can be added.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

2A and 2B are diagrams showing an example of serial data type according to an embodiment of the present invention.

[Explanation of symbols]

 1 signal processing circuit 2 ROM 3 memory circuit 4 clock signal generation circuit

Claims (3)

(57) [Claims] 1. A parallel-serial signal conversion circuit comprising: a clock signal generation circuit for generating a clock signal; and a memory circuit for receiving parallel data and outputting serial data in synchronization with the clock signal. Of the signal processing circuit inserted in the input circuit of RO and a control program for giving a control program to this signal processing circuit
M, the signal processing circuit includes means for adding a specific pattern signal to parallel data passing according to the read output of the ROM, and means for controlling the clock signal generation circuit, and the ROM includes a plurality of ROMs. A parallel-serial signal conversion circuit, characterized in that the control program for the parallel-serial signal conversion rule is held and the control program corresponding to one of the plurality of conversion rules is read by setting. . 2. The specific pattern signal is a frame identification signal (F) and / or a synchronization signal (S).
The parallel / serial signal conversion circuit described. 3. The parallel-serial signal conversion circuit according to claim 1, wherein the means for controlling the clock signal generating circuit includes means for controlling a clock signal frequency.