JP2674799B2 - High efficiency digital add / drop device - Google Patents

Description

The present invention relates to a device for branching, inserting and adding information of an arbitrary time slot in a PCM, and particularly to a digital branch for effectively using a time slot in a PCM signal. Regarding the insertion device.

[Conventional technology]

This type of conventional digital add / drop multiplexer uses a 64 kb / s PCM audio signal as an input signal and 8 × Nkb / s, 64 × N
A digital data signal of kb / s (N is an integer) is targeted, and an outline of the operation will be described with reference to FIG.

The digital add / drop multiplexer has an A port forming a main path, a B port, and a C port forming a branch path,
The input signal input from the A port is the interface circuit 10
The code is converted into an internal code by 0 and the clock is extracted and transmitted to the B port output generation circuit 130 and the C port output generation circuit 150. Further, the input signal input from the B port is code-converted into an internal code by the interface circuit 110, a clock is extracted, and is transmitted to the A port output generation circuit 140 and the C port output generation circuit 150. Similarly, an input signal input from the C port is code-converted into an internal code by the interface circuit 120,
It is transmitted to the port output generation circuit 130 and the A port output generation circuit 140.

In the B port output generation circuit 130, one of the A port input signal code-converted to the internal code, the C port input, and the signal obtained by adding the both is selected by the external control signal and coded to the transmission line code. It is converted and output from the B port to the outside.

Similarly, in the A port output generation circuit 140, one of the signals obtained by adding both the B port input signal and the C port input signal code-converted to the internal code is selected by the external control signal and the transmission line code is selected. The code is converted to and output from the A port to the outside.

In the C port output generation circuit 150, one of the A port input signal and the B port input signal code-converted to the internal code and the signal obtained by adding both is selected by the external control signal and coded to the transmission line code. It is converted and output from the C port to the outside.

By the way, the signal frame format of the PCM primary group signal (2,048 kb / s) is divided into 32 time slots as shown in Fig. 9, and each time slot consists of 8 bits and transmits a 64 kb / s signal. can do.

But out of 32 time slots, time slot 0
Since 16 and 16 are used for transmitting a frame pattern and signaling bits, respectively, a signal of 64 kb / s can normally be transmitted up to 30 channels. For details, refer to CCITT: International Telegraph and Advisory Committee.
Telephone Cunsultative Committee) G.704
It is described in.

[Problems to be solved by the invention]

When the transmission signal is a voice signal, the above-mentioned conventional digital add / drop device is intended for a PCM signal of 64 kb / s. Therefore, when the input / output signal is the PCM primary group signal (2,048 kb / s), it can be output from one port. Since the number of audio signal channels is 30 (31 when the signaling transmission time slot is used for audio transmission), branching to each port,
The maximum capacity of channels that can be inserted and added was limited to 30 channels.

An object of the present invention is to increase the number of channels that can be dropped and added by increasing the transmission capacity of the add / drop multiplexer.

[Means for solving the problem]

The high-efficiency digital add / drop multiplexer of the present invention is a digital add / drop multiplexer that drops, inserts, and adds information of arbitrary time slots in a PCM signal, and means for digitally adding main path information and branch path information. A means for taking a logical product of the two signals in bit units when the information on the main path and the information on the branch path are digital data signals; and transmitting the information on the main path and the information on the branch path, respectively. Means for converting the ADPCM (adaptive differential PCM) signal at a speed of 32 kb / s to an array and converting them into a single time slot; Information and information on the branch path
A means for decoding into a 64 kb / s PCM signal, the output of the addition result, the output after the logical product operation, the output after array conversion, the output after the decoding, the input main path information and the input branch path information A means for selecting one of them to generate an output audio signal; a means for taking a logical product of the signaling information of the main path and the signaling information of the branch path in bit units to generate a signaling signal; Means for inserting code conversion information indicating that the information of the path and the information of the branch path is code-converted into the ADPCM signal of the transmission rate of 32 kb / s into the time slot for signaling information transmission, the output voice signal and the output Output from signaling signal
It has means for generating a PCM signal and means for controlling the operations of the various functions.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is an input terminal of a main path (hereinafter referred to as an A port input terminal) and 2 is an output terminal of a main path (hereinafter referred to as an A port output terminal). ) 3 is the input terminal of the other main path (hereinafter referred to as the B port input terminal), 4 is the output terminal of the other main path (hereinafter referred to as the B port output terminal), 5
Is a branch path input terminal (hereinafter referred to as C port input terminal), 6 is a branch path output terminal (hereinafter referred to as C port output terminal), 7 and 12 are clock extraction circuits 8, 13 and 17 are frame aligners. Circuit (hereinafter referred to as FA circuit), 9,1
4,18 is an output voice signal generation circuit, 10,15,19 is an output signaling signal generation circuit, 11,16,20 is an output PCM signal generation circuit, 2
1 is a control circuit, and 22,23,24,25,26,27 are control bus lines (a plurality of control lines).

In the figure, the description will focus on the process of generating the output PCM signal of the B port.

The clock extraction circuit 7 extracts a clock from the input signal sequence input from the A port input terminal 1 to generate a reference clock CK _ab of the output signal of the B port, and outputs it to the FA circuit 8. In the FA circuit 8, the input signal sequence input from the C port input terminal 5 is output to the output audio signal generation circuit 9 and the output signaling signal generation circuit 10 in accordance with the phase of the above-mentioned extraction clock CK _ab .

The output audio signal generation circuit 9 inputs the input signal sequence input from the A port input terminal 1 and the output of the FA circuit 8 described above, and outputs each time according to the contents of the control bus line 22 from the control circuit 21 described later. Generate the desired output signal for each slot,
Output to the output PCM signal generation circuit 11. The desired signal mentioned here is a signal generated by the following processing.

A signal obtained by converting the input PCM signals input from the A port and C port into a 32 kb / s ADPCM (adaptive differential PCM) code consisting of 4 bits and then arranging both in one time slot.

32kb / s ADPC input from A port and C port
A signal obtained by decoding an M signal into a 64 kb / s PCM signal and inserting one desired signal of two input signals into one time slot.

A signal obtained by code-converting the input PCM signals input from the A and C ports into a linear signal, digitally adding both, and then code-converting the result into a PCM signal and inserting it into one time slot. . (This signal superimposes the voice signal of the subscribers of the A and B ports when the telephone subscribers connected to the A, B and C ports are making a three-way call, and It corresponds to the case of transmission to the A.) The input digital data signals input from the A port and C port are logically ANDed in bit units and the result is 1
A signal obtained by inserting it into a time slot.
(Corresponding to the case where one of the corresponding channels of the A or B port is an empty channel or is in the pause period and all the digital data signals are "1") Input PCM input from the A port and C port or A
A signal obtained by selecting one of the DPCM signals and inserting it into one time slot.

The processes of and are usually performed when either one of the two input signals input from the A port and the C port is in the non-communication state.

Further, in the output signaling signal generation circuit 10, the input signal sequence input from the A port input terminal 1 and the output of the FA circuit 8 described above are input, and according to the contents of the control bus line 22 from the control circuit 21 described later. Extract the signaling bits of each channel (indicating whether the channel is busy or idle ring, etc.), AND the signaling bits of both input signals bit by bit and insert into the desired time slot. , Output to the output PCM signal generation circuit 11. At the same time, the code conversion information described later is extracted and output to the control circuit 21.

The output PCM signal generation circuit 11 inputs the output of the above-mentioned output audio signal generation circuit 9 and the output of the output signaling signal generation circuit 10 according to the contents of the control bus line 23 from the control circuit 21 described later, The information of each channel is arranged in the position of the time slot specified by the control circuit 21 of, and at the same time, in the time slot 16 (TS16) used for transmitting the signaling bit, the current information is the PCM signal. An output PCM signal sequence is generated by inserting code conversion information indicating whether it is an ADPCM signal or not, and is output from the B port output terminal 3.

The control circuit 21 inputs the code conversion information extracted by the output signaling signal generation circuit 10, and selects the operation timing and the function for the output voice signal generation circuit 9, the output signaling signal generation circuit 10 and the output PCM signal generation circuit 11. Output a control signal for.

Up to now, the description has focused on the process of generating the output PCM signal of the B port, but since the same applies to the A port and the C port, duplicate description will be omitted. However, the A port output PCM signal is synchronized with the clock extracted from the B port input signal sequence, and the C port output PCM signal is synchronized with the clock extracted from the A port input signal sequence.

Output audio signal generation circuit Also, the output audio signal generation circuit 9 used in the present invention,
The circuits shown in FIG. 2 can be applied to 14 and 18. In the figure, 30 and 31 are input terminals, 32 is output terminals, and 33 and 34 are ADPCM.
Encoding circuit, 35 is an array conversion circuit, 36 and 37 are PCM decoding circuits, 38 and 39 are non-linear / linear conversion circuits, 40 is a digital addition circuit, 41 is a logical product circuit, 42 is a selection circuit, and 43 is a control signal. The input terminal is shown.

If the input signal input from the input terminal 30 is a signal that can be code-converted into a voice signal converted to a PCM signal or a 32 kb / s ADPCM signal such as a voice band modem signal of 4800 b / s or less, an ADPCM code 32 kb / s ADPCM by conversion circuit 33
The signal is code-converted and sent to the array conversion circuit 35. Similarly, the input signal input from the input terminal 31 is also ADPCM.
The code is converted into a 32 kb / s ADPCM signal by the encoding circuit and sent to the array conversion circuit 35. AD in the array conversion circuit 35
The outputs of the PCM encoding circuits 33 and 34 are input, the two ADPCM signals are arranged in one time slot, and the selected AD signal is output to the selection circuit 42. This is possible because the 32 kb / s ADPCM signal is a 4-bit signal, so that two ADPCM signals can be arranged in one time slot (8-bit configuration).
(In the PCM method, the sample value of the voice waveform is quantized as it is, whereas in the ADPCM method, the difference between the sample values is quantized. Since there is a correlation between the sample values of the voice signal, Predict current input signal and predict error (difference)
The number of quantization bits is smaller when the signal is quantized and transmitted. In the PCM method, the quantization is performed with 8 bits, whereas in the ADPCM method, the quantization is performed with 4 bits. )
(Responsible for the above process).

In the PCM decoding circuit 36, the input signal input from the input terminal 30 has already been encoded into a 32 kb / s ADPCM signal, and the signal of another channel arranged in the same time slot has already been output to the C port. When the signal is dropped or when there is no call, and when the terminal equipment connected to this drop-and-insert device requires a PCM signal, the above input signal is converted to a 64 kb / s PCM signal. Decode and output to the selection circuit 42. (This corresponds to the above-mentioned processing.) Similarly, the PCM decoding circuit 37 also decodes the ADPCM signal into a PCM signal and outputs it to the selection circuit 42.

The non-linear / linear conversion circuits 38 and 39 are respectively input terminals.
The input PCM signals input from 30 and 31 are code-converted into a linear signal and output to the digital addition circuit 40. The digital adder circuit 40 inputs the outputs of the non-linear / linear conversion circuits 38 and 39, digitally adds both outputs, and again converts the result into an 8-bit PCM signal and outputs it to the selection circuit 42. (This corresponds to the above-mentioned processing.) Note that this processing is performed only when the input signal is a PCM signal.

The AND circuit 41 logically ANDs the data signals input from the input terminals 30 and 31 bit by bit and outputs the logical product to the selection circuit 42. Note that this processing (corresponding to the processing described above) is executed only when the input signal is a data signal.

In the selection circuit 42, an input signal input from the input terminal 30, an input signal input from the input terminal 31, an array conversion is performed in a desired time slot according to the content of the control bus line input from the control signal input terminal 43. Any one of the output of the circuit 35, the output of the PCM decoding circuit 36, the output of the PCM decoding circuit 37, the output of the digital addition circuit 40 and the output of the AND circuit 41 is selected and output from the output terminal 32. .

FIG. 3 shows an example (indicated by 50 in the figure) of one time slot of the output audio signal in the present invention. Bits from the 1st bit to the 4th bit are input from the A port, and the audio signal output to the B port is an AD of 32 kb / s.
It shows the signal code-converted into a PCM signal, and the bits from the 5th bit to the 8th bit are converted from the audio signal input from the C port and output to the B port into a 32kb / s ADPCM signal. Shows.

Output Signaling Signal Generation Circuit Output Signaling Signal Generation Circuit Used in the Present Invention
The circuit shown in FIG. 4 can be applied to 10, 15, and 19. In the figure, 60, 61 and 69 are input terminals, 62 and 63 are signaling bit / code conversion information extraction circuits, 64 is a logical product circuit, 65 is a frame recorrection circuit, 66 is a signaling bit output terminal, 67 and 6
Reference numeral 8 is a code conversion information output terminal, and 70 is a code conversion information generation circuit.

The time slot 16 of the PCM primary group signal input from the input terminals 60 and 61 is normally used for transmitting signaling bits as described in Recommendation G.704 from CCITT mentioned above. FIG. 5 shows the channel allocation of the time slot 16 in each frame. As can be seen from the figure, a multi-frame configuration from frame 0 to frame 15 is adopted and signaling bits for 30 channels are transmitted in the frames from frame 1 to frame 15.

In this invention, as shown in FIG. 6, the signaling bit c,
Instead of d, it transmits code conversion information indicating whether the signal has been 32 kb / s ADPCM code converted. When the signaling bits c and d are not used for transmission of signaling information, c = 0 and d = 1 are fixed, so when 32 kb / s ADPCM code conversion is performed, c = 1 and d = 1, and When not converted, c = 0 and d = 0.

FIG. 4 shows a signaling bit / code conversion information extraction circuit.
62 and 63 are signaling bits a and d transmitted in the time slot 16 of the PCM primary group signal input from the input terminals 60 and 61 according to the contents of the control bus line input from the input terminal 69.
Is extracted and output to the AND circuit 64. At the same time, the code conversion information transmission bits c and d are extracted and output to the outside from the output terminals 67 and 68, respectively.

The logical product circuit 64 outputs the signaling bits a and d output from the signaling bit / code conversion information extraction circuits 62 and 63.
Bit-wise logical product of
Output to 65. The bit-wise logical product in this case is obtained as follows when the signaling bits of the signal input from the input terminal 60 and the input terminal 61 are {a ₁ , b ₁ }, {a ₂ , b ₂ }. is there.

a ₀ = a ₁ ∩a ₂ , b ₀ = b ₁ ∩b ₂ This operation is performed when one of the input signals is in the silent state. The obtained signaling bits a ₀ and b ₀ are output to the frame reproduction circuit 65. The code conversion information generation circuit 70 newly generates code conversion information according to the contents of the control bus line input from the input terminal 69 and outputs it to the frame reproduction circuit 65.

The frame reproduction circuit 65 has a logical product circuit 64 at the positions of the signaling bits a ₁ and b ₁ of the time slot 16 of the PCM primary group signal input from the input terminal 60 according to the contents of the control bus line input from the input terminal 69. Outputs a ₀ and b ₀ of the code conversion information generation circuit 70 are inserted at the positions of the signaling bits c and d.
From the signaling bit output terminal 66.

The signaling bits a and b in FIG. 6 are the signaling bits a {VF _{A, B} }, b {VF _{A, B} } of the audio signal input from the A port and output to the B port, and the B input from the C port. Signaling bit a of the audio signal output to the port
The result of taking the logical product with {VF _{C, B} } and b {VF _{C, B} } (indicated by ∩ in the figure) is shown. The code conversion information bits c and d are from the B port. The output PCM primary group signal is 32 kb /
It shows whether or not ps ADPCM code conversion is performed. When both are 0, 32 kb / ps ADPCM code conversion is performed, and when both are 1, both 32 kb / ps ADPCM code conversion is performed.
Indicates that the code has not been converted.

Output PCM Signal Generation Circuit The circuit shown in FIG. 7 can be applied to the output PCM signal generation circuits 11, 16 and 27 of the present invention. In the figure, 80, 81 and 82 are input terminals, 83 is a first selection circuit, 84 is a frame pattern generation circuit, 85 is a second selection circuit, and 86 is an output terminal.

As shown in FIG. 8A, the input signal S _A input from the input terminal 80 has output audio signals packed in the time slots (TS) 1 to 15 and 17 to 31. The input signal S _B input from the terminal 81 has the signaling bits and the code conversion information bits packed in the time slot 16 in the multi-frame structure as described above, as shown in FIG. 8B.

The first selection circuit 83 appropriately selects the audio signal input from the input terminal 80 and the signaling and code conversion information input from the input terminal 81 according to the content of the control bus line input from the input terminal 82, It outputs to the second selection circuit 85.

The frame pattern generation circuit 84 generates a frame pattern and an alarm signal to be inserted into the time slot O of the PCM primary group signal according to the content of the control bus line input from the input terminal 82, and selects the signal S _C as the second selection. It is output to the circuit 85 (Fig. 8C).

The second selection circuit 85 appropriately selects the output signal from the first selection circuit 83 and the output signal S _C from the frame pattern generation circuit 84 according to the content of the control bus line input from the input terminal 82. , Output PCM primary group signal is generated and output from the output terminal 86.

〔The invention's effect〕

As is clear from the above description, in the present invention,
The signals handled by the insertion device are not only PCM signals and digital data signals obtained by converting conventional audio signals, but also ADP
It is also expanded to CM signals. (As is well known, 0th order PC
The M signal is sampled at 8 kHz and quantized at 8 bits, so its bit rate is 64 kb / s.
Since the ADPCM signal is sampled at 8 kHz and quantized at 4 bits, its bit rate is 32 kb / s. According to the present invention, the transmission capacity can be doubled at maximum by arranging the conversion of two channels of the ADPCM signal in one time slot (eight bits) of the PCM signal, if necessary.
That is, the number of channels that can be dropped or added is doubled, that is, 60 channels, that is, 60 channels.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a high-efficiency digital add / drop multiplexer of the present invention, and FIG. 2 is a block diagram showing an example of the output audio signal generating circuits 9, 14, 18 of FIG.
FIG. 3 is a diagram showing an example of a time slot of an output voice signal of the high efficiency digital add / drop multiplexer of the present invention.
FIG. 5 is a block diagram showing an example of the output signaling signal generation circuits 10, 15, 19 of FIG. 1, and FIG. 5 is a diagram showing channel allocation of time slots 16 (signaling bits) in each frame of the PCM primary group signal. FIG. 6 is a diagram showing the configuration of signaling time slots of the high efficiency digital add / drop multiplexer of the present invention, and FIG. 7 shows an example of the output PCM signal generation circuit 11, 16, 20 of FIG. FIG. 8 is a block diagram, FIG. 8 is a timing chart of signals of main parts of FIG. 7, FIG. 9 is a block diagram showing an outline of a conventional digital add / drop multiplexer, and FIG. 10 is a frame of a PCM primary group signal. It is a figure which shows a format.

Continuation of the front page (56) Reference JP 63-237625 (JP, A) JP 63-234742 (JP, A) JP 59-95745 (JP, A) JP 1-125031 (JP , A)

Claims (1)

(57) [Claims] 1. A digital add / drop multiplexer for branching, inserting and adding information of arbitrary time slots in a PCM signal, and means for digitally adding main path information and branch path information, When the information and the information of the branch path are digital data signals, a means for taking a logical product of both signals in bit units, and the ADPCM at a transmission rate of 32 kb / s for the information of the main path and the information of the branch path, respectively. (Adaptive differential PCM) Means for converting the two into one time slot after code conversion, and the AD having the transmission rate of 32 kb / s
Means for decoding the information of the main path and the information of the branch path code-converted and transmitted to a PCM signal into a PCM signal of 64 kb / s, the output of the addition result, and the output after the AND operation 1 out of the output after the conversion, the output after the decoding, the input main path information, and the input branch path information.
A means for selecting an output voice signal and a means for generating an output signaling signal by logically ANDing bit-wise the signaling information of the main path and the signaling information of the branch path, and information of the main path And means for inserting code conversion information indicating that the information of the branching path is code-converted into an ADPCM signal of the transmission rate of 32 kb / s into a time slot for signaling information transmission, the output voice signal and the output signaling signal. Output from PC
A highly efficient digital add / drop multiplexer comprising means for generating an M signal and means for controlling the operations of the various functions.