JPS63262944A - Conversion circuit for bearer velocity of asynchronous data signal - Google Patents

Abstract

PURPOSE:To miniaturize a device and to prevent quantization distortion from being accumulated, by performing compressive conversion and extensive conversion directly between bit strings with first-order and second-order multiplexed bearer velocity. CONSTITUTION:Bit extraction is performed from the bit string with first-order bearer velocity at a constant interval, and at this time, the compressive conversion from the first-order bearer velocity to the second-order bearer velocity is performed by inserting a time quantizing bit which represents the occurrence of the change point of the first-order bearer velocity at the first half or the latter half of a bit extraction interval to a position next to an extracted bit behind the change point, and a bit pattern to expand the number of bits is generated from the combination of consecutive three bits in the bit string with the second-order bearer velocity, and the extensive conversion of the pattern from the second-order bearer velocity to the first-order bearer velocity is performed directly between the bit strings with first-order and second- order multiplexed bearer velocity. In such a way, it is possible to prevent the number of circuits from being increased and to control the quantization distortion when the switching of the bearer velocity of a multiplexed asynchronous data signal is performed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for synchronous transmission of asynchronous data signals.
The present invention relates to a circuit that performs multiple processing of bearer speed conversion due to differences in encoding methods.

[Conventional technology]

In systems such as local area networks (hereinafter referred to as LANs) and digital private branch exchanges (hereinafter referred to as EPBXs), communication lines are installed in relatively narrow areas, so it is necessary to use lines with high-speed bit transmission capacity. Available at low cost. The terminal devices connected to this LAN and EPBX are of various types, for example, 300 bits/second, 1200 bits/second, etc.
bits/second, operating at terminal speeds such as 9600 bits/second. When these terminals are connected to a LAN or EPBX, signals are synchronized by encoding and transmitted.

At this time, the cost of the transmission line is low as mentioned above,
In addition, the encoding/decoding circuit can be simplified, and exchange control can be simplified by treating all asynchronous data signals as data at the same speed. For example, 64kHz
Multi-point sampling is performed using a sampling clock of 1, and data is often sent on a transmission path at a uniform bearer speed of 64,000 bits/second.

On the other hand, it is also possible to communicate not only between terminal devices connected to each LAN or EPBX, but also between terminal devices connected to LANs or EPBXs located in multiple remote locations. Another possibility is to interconnect LANs or EPBXs by using time-division multiplexing of digital lines. When interconnecting asynchronous data signals sent at a single bearer speed within a LAN or EPBX using the digital line, etc., in order to effectively utilize the line capacity of the digital line, it is necessary to
Rather than transmitting all of the above asynchronous data signals at a bearer rate of 64,000 bits/second, which is the same as in the BX, it is necessary to compress and convert them to a bearer rate commensurate with the terminal speed.

For purposes of explanation below, the single bearer rate of asynchronous data signals independent of the terminal speed within each LAN or EPBX will be referred to as the primary bearer rate, and the bearer having that rate will be referred to as the primary bearer. On the other hand, a bearer speed commensurate with the terminal speed as described above is called a secondary bearer speed, and a bearer having that speed is called a secondary bearer.

Now, as a coding method for configuring a secondary bearer, there is a method of performing multi-point sampling by changing the sampling rate for each terminal speed, but this is inefficient and inappropriate when the terminal speed is high. In addition, in order to improve coding efficiency, sliding index methods, fixed index methods, Puer mode 2-bit coding methods, etc. that introduce time quantization processing at data change points have been proposed.
Research practical application report Vol. 1.21, No. 2 (197
2. Nippon Telegraph and Telephone Public Corporation) P45-P84 Research on [)ual Mode code conversion system for rp CM data transmission"
etc〕. Here, the secondary bearer rate will be configured using a dual mode 2-bit encoding method with the highest encoding efficiency. However, in order to eliminate the need for synchronization processing for reference adjustment of the mode pulse train in this method, the patterns 0'' mode pulse train correspond to oooo . . . and the "1" mode pulse train corresponds to patterns 1111 . . .

FIG. 11 is a schematic configuration diagram showing a conventional asynchronous data signal bearer speed conversion circuit. In the figure, 1 is a LAN or EPBX constituent node, and 2 is a primary bearer transmission multiplexed in octets. transmission line, 3 is 1
A bearer speed conversion circuit 4 mutually converts the next bearer speed and the secondary bearer speed, and 4 separates the multiplexed primary bearer from the transmission line 2 and multiplexes and demultiplexes the secondary bearer from the bearer speed conversion circuit 3. 5 is the bearer speed conversion circuit 3
A demultiplexing circuit multiplexes the primary bearer from the digital line 8 side and separates the secondary bearer from the digital line 8 side; 6 is a transmission line for transmitting the secondary bearer multiplexed in units of octets; 7
9 is an interface circuit for the digital line 8, and 9 is a transmission line for data without bearer speed conversion.

FIG. 12 is a block diagram showing the configuration of the bearer speed conversion circuit 3. In the figure, 10 is an input terminal of the primary bearer in units of octets, 11 is a desampling circuit composed of flip-flops, etc., and 12 is a block diagram showing the configuration of the bearer speed conversion circuit 3. 13 is a sampling circuit for dual-mode encoding; 13 is a time quantization bit insertion circuit for indicating whether the change point of the asynchronous data signal occurs in the first half or the second half of the sampling interval; 14 is a time quantization bit insertion circuit; bit insertion circuit 13
15 is an output terminal of a secondary bearer in units of octets, 16 is an input terminal of secondary bearers in units of octets, and 17 is a A parallel-to-serial conversion circuit, 18 a decoding circuit for decoding dual-mode encoded data at secondary bearer speed, 19 a sampling circuit for converting to primary bearer speed, and 20 converting serial data from the sambrisoge circuit 19 into parallel data. 21 is an output terminal of the primary bearer in units of octets, and 22 is a timing generation circuit that generates timing pulses to be supplied to each circuit.

Next, the operation will be explained. Note that the explanation will be made separately for the case of compression conversion from the primary bearer speed to the secondary bearer speed, and the case of decompression conversion from the secondary bearer speed to the primary bearer speed.

(a) A plurality of primary bearers multiplexed in units of octets from the component node 1 of the compression conversion LAN or EPBX are transmitted to the demultiplexing circuit 4 via the transmission line 2. The demultiplexing circuit 4 separates each of the multiplexed primary bearers,
It is distributed to a plurality of bearer speed conversion circuits 3. The distributed primary bearer enters the desampling circuit 11 via the input terminal 10, where it is desampled with a clock having the same sampling rate, for example, 64 kHz, and is converted into serial data at the original terminal speed, for example, 1200 bits/second. be returned.

It is then sampled again in the sampling circuit 12 for dual-mode encoding, which determines the secondary bearer rate. The time quantization bit insertion circuit 13 performs a process of inserting time quantization bits to convey the position of occurrence of a change point in the sampling interval. The signals are then assembled into octets by the serial/parallel conversion circuit 14 and transmitted to the demultiplexing circuit 5 via the output terminal 15. The demultiplexing circuit 5 multiplexes the secondary bearers from the plurality of bearer speed conversion circuits 3 and transfers them to the digital line interface circuit 7.
via the transmission line 6.

(b) A plurality of secondary bearers multiplexed in octet units from the expansion/conversion digital line interface circuit 7 are transmitted to the demultiplexing circuit 5 via the transmission line 6.

The demultiplexing circuit 5 separates each of the multiplexed secondary bearers and distributes them to a plurality of bearer speed conversion circuits 3. The distributed secondary bearers enter the parallel-to-serial conversion circuit 17 via the input terminal 16, and are converted from parallel data in units of octets to serial data. The decoding circuit 18 then converts the dual mode encoded format to the original terminal speed, e.g.
The data is converted back to serial data at 200 bits/second. The signals are then assembled into octets by the serial/parallel conversion circuit 20 and transmitted to the demultiplexing circuit 4 via the output terminal 21. In the demultiplexing circuit 4, one of the plurality of bearer speed conversion circuits 3
The next bearer is multiplexed and transmitted to the constituent node 1 via the transmission line 2.

[Problem that the invention seeks to solve]

Since the conventional bearer speed conversion circuit for asynchronous data signals is configured as described above, one bearer conversion circuit 3
can only convert one asynchronous data signal,
When handling multiple time-division multiplexed asynchronous data signals, data demultiplexing circuits 4 and 5 are required, and as the number of asynchronous data signals to be handled increases, the number of circuits also increases, leading to an increase in cost. (In addition, there were problems such as quantization distortion being accumulated because dual mode encoding processing was performed after the terminal speed was returned to the original speed by desampling.

This invention was made to solve the above-mentioned problems, and when carrying out bearer speed conversion of multiplexed asynchronous data signals, it does not require an increase in the number of circuits, and it reduces quantization distortion compared to conventional methods. An object of the present invention is to obtain a bearer speed conversion circuit for asynchronous data signals that can control the speed of asynchronous data signals.

[Means for solving problems]

The bearer speed conversion circuit for asynchronous data signals according to the present invention includes a bit extraction means for extracting bits at the same bit interval as a conversion ratio N obtained by dividing the primary bearer speed by the secondary bearer speed, and a bit string of the primary bearer speed. changing point determining means for determining whether a changing point in the extraction interval occurs in the first half or the latter half of the extraction interval; a compression conversion unit having a time quantization bit insertion means for inserting a time quantization bit indicating a determination result by the means; It is equipped with an expansion converter having a 3-pit pattern output means for generating a bit pattern, and an expansion pattern output means for outputting a bit pattern corresponding to the output signal of the 3-bit pattern output means and the conversion ratio N. be.

[For production]

The bearer speed conversion circuit for asynchronous data signals in this invention extracts bits at regular intervals from the bit string of the primary bearer speed without once returning the primary bearer speed or the secondary bearer speed to the terminal speed. A time quantization bit indicating whether the change point of the primary bearer occurred in the first half or the second half of the bit extraction interval is inserted into the next position of the extracted bit after the change point, and the secondary bearer is determined from the primary bearer speed. A bit pattern for expanding the number of bits is created from a combination of consecutive 3 bits in the bit string of the secondary bearer speed, and it is expanded and converted from the secondary bearer speed to the primary bearer speed. By performing this directly between the bit strings of the multiplexed primary bearer rate and secondary bearer rate, the compression conversion and expansion conversion of the time-division multiplexed asynchronous data signal can be performed while remaining multiplexed. , which prevents the accumulation of quantization distortion.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a component node of a LAN or EPBX, 2 and 6 are transmission lines, 7 is a digital line interface circuit, and 8 is a digital circuit, which are the same as or equivalent to the conventional ones with the same symbols in FIG. 11. Since this is only a partial explanation, a detailed explanation will be omitted. Also, 23 is, for example, 480
24 is an asynchronous terminal with a terminal speed of 1200 bits/s, for example, 25.26 is a transmission line connecting each asynchronous terminal 23, 24 and the constituent node 1, 27 is a bearer speed conversion circuit, and this bearer speed conversion circuit 27 mainly includes a compression conversion unit 28 that converts from a primary bearer speed to a secondary bearer speed;
It is composed of an extension converter 29 that converts the secondary bearer speed to the primary bearer speed.

FIG. 2 is a block diagram showing the configuration of the compression conversion section 28. In the figure, 101 is an input terminal of a multiplexed primary bearer, and 102 is a primary bearer input from the input terminal 101 in units of octets from a control circuit 103 to a control line 1.
105 counts the control pulses sent from the primary bearer input circuit 102 via the control line 104. A bit extraction circuit for counting the number of bits passed from the primary bearer output circuit 102 via the line 107 and instructing the bits to be extracted from among them. , 108 are an extraction bit holding register 109 for holding the state of the previously extracted binoto and a primary bearer output circuit 10 for the previous extraction bit.
It has a bit holding register 110 for holding the state of the bit passed from the primary bearer output circuit 102 and a same state counter 111 for counting how many times the same state continues for the bit passed from the primary bearer output circuit 102. Changing point determination circuit for detecting the changing point of the next bearer and calculating the position, 1
Reference numeral 12 denotes a change point detection register 1 which is set to "1" when there is a change point according to an instruction from the change point determination circuit 108.
13 and a change point position register which is similarly set to 0'' when the change point position occurs in the first half of the bit extraction interval and to 1'' when the change point position occurs in the latter half according to instructions from the change point determination circuit 108. 114 and a change point position register 11
A time quantization bit insertion circuit 115 inserts a time quantization bit in place of the bit extracted by the value of 4, and 115 is a modulus 8 for instructing in which position in the octet structure of the secondary bearer the bit is to be accommodated. A secondary bearer output circuit has a bit storage counter 116 which is a cyclic counting counter and assembles 1-bit data passed from the time quantization bit insertion circuit 112 into 8-bit data. 117 is an output terminal from the secondary bearer output circuit 115. be. Also, 1
Reference numeral 18 denotes a storage circuit for holding information when performing multiple processing, which includes the extraction counter 106, extraction bit holding register 109, bit holding register 110, same state counter 111, change point detection register 113, change point position register 114. , 119 and 120 are control lines. Further, the six values mentioned above will be collectively referred to as reference information hereinafter.

FIG. 3 is a block diagram showing the configuration of the expansion/conversion section 29. As shown in FIG. In the figure, 201 is an input terminal of a multiplexed secondary bearer, and 202 is a modulo 8 cyclic counter for indicating which bit of the secondary bearer input in units of octets from this input terminal 201 is to be processed. A secondary bearer input circuit 204 has a processing bit counter 203 and outputs the bit indicated by the processing bit counter 203. 204 is a register for holding the state of 1 bit, and has a first bit holding register 205 and a second bit holding register 205. a second bit holding register 206 . First bit holding register 205
, and a 3-bit pattern output circuit for configuring and outputting a 3-bit pattern in which the 1-bit 6 values from the secondary bearer input circuit 202 are arranged in the above-mentioned group number, 207 is R
A 3-bit pattern output circuit 20 consisting of OM etc.
The address is the 3-bit pattern from 4 and the conversion ratio N1, that is, the value obtained by dividing the primary bearer speed by the secondary bearer speed,
Thereby, an expansion pattern output circuit 208 outputs an expansion pattern consisting of N bits which is the same as this conversion ratio N.
The expansion pattern storage counter 209 of the module port 8 indicates where in the octet configuration of the next bearer the bits constituting the expansion pattern are stored, and which bits of the expansion pattern are stored in this expansion pattern. It has a decompression pattern processing counter 210 which is a cyclic counting counter of modifier ports N (N is the conversion ratio) to indicate whether to store the data in the position indicated by the storage counter 209, and extracts an 8-bit primary bearer from the decompression pattern. This is a primary bearer output circuit for forming and outputting.

Note that the processing bit counter 203. Bit holding register 2
05. Bit holding register 206. The six values of the expansion pattern storage counter 209 are collectively referred to as the same as in compression conversion.
It is called reference information. These values are read and written to the storage circuit 118.

Next, the operation will be explained. Here - as an example, for an asynchronous data signal with a terminal speed of 4800 bits/sec, a conversion with a primary bearer rate of 64000 bits/sec and a secondary bearer rate of 12800 bits/sec, compression conversion and decompression conversion. I will explain it separately.

(a) Compression Conversion FIG. 4 shows the concept of compression conversion from a primary bearer to a secondary bearer by bit extraction, and the conversion process shown in this figure will be explained. In the figure, 301 is the terminal speed 4800 in Figure 1.
This signal represents the output signal from the asynchronous terminal 23 with bits per second, which is multi-point sampled by a 64 kHz sampling pulse 302 at the component node 1, such as a LAN or EPBX, to obtain a 64K signal as shown in 303.
It is encoded into a bit stream with a primary bearer rate of b/S.

304 a, 304 b = 304 e--, etc. 304 indicates a delimiter when this bit string is assembled into an octet configuration in a serial-to-parallel conversion circuit (not shown) in the configuration node 1. LAN or E
In actual transmission using a PBX or the like, a plurality of pieces of data are time-division multiplexed and sent in units of octets. That is, when focusing on one primary bearer, the data passed to the bearer speed conversion circuit 27 is delivered in units of octets at regular time intervals.

305 indicates the interval at which bits are extracted. In this example, since the conversion ratio N is 5, every 5 bits are extracted. 306 indicates the transition of the value of the extraction counter 106, and bits are extracted when the value is a multiple of the conversion ratio N (including O).

Reference numeral 307 is introduced for processing time quantization bits, and represents the value of the same state counter 111 in FIG. Alternatively, it is reset to 0 due to two factors in the bit extraction operation. 308 indicates the transition of the value of the bit holding register 110, 309 indicates the transition of the value of the extraction bit holding register 109, 310 indicates the transition of the value of the change point detection register, and 311 indicates the change point position register 1.
14, where the "-" sign indicates that the value at that point has no meaning. 312 indicates the transition of the value of the bit storage counter 116. 3
13 is a bit string obtained by bit extraction and has a secondary bearer speed. However, since the bit string has not been subjected to time quantization bit processing corresponding to the changing point position of the original asynchronous data signal 301, this is equivalent to simply reducing the number of samplings of 302. Further, 314 is a bit string having a quadratic pair rate, which has been subjected to time quantization bit processing.

Hereinafter, the process of compressing and converting the five octets 304a to 304e of the primary bearer into one octet 315 of the secondary bearer will be explained in detail with reference to the flow chart of FIG. The bit position in the octet is Oth from the left in the diagram.
Bit, 1st bit, . . . 7th bit.

First, the octet of 304a is the bearer speed conversion circuit 27.
, the compression converter reads reference information such as the extraction counter value from the storage circuit 118 as preprocessing, loads it into the extraction counter, stop counter, and register, and sets an internal counter (not shown) to 0''. (Step 8'TI,
5T2). In the next VC primary bearer input circuit 102,
The bit at the position indicated by the internal counter in the octet of the primary bearer is output on line 107 (step 5T3).
).

Hereinafter, for the sake of explanation, this bit will be referred to as the X bit. Further, the bit extraction circuit 105 checks the value of the extraction counter 106, and if the value is a multiple (including 0) of the desired conversion ratio N, it instructs to extract the X bits (step 5T).
4). In the example of FIG. 4, since the extraction power kunta value is 6'' for the 0th bit, bit extraction is not performed and the process moves to step ST5. In step ST5, the above-mentioned X bit and the value of the bit holding register 110 are They are compared, and if they are equal, the same state counter 111 is incremented by one (step 5T6), and if they are different, it is reset to "O" (step 5T7).The bit before the 0th bit is ON. From here, the process proceeds to step ST6.

Further, the value of the X bit is assigned to the bit holding register 110 (step 5T8), and the extraction counter 106 is incremented by one (step 5T9). Next, the value of the internal counter is checked (step 5T10), and since it is not 7", the process proceeds to step 5T11, increments the internal counter by one, and then returns to step ST3.

Hereafter, after the same processing as the 1st, 2nd, and 3rd bits, the extraction counter value is 1 for the 4th bit.
0, and the data value "0" at that time is extracted (step 5T4). After that, the extraction counter value becomes “1”
5", "0", "5".

"1o-...", bits are extracted from the bit string of the primary bearer.The bit string obtained by repeating this process is the primary bearer bit string shown at 313 in FIG. The bit string is an asynchronous data signal 3
Since the time quantization bit processing corresponding to the change point position of 01 is not performed, this is equivalent to simply reducing the number of samplings of 302.

Since the bit has been extracted for the fourth bit, the process proceeds to step 5T121C. In step S T12, the current value of the change point detection register 113 is checked, and it is n1.
”, it indicates that a change point was detected at the previous bit extraction point, and inserts a time quantization bit.
'', the process of detecting the presence or absence of a change point is instructed. Here, the process proceeds to step ST13, and a comparison is made with the extracted bit holding register 109 to detect a change point. The bit extracted before the fourth bit is 0'', the comparison result is a match and the process proceeds to step 5T18. In step 5T18, the extracted bit, X bit, is stored in the position indicated by the bit storage counter 116 within the octet of the secondary bearer. Next, the X bit is assigned to the extracted bit holding register 109 (step 5T19), and the value of the bit storage counter 116 is incremented by one (step 5T19).
T20), and further resets the value of the same state counter 111 to 0'' (step 5T21).

As the processing progresses, at the 7th bit, since the value of the internal counter is "7" in step ST10, it is assumed that all the octets passed from the primary bearer have been processed, and the reference information such as the extraction counter value is stored in the storage circuit. 118 (step 5T22), and moves on to processing the next different primary bearer.

After a certain period of time, when the primary bearer is processed again, the reference information is loaded into each register and counter and OffTera) 30
Processing of step 4b begins. Here, the first bit is the target of extraction, but since the value of the extraction bit holding register 109 and the value of the Set register 113 to 1. In step ST15, it is determined from the value of the same state counter 111 at that time whether the change point occurs in the first half or the second half of the bit extraction interval. In this example, if the conversion ratio N is 5'',
The value of the same state counter 111 is 1", "2", "3"
”, the first half change, and “0” or “4”, the second half change.Currently, the value of the same state counter 111 is “3”.
The lick causes a change in the first half, and the process proceeds to step ST16, where the change point position register is set to 0 and then step 5T.
Proceed to step 18. In addition, the conversion ratio N "2", 4", "5""1
．． Same state counter 11 for examples of 0” and “20”
FIG. 6 shows the relationship between the value of 1, the first half change, and the second half change.

Processing progresses, and the extraction counter value becomes 'ON' in the 6th bit.
Therefore, a bit extraction instruction is issued in step ST4, but since the change point detection register 113 is 1'' in step ST12, the process proceeds to step 23 for time quantization bit insertion processing. Instead of the X bit, the value of the change point position register 114 is stored in the position indicated by the bit storage counter 116.Furthermore, the process moves to step 5T24, where the change point detection register 11
Set 3 to 'O'.

Thereafter, by repeating the above-described processing, the five octets 304a to 304e of the primary bearer can be compressed and converted into one octet 315 of the secondary bearer.

(b) Extension Conversion FIG. 7 shows the concept of extension conversion from a secondary bearer to a primary bearer by bit extension, and the conversion process shown in this figure will be explained. In the figure, 501 indicates the octet configuration of the secondary bearer formed by the previous compression conversion, and 502 indicates the octet configuration of the secondary bearer formed by the previous compression conversion.
The bit at the position indicated by the processing bit counter 203 is shown among the 8 bits of the octet of the next bearer.

Hereinafter, this will be referred to as the X bit. 503 indicates a transition in the value of the first bit holding register 205, 504 indicates a transition in the value of the second bit holding register 206, and 505 indicates a transition in the value of the processing bit counter 203. 50
6 shows again the 3-bit pattern consisting of K, which combines 3-bit data consisting of the value of the second bit holding register 206, the value of the first bit holding register 205, and the value of the y bit in the above order. It is something that

507 indicates an N-bit length expansion pattern determined by the conversion ratio N and the 3-bit pattern. 508 indicates the transition of the value of the expanded pattern processing counter 210;
09 indicates the transition of the value of the expanded pattern storage counter 209. 510a.

510b...510e...etc. 510 is an octet having a primary bearer rate formed by inserting the above expansion pattern. Reference numeral 511 indicates a 64 kHz desampling pulse for decoding performed in the constituent node 1 such as LAN or EPBX in order to return the primary bearer speed to the original terminal speed. Further, 512 indicates a decoded asynchronous data signal of 4800 pits/second.

The process by which octet 501 of the secondary bearer is expanded into five octets 510a to 510e of the primary bearer will be explained below in detail with reference to the flowchart in Figure 8. The position is the Oth bit, the 1st bit from the left in the diagram...
・Suppose.

First, when 501 octets are passed to the bearer speed conversion circuit 27, the decompression conversion unit reads reference information such as the processing bit counter value from the storage circuit 118 as a preprocessing, and loads it into the processing bit counter equal volume counter and register.
The expansion pattern storage counter is reset to θ (steps 5T31 and 5T32). Next, the secondary bearer input circuit 202 takes out the bit at the position indicated by the processing bit counter 203 in the octet of the secondary bearer (step 5T31, 5T32). 5T33).As mentioned above, set this bit to y
It is called a bit. In the 3-bit pattern output circuit 204, a second bit holding register 206, a first bit holding register 205. A 3-bit pattern is constructed by combining the values of the y bits in this order (step 5T34). In the example of FIG. 7, the second bit holding register 206, the first bit holding register 205
Assuming that the initial values of are both "0", the 3-bit pattern formed by these and the ``0'' of the Oth bit of the secondary bearer becomes ``ooo''. Then, in the expansion pattern processing circuit 207, using the conversion ratio N and the 3-bit pattern as an address, a desired expansion pattern from among the expansion patterns written in advance is retrieved from a storage element (not shown) (step 5T35). Conversion ratio N is “2”.

For the examples of "4", "5", "10'", and "20", the correspondence with the expansion pattern using the 3-bit pattern is shown in the first example.
Shown in Figure 0. From this correspondence, the 3-bit pattern is “000”
”, the expansion pattern becomes “o o o oo”.

Next, in the primary bearer output circuit 208, the bit in the N bits of the expanded pattern at the position indicated by the value of the expanded pattern processing counter 210 is transferred to the position indicated by the value of the expanded pattern storage counter 209 of the primary bearer octet. Store (step 5T36). In the above example, both the expansion pattern processing counter and the expansion pattern storage counter are "0", so the Oth bit of the expansion pattern is 0.
'' is stored in the zeroth pit of the primary bearer octet.

Thereafter, the expanded pattern storage counter 209 is incremented by one (step 5T37), and the expanded pattern processing counter 210 is also incremented by one (step 5T3B).
. Then, the next process is assigned based on the combination of the values of the expanded pattern storage counter 209 and the expanded pattern processing counter 210 at that time. Here both counters are 6
1", the process proceeds to step 5T36. After performing the same processing as the first bit, second bit, third bit, and fourth bit of the expansion pattern, the expansion pattern processing counter 210 becomes "0'', and when the expanded pattern storage counter 209 reaches 5'', the process proceeds to step 5T39 in order to retrieve a new expanded pattern. Step 5T39 is the second bit holding register 206, the first
This is a step for controlling the state of the bit holding register 205, the details of which are shown in FIG. That is, step 5T4
0, the processed 3-bit pattern is “,”0
If it is one of ``11'', 100'', and ``101'', the value of the first bit holding register 205 is substituted into the second bit holding register 206 (step 5T41).

If the 3-bit pattern is other than that, the value of the first bit holding register 205 is to be assigned to the second bit holding register 206. After step 5T42), the value of the y bit is assigned to the first bit holding register 205. (Step 5T43). In the above example, the 3-bit pattern is “ o o
o”, so steps 5T42 and 5T4
3 and newly stores the second bit holding register 20.
6 is “0”, and the first bit holding register 205K
"0" is assigned. Further, the processing bit counter 203 is incremented by one (step 5T44) and becomes ``1''. After that, the process returns to step 5T33 and a new 3
A new expansion pattern is extracted from the bit pattern and similar processing is performed. The second of the second elongation patterns
When all bits are stored in the primary bearer octet, the expanded pattern processing counter 210 becomes "3" and the expanded pattern storage counter 209 becomes 0. This means that one octet of the primary bearer has been configured, and the next 2 different
Reference information such as the processing bit counter is saved in the storage circuit 118 for processing the next bearer (step 5T45).
, the process returns to step 5T31.

Hereinafter, by such operations, the primary pair octet 51 0b, 51 0c, 5
1 0d and 51 0e are formed in sequence. And expansion pattern processing counter 2
10 is “0” and the expansion pattern storage counter 209
When becomes '0', bit retention control is performed in step 5T46, and the processing bit counter 203 is incremented by one (
Step 5T47), and the reference information is further saved in the storage circuit 118 (step ST45).

As described above, it becomes possible to multiplex compression conversion and decompression conversion of a plurality of different bearers in one circuit.

〔Effect of the invention〕

As described above, according to the present invention, compression conversion and expansion conversion are performed directly between the multiplexed bit strings of the primary bearer speed and the secondary bearer speed, so one conversion circuit can be used in a time-division manner. Since the bearer rate conversion of asynchronous data signals can be multiplexed, not only can devices be made smaller and cheaper, but also the accumulation of quantization distortion can be prevented.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing a bearer speed conversion circuit for an asynchronous data signal according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of its compression conversion section, and FIG. 3 is a similar block diagram showing its expansion conversion section. FIG. 4 is an explanatory diagram showing the process of compression conversion. FIG. 5 is a flowchart showing the control flow for compression conversion. FIG. An explanatory diagram showing an example of the standard,
FIG. 7 is an explanatory diagram showing the process of expansion conversion, FIG. 8 is a flowchart showing the control flow for expansion conversion, FIG. 9 is a flowchart showing the bit retention control routine in FIG. 8, and FIG. 11 is an explanatory diagram showing an example of conversion from a 3-bit pattern to an expanded pattern, FIG. 11 is a schematic configuration diagram showing a conventional asynchronous data signal bearer speed conversion circuit, and FIG.
The figure is a block diagram showing the configuration of the bearer speed conversion circuit. 28 is a compression converter, 29 is an expansion converter, 105 is a bit extraction means (bit extraction circuit), 108 is a change point determination means (change point determination circuit), 112 is a time doji conversion bit insertion means (time quantization bit insertion circuit), 204 is a 3-bit pattern output means (3-bit pattern output circuit), 20
5 is the first register (first bit holding register), 2
06 is the second register (second bit holding register),
207 is an expanded pattern output means (expanded pattern output circuit). In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation No. 50 Figure 8 Figure 10

Claims (2)

[Claims] (1) The primary bearer speed of an asynchronous data signal encoded with multi-point sampling using a single sampling rate is
A bit extraction means for extracting bits at the same bit interval as a conversion ratio N divided by a secondary bearer speed corresponding to the terminal speed by dual mode encoding, and a primary bearer speed within the extraction interval of this bit extraction means. 1 within the extraction interval when there is a change point in the asynchronous data signal.
The same value (“0” or “1”) in the next bearer speed bit string
Detect how many consecutive bits with ”) are present, and
a changing point determining means for determining whether the changing point occurs in the first half or the latter half of the extraction interval; and comparing the extracted bit with the bit extracted one before. and time quantization bit inserting means for determining that the change point has occurred if the values are different, and inserting a time quantization bit indicating a determination result by the change point determination means in place of the bit to be extracted next. , the primary bearer speed is 2
a compression converter for converting to the next bearer speed; and a 3-bit pattern output means for generating a 3-bit pattern for expanding the number of bits based on a combination of 3 bits in the bit string having the secondary bearer speed; An N-bit pattern consisting of the same number of bits as the conversion ratio N to be inserted corresponding to the bit pattern is stored in advance, and the N-bit pattern that corresponds to the output signal of the 3-bit pattern output means and the conversion ratio N is stored in advance. An asynchronous data signal bearer speed conversion circuit comprising: an expansion pattern output means for outputting a pattern, and an expansion conversion section for converting a secondary bearer speed to a primary bearer speed. (2) The 3-bit pattern output means has a first register that holds data for 1 bit and a second register having the same configuration, and the contents of the second register and the first
3, which combines 1 bits sequentially extracted from the bit string having the contents of the register and the secondary bearer speed in the above order.
It constitutes a bit pattern, and this 3-bit pattern is “0”.
00", "001", "110", or "111", assign the contents of the second register and the contents of 1 bit extracted from the bit string to the first register, respectively, and The bit pattern is “010”, “
011'', ``100'', or ``101'', the contents of the first register are assigned to the second register, and the first register is held as is. Bearer speed conversion circuit for asynchronous data signals as described in Section 3.