JPH05130254A - Isdn terminal equipment - Google Patents

Abstract

PURPOSE:To realize the ISDN terminal equipment capable of being connected to ISDN lines whose transmission speed differs. CONSTITUTION:A clock speed identification circuit 3 identifies whether a speed of a clock signal given from an ISDN line is 64kbit/s or 56kbit/s and gives the identification result to a data speed control circuit 4. The data speed control circuit 4 controls a data transmission circuit 2 so that the data transmission circuit 2 executes the data processing in response to the speed. Thus, the data processing such as coding or decoding in response to the identified speed is executed by the data transmission circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to ISDN (Integrated
The present invention relates to an ISDN terminal connected to a Service Digital Network) line, and more particularly to an ISDN terminal that can be connected to ISDN lines of different transmission rates.

[0002]

2. Description of the Related Art The basic interface of an ISDN line is
It is composed of two information channels (B channel) and one signal channel (D channel). Normally, the B channel has a transmission rate of 64 kbit / s, but is interconnected with a data exchange network other than ISDN having a different speed, such as an interconnection with a 56 kbit / s data exchange network existing in the United States. There are cases. In this case, the ISDN line network sends the transmission speed information of 56 kbit / s to the I side of the receiving side through the network / user interface of the D channel.
The SDN line network is notified and the called terminal is prompted to respond with a transmission rate of 56 kbit / s.
However, in general, a terminal that does not have a built-in network / user interface, that is, a terminal that is connected to an ISDN line through a network terminating device such as a terminal adapter or a communication control device, directly transmits information on this D channel. Since it cannot be received from the network and cannot detect information on the transmission rate from the other party, one device exists in one network 2
It was difficult to automatically adapt to the transmission speed of each piece. Therefore, in order to make such a terminal compatible with ISDN line connections having different transmission speeds, the user needs to take measures such as preparing a separate terminal for each line speed.

[0003]

However, preparing two ISDN terminals having different transmission speeds is a heavy burden in terms of cost and space. Further, when only one ISDN terminal corresponding to either transmission speed is prepared, there is a problem that the communication area is limited.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide an ISDN terminal that can be connected to ISDN lines having different transmission rates.

[0005]

In order to solve such problems, the ISDN terminal of the present invention comprises the following circuits. That is, as a processing unit that performs encoding processing for transmission data and decoding processing for reception data, the transmission speed is 64 kbit /
The first processing unit for data of s and the transmission speed is 56 kbi
and a second processing unit for t / s data, and a data transmission circuit. Further, a clock speed identification circuit for identifying the speed of the clock signal input from the ISDN line side,
And a data rate control circuit for selectively controlling the first or second processing unit in the data transmission circuit according to the identification result.

[0006]

In the present invention, the clock speed identification circuit is I
The speed of the clock signal applied from the SDN line side is identified and the identification result is given to the data rate control circuit. The data speed control circuit controls the data transmission circuit so that the data transmission circuit executes data processing according to the speed. That is, the first or second processing unit corresponding to the speed is effectively operated. Thus, data processing such as encoding and decoding according to the speed identified by the data transmission circuit is executed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an ISDN terminal for processing a voice signal (including an acoustic signal etc.) will be described in detail with reference to the drawings.

FIG. 1 shows a partial configuration of the ISDN terminal of this embodiment. The ISDN terminal 1 includes a data transmission circuit 2, a clock speed identification circuit 3, a data speed control circuit 4, and a voice signal input / output unit 5. The ISDN terminal 1 is connected to an ISDN line having a transmission rate of 64 kbit / s or an ISDN line having a transmission rate of 56 kbit / s, for example, via a network terminating device.

The data transmission circuit 2 includes a transmission data processing section 1
0 and a reception data processing unit 20 for processing B channel data, which encodes an audio signal input from the audio signal input / output unit 5 into transmission data and gives it to the transmission data terminal a or the reception data terminal b. The received data given by is decoded to reproduce a voice signal and given to the voice signal input / output unit 5. The data transmission circuit 2 uses a clock signal supplied from the ISDN line side via the clock terminal c when executing such processing.

The data transmission circuit 2 of this embodiment has a CCI
TT (International Telegraph and Telephone Advisory Committee) Recommendation G. The audio signal is encoded and decoded in accordance with the 7 kHz audio encoding method by 722.

FIG. 2 shows this recommendation G.264. 2A shows a data structure according to 722. In FIG. 2A, the transmission rate is 64k.
FIG. 2 shows the one for a bit / s ISDN network.
(B) shows an ISDN line network with a transmission rate of 56 kbit / s.

One data for an ISDN line of 64 kbit / s is 8 bits (1 octet), and the high frequency component of the audio signal is ADPCM for the first bit and the second bit.
The encoded high frequency side ADPCM code is inserted, and the low frequency side ADPCM code obtained by ADPCM encoding the low frequency component of the audio signal is inserted in the third to eighth bits. The least significant bit of the low-frequency side ADPCM code (which is also the least significant bit of 1 data) is, for example, CCITT Recommendation H.264. Bits constituting the frame synchronization signal and the bit rate allocation signal by 221 are appropriately inserted. That is, 8
Each bit of the frame synchronization signal of 8 bits is sequentially inserted in the least significant bit of the first 8 data of each 0 data, and the bit of the bit rate allocation signal of 8 bits is inserted in the least significant bit of the next 8 data. Each bit is inserted in order.

On the other hand, one data for the 56 kbit / s ISDN line is 7 bits (1 septed), and the high frequency component of the audio signal is AD in the first bit and the second bit.
The PCM-encoded high-frequency side ADPCM code is inserted, and the low-frequency component of the audio signal is ADP in the 3rd to 7th bits.
A CM-coded low-frequency side ADPCM code is inserted. In addition, the low-frequency side AD of this 56 kbit / s data
For the least significant bit of the PCM code (which is also the least significant bit of 1 data), as in the case of 64 kbit / s data, for example, CCITT Recommendation H.264. Bits constituting the frame synchronization signal and the bit rate allocation signal by 221 are appropriately inserted.

In order to process the transmission data having such a data structure, the transmission data processing unit 10 includes an analog / digital conversion unit 11, a band division unit 12, an ADPCM encoding unit 13 and a multiplexer 14, and receives data processing. The unit 20 includes a demultiplexer 21 and an ADPCM decoding unit 2
2. Band synthesizer 23 and digital / analog converter 24
Is equipped with.

In the transmission data processing unit 10, the analog / digital conversion unit 11 samples an audio signal at 16 kHz, the band division unit 12 divides it into high frequency components and low frequency components, and audio data of each frequency component is obtained. The ADPCM coding unit 13 performs ADPCM coding, and the multiplexer 14 performs high band ADPCM code and low band ADPCM.
The codes are multiplexed to realize the data structure shown in FIG. The frame synchronization signal and the bit rate allocation signal are inserted after the processing of the multiplexer 14. Here, the band division unit 12, the ADPCM encoding unit 13, and the multiplexer 14 (including the insertion structure of the frame synchronization signal and the bit rate allocation signal) are actually realized by software processing using a DSP (digital signal processor). Therefore, only the processing different in processing content between the processing of data having a transmission rate of 64 kbit / s and the processing of data having a transmission rate of 56 kbit / s is provided separately, and a control signal from a data rate control circuit 4 described later is used. ,
The process is branched to a process peculiar to each transmission rate. For example, the process of ADPCM-encoding the low frequency component of the audio signal and the process of inserting the frame synchronization signal and the bit rate allocation signal are separate processes for each transmission rate.

In the received data processing unit 20, the input ADPCM code is given to the demultiplexer 21 and separated into a high band ADPCM code and a low band ADPCM code, and the ADPCM decoding unit 22 receives these high band ADPCM code and low band ADPCM code. The ADPCM code is ADPCM-decoded, and the high-frequency and low-frequency audio data thus obtained are combined by the band synthesizing unit 23, and then converted into an analog audio signal by the digital / analog converting unit 24 and output. To be done. Note that the synchronization is established based on the frame synchronization signal included in the ADPCM code, and the communication mode and the like are recognized by the bit rate allocation signal. Here, the demultiplexer 21, the ADPCM encoding unit 22, and the band synthesizing unit 23 (including the processing configuration of the frame synchronization signal and the bit rate allocation signal) are also actually DS.
It is realized by software processing using P (digital signal processor), and the transmission speed is 64 kbi.
t / s data processing and transmission speed is 56 kbit / s
Only the processing whose processing content is different from that of the data processing is separately provided, and the processing is branched to the processing unique to each transmission rate by the control signal from the data rate control circuit 4 which will be described later. For example, the process of decoding the low band ADPCM code and the process corresponding to the frame synchronization signal and the bit rate allocation signal are separate processes for each transmission rate.

The transmission data processing unit 10 and the reception data processing unit 20 are functionally provided with a transmission speed of 64 kbit.
/ S data processing configuration and transmission speed of 56 kbit /
This is equivalent to providing the processing configuration of s data separately.

As a configuration for controlling the data transmission circuit 2 to execute appropriate processing according to each transmission speed, the clock speed identification circuit 3 and the data speed control circuit 4 described above are used.
And are provided.

The clock speed discriminating circuit 3 discriminates whether the speed (according to the transmission speed) of the clock signal given from the ISDN line side is 64 kbit / s or 56 kbit / s. As a specific identification method, for example, there is a method of counting the number of clocks input during 10 ms, identifying the speed as 64 kbit / s when the count value is 600 or more, and identifying the speed as 56 kbit / s when the count value is 599 or less. .. Incidentally, when there is no jitter or transmission line noise, the count value at the speed of 64 kbit / s becomes 640, and the count value at the speed of 56 kbit / s becomes 560. The clock speed identification circuit 3 gives the identified speed information to the data speed control circuit 4.

The data rate control circuit 4 outputs a control signal according to the identified clock rate to the data transmission circuit 2. When the partial configurations of the transmission data processing unit 10 and the reception data processing unit 20 of the data transmission circuit 2 are realized by software processing using the DSP as described above, the processing routine is branched to different processing routines at each speed. For example, a flag (the control signal described above) or the like is set to a value corresponding to the speed.

CCITT Recommendation G. 722 and H.M.
When the transmission data processing unit 10 and the reception data processing unit 20 are configured so as to comply with 221, a mode signal may be given to the data transmission circuit 2 as a control signal. For example, CCITT Recommendation G. In 722, the low band ADPCM coding method for 64 kbit / s is defined in mode 1,
Since the low-range ADPCM coding method in the case of 56 kbit / s is defined in the mode 2, the mode signal having such contents may be output to the data transmission circuit 2. Also, CC
ITT Recommendation H. 221 has a clock speed of 64 kbi for the frame synchronization signal and the bit rate allocation signal.
Since the mode 2 is defined in the case of t / s and the mode 3 is defined in the case of 56 kbit / s, the mode signal having such contents may be output to the data transmission circuit 2.

In the above configuration, the transmission speed is 64 kb
When connected to the it / s ISDN line, the clock speed identification circuit 3 identifies that the speed is 64 kbit / s, and the data rate control circuit 4 indicates that the data transmission circuit 2 is 6
The control is performed so as to execute the processing corresponding to 4 kbit / s, and thus the transmission / reception processing of the data of 64 kbit / s is executed. On the other hand, the transmission rate is 56 kbit / s
When connected to the SDN line, the clock speed identification circuit 3 identifies that the speed is 56 kbit / s, and the data rate control circuit 4 sets the data transmission circuit 2 to 56 kbit / s.
control to execute the process corresponding to s, thus
Transmission / reception processing of data of 56 kbit / s is executed.

Therefore, according to the above-described embodiment, the ISDN line network having a transmission rate of 64 kbit / s and the transmission rate of 5 is used.
ISDN connectable to 6 kbit / s ISDN line network
A terminal can be realized. In this way, since the speed of the ISDN line network to be connected is automatically determined, it is not necessary for the user to perform an operation for switching the speed, and an ISDN terminal with good usability can be realized.

Although the present invention is applied to the ISDN terminal for processing the audio signal in the above-mentioned embodiment, it can be applied to the ISDN terminal for handling the image signal and data itself and the ISDN terminal for handling the multimedia. The present invention can be applied.

[0025]

As described above, according to the present invention, ISD
Since the clock speed received from the N line network is identified and the processing of the transmission / reception data is controlled by the identification result, both the ISDN line with the transmission rate of 64 kbit / s and the ISDN line with the transmission rate of 56 kbit / s are used. I can handle
An SDN terminal can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a partial configuration of an embodiment.

FIG. 2 is an explanatory diagram showing a structure of data relating to an ISDN line network.

[Explanation of symbols]

1 ... ISDN terminal, 2 ... Data transmission circuit, 3 ... Clock speed identification circuit, 4 ... Data speed control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroshi Wada 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (72) Masahisa Iida 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo No. International Telegraph and Telephone Corporation

Claims (1)

[Claims] 1. As a processing unit for performing an encoding process on transmission data and a decoding process on reception data, a transmission speed is 64 k.
First processing unit for bit / s data and transmission speed of 5
A data transmission circuit provided with a second processing unit for 6 kbit / s data, a clock speed identification circuit for identifying the speed of a clock signal input from the ISDN line side, and the above data depending on the identification result. An ISDN terminal, comprising: a data rate control circuit for selectively controlling the first or second processing unit in the transmission circuit.