JPS53135232A - Main memory control system - Google Patents

Main memory control system

Info

Publication number
JPS53135232A
JPS53135232A JP5031077A JP5031077A JPS53135232A JP S53135232 A JPS53135232 A JP S53135232A JP 5031077 A JP5031077 A JP 5031077A JP 5031077 A JP5031077 A JP 5031077A JP S53135232 A JPS53135232 A JP S53135232A
Authority
JP
Japan
Prior art keywords
control system
main memory
memory control
data
accordance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5031077A
Other languages
Japanese (ja)
Inventor
Jiro Imamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5031077A priority Critical patent/JPS53135232A/en
Publication of JPS53135232A publication Critical patent/JPS53135232A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize the main memory control system by which the number of write requests is reduced, by storing write data in the data buffer until the accordance with the store data width of the memory.
JP5031077A 1977-04-30 1977-04-30 Main memory control system Pending JPS53135232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5031077A JPS53135232A (en) 1977-04-30 1977-04-30 Main memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5031077A JPS53135232A (en) 1977-04-30 1977-04-30 Main memory control system

Publications (1)

Publication Number Publication Date
JPS53135232A true JPS53135232A (en) 1978-11-25

Family

ID=12855309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5031077A Pending JPS53135232A (en) 1977-04-30 1977-04-30 Main memory control system

Country Status (1)

Country Link
JP (1) JPS53135232A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005489A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Method of nonsynchronous access to shared memory
JPH06274405A (en) * 1993-03-24 1994-09-30 Nec Corp Memory write control circuit
US6108755A (en) * 1990-09-18 2000-08-22 Fujitsu Limited Asynchronous access system to a shared storage

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131742A (en) * 1973-04-23 1974-12-17
JPS50100932A (en) * 1973-12-03 1975-08-11

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131742A (en) * 1973-04-23 1974-12-17
JPS50100932A (en) * 1973-12-03 1975-08-11

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005489A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Method of nonsynchronous access to shared memory
US6108755A (en) * 1990-09-18 2000-08-22 Fujitsu Limited Asynchronous access system to a shared storage
JP3141948B2 (en) * 1990-09-18 2001-03-07 富士通株式会社 Computer system
JPH06274405A (en) * 1993-03-24 1994-09-30 Nec Corp Memory write control circuit

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