KR930008620A

KR930008620A - System memory test method and data processing system with cache memory in data processing system with cache memory

Info

Publication number: KR930008620A
Application number: KR1019920016537A
Authority: KR
Inventors: 사또시 야마자끼; 도시아끼 후꾸시마; 미쯔히로 고다
Original assignee: 죤 디. 크래인; 인터내셔널 비지네스 머신즈 코포레이션
Priority date: 1991-10-11
Filing date: 1992-09-09
Publication date: 1993-05-21
Also published as: JPH05127994A; TW234173B; JPH0776943B2

Abstract

캐쉬 메모리를 갖는 데이타 처리 시스템에서 시스템 메모리의 테스트를 신속하게 행할 수 있도록 하는 것이다. 시스템 메모리의 테스트 프로그램을 실행할때 테스트 프로그램중의 코드 부분에 관해서는 캐쉬 메모리를 훼치되지만, 데이타 부분에 관해서는 캐쉬 메모리로 훼치되지 않도록 했다.In a data processing system having a cache memory, it is possible to quickly test the system memory. When running a test program in the system memory, the cache memory is corrupted for the code portion of the test program, but not for the data portion.

Description

System memory test method and data processing system with cache memory in data processing system with cache memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 관계되는 데이타 처리 시스템의 하나의 실시예의 주요 구성을 도시하는 블럭도,1 is a block diagram showing the main configuration of one embodiment of a data processing system according to the present invention;

제3도는 상기 실시예의 레지스터내에 유지되는 캐쉬 제어 비트와 캐쉬 제어의 내용과의 관계를 도시하는 테이블,3 is a table showing the relationship between the cache control bits held in the registers of the above embodiment and the contents of the cache control;

제4도는 상기 실시예의 의한 시스템 메모리에 요하는 시간을 종래예와 비교해서 도시하는 그래프.4 is a graph showing the time required for the system memory according to the embodiment compared with the conventional example.

Claims

In the method of testing the system memory of a data processing system with the cache memory in a data processing system having a CPU, a system memory cache memory, when executing a test program, the cache memory is discarded for the code portion of the test program. And the data portion is not fetched into the cache memory.

The system memory test method of claim 1, wherein the cache memory has a general-purpose cache memory capable of caching both a data portion and a code portion.

A CPU, a system memory for storing a program executed by the CPU, status signal generating means for generating at least a code / data signal indicating whether the CPU accesses a code portion or a data portion of the program, a cache memory; A data processing system having a cache control signal generating means for generating a signal for enabling or disabling said cache memory, said cache control signal generating means having a cache memory responsive to an output signal of said status signal generating means. Data processing system.

4. The data processing system of claim 3, wherein the cache memory is a general-purpose cache memory capable of caching both data and code portions.

The data processing system according to claim 4, wherein said cache memory has a cache memory built in said CPU.

4. The data processing system of claim 3, wherein the program is a program for testing the system memory.

4. The data processing system according to claim 3, wherein said status signal generating means has a cache memory built in said CPU.

4. The data processing system of claim 3, wherein the cache control signal generation chatter has a register accessible by the CPU, and a cache memory in which a signal for enabling or disabling the general-purpose cache memory is generated according to a value in the register. .

※ Note: The disclosure is based on the initial application.