JPS63101943A - Cache move-in control system - Google Patents

Abstract

PURPOSE:To improve the processing capacity of a whole computer system by temporarily storing move-in data and a tag corresponding to the data in a data buffer and a tag buffer at the time of move-in, and at the time of generating the succeeding move-in, writing the contents of the data buffer and the tag buffer in cache memories. CONSTITUTION:Cache move-in is controlled so that move-in data and its corresponding tag data are stored in the data buffer 21 and the tag buffer 20 for the cache memories 10, 11 at the time of move-in, the contents of the data buffer 21 and the tag buffer 20 are written in the cache memories 10, 11 at the time of generating the succeeding move-in, and at the time of the move-in the succeeding cache memory access is executed from a cycle immediately after receiving a memory access, both data buffer 21 and tag buffer 20 are processed as a part of the cache memories 10, 11. Consequently, the processing capacity of the whole computer system can be improved.

Description

Detailed Description of the Invention [Summary] In a computer system equipped with a cache memory, a data buffer (DBF) and a tag buffer (TBF) for one block of the cache memory are provided, and when moving in, a data buffer (DBF) and a tag buffer (TBF) are provided. The move-in data and the corresponding tag are temporarily stored in the data buffer (DBF) and the tag buffer (TBF), and when the next move-in is ordered, the data buffer (DBF) and the tag buffer (TBF) are stored. means for controlling the writing of the contents of to the cache memory;

The data buffer (DBF) and the tag buffer (TBF)
) is also provided with a means for handling it as part of the cache memory, so that during the move-in, the next cache access can be performed from the cycle immediately after receiving the necessary words in one block.

[Industrial application field]

The present invention relates to a move-in control method for a cache memory when a move-in occurs in a computer system equipped with a cache memory.

In recent computer systems, in order to improve the processing power of the computer system, a small capacity but high-speed cache memory is installed between the main memory (MS) and the central processing unit (CPU). Efforts are being made to shorten the apparent access time to the main memory bag f (MS) as seen from the device (CPU).

Further, as a means for improving the processing capacity of the computer system, a preemptive control method typified by a pipeline processing method has been adopted.

Therefore, there are many cases where the cache memory is accessed continuously.

However, when the cache memory is accessed and the required data block does not exist (that is, there is no hit), the data block containing the relevant data is retrieved from the main memory (MS).
It is necessary to move in a block, and during the move-in period, the cache is busy and cache access is not possible. Therefore, if there are continuous cache accesses, even after the required word is received by move-in, the next block will not be processed until the move-in of one block is completed. (Continued) (Cache access is forced to wait, disrupting the pipeline and causing performance degradation.

Therefore, for continuous access to the cache memory,
There is now a need for an effective move-in control method that can improve performance by minimizing wait times due to cache busy.

(Prior art and problems to be solved by the invention) FIG. 3 is a diagram explaining a conventional cache move-in control method, in which (a) shows an outline of a configuration example of a cache memory, and (b) is a time chart showing the operation during move-in.

Generally, the cache memory is as shown in figure (a).
Consisting of a data section 11 and a tag section 10, when the cache memory is accessed from a processing device (not shown), the access address is compared with the address of the tag section 10, and the data at the required address is exists, the comparator (C) 10a outputs a coincidence output (i.e.,
The data is read out from the data section 11 and sent to the arithmetic circuit of the processing device via the selectors (SEL) 11a and 3. However, if the data does not exist, , ``Non-hit'', and according to the instructions from the control unit (not shown), the main memory bag! A move-in operation is activated for the (MS), and l block data including data at the corresponding address is transferred from the main memory (MS) to the data section 11 of the cache memory, and at the same time, it is transferred to the corresponding tag section 10. with address.

Setting of the valid (V) bit, etc. is performed according to a predetermined procedure (for example, LRU control, etc.), and data required by the processing device is immediately transferred via the bypass route.

In a normal cache memory, in order to improve the efficiency of the move-in time, a main memory bag W (MS) (not shown) is used.
For the access data width (for example, 478 bytes), one block is configured to perform block transfer, with several times that width (for example, 32 to 64 bytes) being one block.

Therefore, writing one block of read data d0 to d into the data section 11 of the cache memory in one move-in requires several times more time as shown in FIG. (Of course, this does not include the fetch time to the main memory (MS).) In addition, in a normal cache memory, the data section 11. Normally, a memory element is used for both the tag section 10, and the next cache access is impossible while the move-in data is being written, so the next access process has to wait until the writing is finished. become.

For the access that caused the move-in above, the data required for the time being is 1. Or, since it is about 2 words, the 1 that moved in
Regardless of the position of the necessary data within the block, the required word is first fetched from the main memory (MS) and the data section 11 of the cache memory is bypassed; When there is an access to , there is a wait until 8 hours of writing (匈.' to -3') is completed.

Furthermore, when the computer system performs pipeline control, access to the cache memory occurs almost every cycle during most of the pipeline processing time, but if a move-in occurs, the effect will no longer be obtained. There was a problem.

In view of the above-mentioned conventional drawbacks, the present invention provides that, in a computer system equipped with a cache memory, the wait time caused by the cache memory's busy time is caused by a move-in performed when the cache memory does not contain necessary data. The purpose of this invention is to provide a cache move-in control method that reduces access loss.

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of a cache move-in control method according to the present invention.

In the present invention, in a computer system equipped with a cache memory (10, 11), a data buffer (21) for one or more blocks of the cache memory (10, 11) and a tag buffer (2) are provided.
0), and at the time of move-in, the move-in data and corresponding tag data are stored in the data buffer (21) and tag buffer (20), and when the next move-in occurs, the data buffer (2) is stored.
1), writes to the cache memory (10, 11) from the tag buffer (20), and writes the next cycle to the move-in time-controlled lock from the cycle immediately after receiving the required word. The data buffer (21) and tag buffer (20) are also controlled as part of the cache memory (10, 11) for normal cache memory access. Configure to handle.

[Effect]

That is, according to the present invention, in a computer system equipped with a cache memory, for example,
A data buffer (DBF) for one block and a tag buffer (TBF) are provided, and at the time of move-in, the move-in data and the corresponding tag are temporarily stored in the data buffer (DBF) and tag buffer (TBF). Then, when the next move-in occurs, the data buffer (DB
F), means for controlling the contents of the tag buffer (TBF) to be written to the cache memory, and means for treating the data buffer (DBF) and the tag buffer (TBF) as part of the cache memory, At the time of move-in, the next (cache access) can be performed from the cycle immediately after receiving the necessary words in one block, so the busy time of the cache memory associated with move-in can be shortened, and the wait time can be reduced equivalently. This has the effect of increasing the number of hits, improving the hit rate, and improving the processing capacity of the entire computer system.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing an example of the configuration of the cash move-in control method of the present invention, and FIG. 2 is a diagram showing the move-in operation according to the present invention as a time chart. For example, one block of data buffer (D
BF) 21. Tag buffer (TBF) 20. and the data buffer (DBF) 2L tag buffer (TB
F) Write routes ① and ② from 20 to the cache memory (ILIO) are necessary means to implement the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The cache move-in control system of the present invention will be explained below with reference to FIGS. 1 and 2.

Even if the present invention is implemented, the operation of detecting whether or not the required data exists in the cache memory is not particularly different from the conventional method, so it will be omitted here. Now, the cache move-in operation of the present invention will be explained with reference to FIGS. 1 and 2.

First, when a memory access is performed from a processing device (not shown) and the target data does not exist in the cache memory, that is, when a cache miss (non-hit) occurs, data is accessed from the main storage (MS), etc. (not shown). The read data d0 to d3 fetched by move-in are first sent to the data buffer (DBF) for blocks 2
1 and written to the tag buffer (TBF) 20.
The address where the data is written, the variable (V) bit, etc. are set.

The above tag buffer (TBF) 20 only needs to be one for one block of data, and in terms of timing, the move-in data has been transferred. It is sufficient if it is written in ~6. (See Figure 2) As mentioned above, the order (aO to d) of the data fetched from the main memory (MS) etc. to the data buffer (DBF) 21 is not necessarily the same as that on the main memory bag ff (MS). The order does not have to be the same as the order of . For example, a fetch function from the required word and a bypass function may be added, and in that case, the read that caused the move-in will be performed in -〇 cycles by the bypass route, as shown in Figure 2. .

Between -0 and -3 above, cache memory 10.11
Since the cache has not been written to, the next cache access can be executed from the cycle following the bypass cycle -0, thereby eliminating unnecessary waiting time and speeding up the processing.

Even if the above bypass is not performed, for example, −
If you read the access data that missed in step 1, W
The next access is possible with z.

Only when the next access is to a block within the data buffer (DBF) 21, it is necessary to make the next access wait. At that time, the comparator (C) 20a provided for the tag buffer (TBF) 20 can determine whether or not the necessary word has been taken in, and it can be determined whether to make the tag buffer (TBF) 20 wait.

For subsequent cache memory accesses, data buffer (CDBF) 2L tag buffer (TBF)
20 is also completely treated as part of the cache memory (11, 10). In this case, the result is the same as an increase in the number of ways.

After that, when a new cache miss occurs, the data buffer (DBF) 2L will
From the tag buffer (TBF) 20 to the data section 11 of the cache memory. Write to the tag section 10 using the route ■,
According to (2), the processing is performed at the timing (tll, '~-1') (see Fig. 2).This period is originally a time when processing has to be stopped, and has no effect on performance. Furthermore, considering the speed difference between the main memory (MS) etc. and the processing device, in the case of a normal configuration, there is sufficient time for writing to the cache memory.

In a cache memory that performs so-called LRU control, when writing data moved into the data buffer (DBF) 21 to the data section 11 of the cache memory,
The block to be replaced may be determined by the LRU control (2) or the like.

As is clear from the above description, the present invention can improve processing speed, but it also locally increases the cache capacity, especially the number of ways.
An improvement in the hit rate can be expected, and an improvement in processing speed can also be expected from this point of view.

By applying the present invention, the amount of hardware increases at first glance, but with the development of highly integrated technology accompanying recent advances in semiconductor technology, the entire cache control circuit is configured on one highly integrated circuit (LSI). Therefore, the increase in the amount of hardware does not become a factor that hinders the present invention.

In the above embodiment, the cache memory l011
Although the main memory (MS) has been described as an example of an upper memory for 1, the present invention is not necessarily limited to this, and the present invention can also be applied to file memory, control memory, etc. Needless to say, this is true.

Further, in the above embodiment, an example was explained in which a data buffer (DBF) for one block and a tag buffer (TBF) were provided, but the data buffer (DBF) and tag buffer (TBF) were provided for multiple blocks. It goes without saying that it is good to have more than that.

As described above, the present invention provides a computer system equipped with a cache memory with, for example, a data buffer (DBF) for one block and a tag buffer (TBF), so that a processing device can access the cache memory and perform non-history operations. At this time, the move-in data transferred from the main memory (MS) is temporarily stored in the data buffer (DB).
F) is stored in the tag buffer (TBF) and written to the cache memory when the next move-in operation is performed, thereby reducing the waiting time associated with the move-in operation when accessing the cache memory from the processing unit. It is characterized by the fact that it is short (short).

〔Effect of the invention〕

As described above in detail, the cache move-in control method of the present invention is applicable to a computer system equipped with a cache memory. ), and at the time of move-in, the move-in data and the corresponding tag are temporarily stored in the data buffer (D
BF) and the tag buffer (TBF), and when the next move-in occurs, the corresponding data buffer (DBF)
, means for controlling the contents of the tag buffer (TBF) to be written to the cache memory, and means for controlling the content of the tag buffer (TBF) to be written to the cache memory;
DBF) and tag buffer (TBF) are also treated as part of the cache memory, so that during move-in, the next cache access can be performed from the cycle immediately after receiving the necessary words in one block. As a result, the busy time of the cache memory associated with move-in can be shortened, and the number of ways has been increased equivalently, which has the effect of improving the hit rate and improving the processing capacity of the entire computer system. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a cache move-in control system according to the present invention. FIG. 2 is a time chart showing the move-in operation according to the present invention. FIG. 3 is a diagram explaining a conventional cache move-in control method. It is. In the drawing, 10 is a tag section, and 11 is a data section. 10a is a comparator (C). 20 is a tag buffer (TBF), and 21 is a data buffer (DBF). 20a is a comparator (C). 3 is a selector (SEL). d0 to d3 are read data. 10 to W3 are write timings to the data buffer (DBF). 109 ~ ゛ is the write timing to the cache. ■, ■ are data buffer (DBF), tag buffer (
TBF) to the cache memory. are shown respectively.儂漼时tW r＼

Claims (1)

[Claims] In a computer system equipped with a cache memory (10, 11), a data buffer (21) for one or more blocks of the cache memory (10, 11) and a tag buffer (2) are provided.
0), and at the time of move-in, the move-in data and corresponding tag data are stored in the data buffer (21) and tag buffer (20), and when the next move-in occurs, the data buffer (2) is stored.
1), writes from the tag buffer (20) to the cache memory (10, 11), and at the time of the move-in, access to the cache memory that follows from the cycle immediately after receiving the necessary word in the block to be moved in. control so that the data buffer (21) and tag buffer (20) are also treated as part of the cache memory (10, 11) for normal cache memory access. A cash move-in control method featuring: