JPH04268638A - Cache memory system - Google Patents

Abstract

PURPOSE:To reduce the frequency in access to a main storage part by providing a CPU with a cache memory exclusive for stack and regarding data, to which a pop instruction is executed, to be not read again and using its storage area to not write data in the main storage part at the time of executing a push instruction to another data. CONSTITUTION:Data to be stacked is temporarily stored in a data block 3. The address of the data block 3 is stored in an address tag part 2. When new stack push occurs in one set, an LUR 1 determines the way whose data should be updated to new data. Though old data in the pertinent set is updated in the case of mishit, namely, write/read of data which does not exist in the cache memory, old data is not written in the main storage part on condition that the CPU does not require updated data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory method for accessing memory at high speed in a computer system.

0002

[Background Art] Conventional cache memory methods for high-speed memory access in computer systems either write written data directly to the main memory (write-through) or replace it in the event of a write miss. Therefore, a method is adopted in which the data is finally written to the main memory.

0003

[Problems to be Solved by the Invention] As mentioned above, the conventional cache memory method is difficult to use when memory is used for temporary registers, that is, when it is used for stacks or for local variables. In this case, the data is written to the main memory even though it does not need to exist semi-permanently in the cache memory and the main memory.

That is, in the conventional cache memory method, when written data continues to have misses in the cache memory, it is saved in the main memory, but some of the data saved in this way is There is data that will never be used again. This includes data used for the stack and temporary data used for local variables.

[0005] These data are pushed once (PUS
H) The time from writing to memory to reading from memory by POP is much shorter than the write/read interval of commonly used memories.
Moreover, even though the data is often never read again, the data is written to the main memory.

Since the access time of the main memory is slower than that of the cache memory, the conventional cache memory method described above has the disadvantage that the number of accesses to the main memory increases and the processing speed of the entire system decreases. It has drawbacks.

[0007]

[Means for Solving the Problem] A data block for temporarily storing data to be stacked, an address tag section indicating in which address of the data block the data is stored, and a data block in one set. When a new stack push occurs, compare the LUR that determines which way's data will be updated with new data and whether or not the access address from the CPU is the address in the address tag section. The data to be sent from the data block to the CPU is compared with the address from the CPU and the address tag compare.
It has a word select and a way select that are selected by signals from the tag compare, and a valid bit that corresponds to the address tag and indicates whether or not the data needs to be written to the main memory when updating. A cache memory dedicated to the stack is provided in the CPU, and temporary storage data with a pop instruction is assumed not to be read again, and when another data push instruction is executed, that storage area is used to transfer data to the main memory. This is done so that it is not written.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and is a block diagram showing a 4-way set associative cache memory. FIG. 2 is a block diagram showing an example of a CPU instruction when updating data in the embodiment of FIG. It is an explanatory view showing an example.

In FIG. 1, a CPU (not shown) sends a signal indicating whether a memory access is by a stack instruction. A cache memory is enabled only when this signal is sent, and other cache memories operate during other memory accesses.

The data block 3 is a part that temporarily stores stacked data, and the address tag part 2
indicates at which address in data block 3 the data is stored. LUR1 determines which way's data is updated to new data when a new stack push (PUSH) occurs within one set. Basically, the data of the least used way is either discarded or updated with new data after being written to the main memory. Address tag compare 4 is CPU
This is where the access address from is compared to see if it is the address in the address tag section 2.
The select 5 and way select 6 are parts that select data to be sent from the data block 3 to the CPU based on the address from the CPU and the signal from the address tag compare 4.

The difference between the present embodiment configured as described above and the conventional cache memory system is the operation when a miss occurs, that is, when writing/reading data that is not in the cache memory. At this time, the old data in the set corresponding to LUR1 is updated, but when the condition (condition 1) is that the data is not required by the CPU, the old data is not written to the main storage.

Condition 1 is the following condition. That is, as shown in Figure 2, the CPU performs a PUSH and then a POP.
When address C is an update target, condition 1 is satisfied if it is after execution B, and condition 1 is not satisfied if it is between execution A and execution B. For this reason, a valid bit 2a is provided corresponding to the address tag to indicate whether or not the data needs to be written to the main memory when updating, and is referred to when updating the data.

[0014] If the size of the cache memory is set to the most frequently used amount of the stack, it becomes a guideline for the size of the cache memory without saving data to the main memory.

[0015]

Effects of the Invention As explained above, the cache memory method of the present invention uses Cache memory exclusively for stacks.
By providing it in the PU, there is an effect that the number of accesses to the main memory section can be reduced, and therefore, the performance of the entire system can be improved. This is particularly effective for systems in which the stack is used many times or systems in which interrupt processing is frequently performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and is a block diagram showing a 4-way set associative type cache memory.

[Fig. 2] In the embodiment of Fig. 1, CP at the time of data update
It is an explanatory diagram showing an example of a command of U.

[Explanation of symbols]

1 LUR 2 Address tag section 2a Valid bit 3 Data block 4 Address tag compare 5. Word selection 6 Way Select

Claims (2)

[Claims] 1. A data block for temporarily storing data to be stacked, an address tag section indicating in which address of the data block the data is stored, and a newly stacked data block in one set. LUR that determines which way data is updated to new data when a push occurs, and an address tag that compares whether the access address from the CPU is the address in the address tag section.・Compare and send data from the data block to the CPU by the C
Word select and way select that are selected based on the address from the PU and the signal from the address tag compare, and whether or not the data needs to be written to the main memory when updating, corresponding to the address tag. A cache memory method characterized in that a cache memory dedicated to a stack is provided in a CPU and has a valid bit indicating a valid bit. 2. A data block for temporarily storing data to be stacked, an address tag section indicating in which address of the data block the data is stored, and a data block for newly stacking data in one set. LUR that determines which way data is updated to new data when a push occurs, and an address tag that compares whether the access address from the CPU is the address in the address tag section.・Compare and send data from the data block to the CPU by the C
Word select and way select that are selected based on the address from the PU and the signal from the address tag compare, and whether or not the data needs to be written to the main memory when updating, corresponding to the address tag. A cache memory dedicated to the stack is provided in the CPU with a valid bit indicating the pop instruction, and the temporary storage data where the pop instruction was received is assumed not to be read again, and when a push instruction for other data is executed, the storage area is A cache memory method that is characterized in that data is not written to the main memory using the cache memory.