JPH0528414B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer memory device that maintains a copy of a portion of information in main memory.

[Conventional technology and its problems]

The buffer memory is a storage section that stores part of the information in the main memory and is composed of high-speed storage elements to enable high-speed access. Its operation is based on locality, which is a characteristic of dynamic memory access of a program in that the storage area of data and instructions to be accessed is concentrated within a very short time. In other words, by taking advantage of this property, information that is likely to be accessed repeatedly is stored in buffer memory so that it can be accessed quickly, resulting in more effective access compared to storage devices that consist only of main memory. A fast storage device can be realized.

The configuration of this buffer memory consists of a data array for storing part of the information in the main memory, a part that determines whether or not there is data to be accessed in this data array, and a part that determines whether or not the data to be accessed exists in this data array. It is comprised of a selection section that selects an output and makes it an output of the buffer memory, and a control section that controls data transfer from the main memory to the data array when it is determined that no data exists in the data array. In a buffer memory having such a configuration, the circuit passage (critical path) that requires the most processing time is often a path that passes through a portion that determines the presence of data from access address information and then a selection portion. In particular, the part that determines the presence of data requires access to a storage element similar to a data array, comparison processing of the access result with address information, and generation of a control signal for data array output selection based on the comparison result. It is.

The access time of the buffer memory and the cycle time of the processor that processes data are often approximately the same. As a result, the data read from the buffer memory is temporarily stored in the register, and the data is processed by the processor from the next machine cycle onward.

On the other hand, as an example of increasing the distance within a processor by making it possible to access data that is frequently processed faster than the buffer memory described above, there is a method in which the stack memory is realized by a hardware stack within the processor. However, introducing specific hardware within the processor as described above significantly increases the amount of hardware. In addition, in the case of a hardware stack, a large amount of control circuitry is required to manage data within the stack and to manage data transfer between the main memory and the stack, as well as high-speed storage elements for the hardware stack. This increase in the amount of hardware is accompanied by an increase in equipment cost and a longer design/inspection period.

An object of the present invention is to eliminate such conventional problems, and to provide a buffer memory function that allows faster access to specific data access specifications than conventional buffer memory. An object of the present invention is to provide a buffer memory device that improves processing efficiency to the same extent as a method that improves processing efficiency by mounting high-speed memory elements.

[Means for Solving the Problems] The present invention provides a high-speed, small-capacity data array that divides and stores a portion of data stored in main memory into multiple columns, and a and a buffer memory having an address array holding corresponding address information, and determines whether or not the data to be accessed exists in the data array by referring to the address array based on the address information for accessing the main memory. , a buffer memory device that makes data in the data array accessible by identifying columns in the data array, if any, identifying the columns in the data array without relying on a determination by the address array. means for selecting data output from a corresponding block in the data array as output data from the buffer memory device in response to a column designation access signal; and a result of referring to the address array using address information for main memory access. , if it is determined that the corresponding data does not exist in the data array while the column designation access signal is being output, a buffer for storing the corresponding data from the main memory into the column designated by the column designation access signal; and a control means for selecting data from a column in the data array designated by the column designation access signal.

[Effect]

The present invention solves the problems of the prior art through the above-mentioned means.

According to the present invention, when a signal specifying a column in the data array of the buffer memory device is applied from the outside, the output from the specified column in the data array is sent to the buffer memory device without waiting for the storage column detection result using the address array. By selecting it as an output, high-speed access from the buffer memory device is realized. As a result, when a column is specified in a processor that receives data from a buffer memory device, the data output from the buffer memory device can be manipulated without first being stored in a register. Processing efficiency can be improved.

High-speed access according to the present invention can be achieved when the externally applied column designation signal is applied at high speed or when it is applied before the start of access. In other words, faster access can be achieved than in conventional buffer memory devices that involve accessing the address array.

Furthermore, data accesses in stack operations, which are highly effective in achieving high-speed access using column designation access signals, can be broadly classified as follows.

(1) Access the oldest data in order from the newest stored data.

(2) Access any stored data, regardless of whether it is new or old.

In the case of (1) above, the stack top address that is stored most recently and indicates the beginning of the valid area of the stack, and the addresses immediately before and after that address are the targets of access. In this case, since the locality of memory access is strong, it is highly effective to hold the most recently accessed area of the stack in the buffer memory.

In case (2) above, Lisp language or
There is a stack required to process things like the Prolog language. In this stack, accesses are normally concentrated in the vicinity of the stack top address, but accesses to old data far away from the stack top address also occur. At this time, it is a normal buffer memory management method to hold data in this far away area in the buffer memory. However, even if the area is held in the buffer memory, there is a very low possibility that the area will be accessed, and the effect of buffering is small.

Furthermore, maintaining distant regions in buffer memory may itself have adverse effects.
In other words, if this area and the stack top area overlap as the storage area for the data array of a specific column, the area occupied by the stack top will be used for the distant area and will be deleted from the buffer memory. . The stack top area will be accessed soon, so again,
Since it is necessary to store the stack top area in the buffer memory, efficiency deteriorates. In order to prevent this deterioration in efficiency, when accessing a stack area far away from the stack top, data is not stored in the data array.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the buffer memory device of the present invention. In the figure, 10 is a main memory for storing data, and 12 is an address register for storing address information for accessing the main memory and buffer memory. The information stored in the address register 12 is divided into row addresses, column addresses, and block address information indicating the position within the block.

The buffer memory device stores part of the data existing in the main memory 10 in two columns, and includes a data array 50 consisting of a plurality of blocks, and two columns (column 1 and column 2) of the data array 50.
and an address array 51 which holds the information appearing in the row address field of the address register 12 corresponding to each block, and which is accessed using the column address as an address, and the address register 1.
matching circuits 52 and 53 that compare the row address information in the address array 51 read by the column address of column 2 with the row address of the address register 12 and detect whether or not they match for columns 1 and 2; Selection circuit 5 that selects one of the outputs of column 1 and column 2 of data array 50
4, a column designation access signal S sent from a processor outside the buffer memory device, and a coincidence circuit 52,
A selection control circuit 55 inputs the output information of 53 and specifies the column to be selected by the selection circuit 54; a selection circuit 56 selects the data read from the main memory 10 and the output of the selection circuit 54; A stack top pointer 57 holds the start address of the side where new data is stored, and a match circuit 58 detects a match between the row address of the address register 12 and the corresponding bit group of the stack top pointer. be a constituent element. The column designation access signal is a signal that designates column 1 access in this embodiment.

If the data to be accessed exists in column 1 of the data array 50 when the column designation access signal S is output, the buffer control unit 17 controls the selection circuit 56 to select the output of the selection circuit 54. If the data to be accessed does not exist, it is read from the main memory 10, and at this time it is controlled whether to store it in the data array 50 or not. That is, the stack top pointer 57 and the row address value of the address register 12 are compared, a match/mismatch signal is received from the matching circuit 58, and if they match, it is determined that the data is near the stack top, and the data is Main memory 10 in column 1 of array 50
Store the data read from. If they do not match, it is determined that the data is distant from the stack top, and the data read from the main memory 10 is not stored in the data array 50, but the data read from the main memory 10 is sent to the processor as is by the selection circuit 56.

Next, the operation of this embodiment will be explained. A column access instruction specifying access to column 1 of data array 50 is issued from an external processor, and the access target address is address register 1.
2. This address is a low address,
“1” in the column address and block address order
4, 4, 11". The column access command makes the column designation access signal S active, and the selection control circuit 55 activates the matching circuit 5.
2,53, the data array 50
An instruction signal is output to the selection circuit 54 so that the selection circuit 54 selects the column 1 output of. In the data array 50, by inputting the column address and block address "4, 11" of the address register 12 as addresses, corresponding data is output from columns 1 and 2 to the selection circuit 54, respectively.The selection circuit 54 outputs corresponding data to the selection control circuit. In response to a signal instructing to select column 1 from data array 55, column 1 output of data array 50 is selected as the output of selection circuit 54.

In order to check whether the data output from the selection circuit 54 actually exists in the data array 50, the contents of the address array 51 are checked by the matching circuit 52.

A case where data corresponding to the address of the address register 12 exists in the data array 50 will be described below. FIG. 2 illustrates the state of address array 51. Row address value “14” is stored in column 1 of address array 51 addressed by column address “4” of address register 12, and column 1 of corresponding data array 50 is stored.
A valid flag indicating that the block is valid is set to "1". Furthermore, a write flag indicating that writing has been performed in this block is set to "1". By inputting the column address "4" of the address register 12 into this address array 51, the row address "1" is input.
A match is detected by outputting "4" from column 1 and comparing it with the row address "14" of the address register 12 in the matching circuit 52.Furthermore, since the valid flag is also "1", the data array 50
By notifying the buffer control unit 17 that the corresponding block is valid, it is determined that the output of the selection circuit 54 is valid as the output of the buffer memory. As a result, the selection circuit 54 outputs data corresponding to the addresses "14, 4, 11",
This data is also output as the output of the selection circuit 56, and the processing as a buffer memory by the column access command is completed.

Next, address register 1 is added to data array 50.
A case where there is no data corresponding to address 2 will be explained. In this case, if address “4” in column 1 of address array 51 contains a value other than “14” or the valid flag is “0”.
In some cases, it is. In the former case, the coincidence circuit 52 detects a mismatch, and the buffer control section 17
to notify. Even if the valid flag is "0", the buffer control unit 17 is notified. In either case, the data output from selection circuit 54 is not the data requested by the column access command. Stack top pointer 57 at this time
Assume that the address indicated by is "14, 5, 10". Here, the stack grows in the direction of increasing addresses. At this time, the output of the coincidence circuit 58 indicates that the row address "14" is the stack top pointer 5.
7 and the address register 12, a match signal is output to the buffer control section 17. In response, the buffer control unit 17 determines that the data requested by the column access command is close to the stack top, reads the corresponding data and the block to which the data belongs from the main memory 10, and stores the data array 50. Store in column 1. The storage location is the area indicated by column address "4". Furthermore, the address array 51 is also updated, and the contents of column address "4" of column 1 become valid flag "1", write flag "0", and row address information "14".

The address indicated by the address register 12 is “1”
2, 4, 7". At this time, the row addresses of the address register 12 and stack top pointer 57 are "12" and "14", respectively, and the matching circuit 58 detects a mismatch. does not store data in data array 50 or update address array 51.

In this embodiment, the vicinity of the stack top refers to an area having the same row address as the stack top. FIG. 3 shows the location and vicinity of each address shown in the operation example.

When the column designation access signal S is not active, the selection control circuit 55 selects the matching circuits 52 and 5.
3 sends a control signal to the selection circuit 54 to select the column from which the matching signal is output. For example, when the column designation access signal S is not active, the address "14, 4, 11" stored in the address register 12 is referred to. If the address array 51 at this time is in the state shown in FIG. 2, both of the two inputs to the matching circuit 52 will be "14" and a match is detected, and since the valid flag is "1", column 1 will be selected. An instruction is given to the selection circuit 54.

〔Effect of the invention〕

According to the present invention, in a buffer memory device usually called a cache, which stores a part of main memory data in high-speed memory to enable high-speed access,
By receiving a signal designating the column number of the data array within the buffer memory device from outside the buffer memory device, even faster access is possible. As a result, data can be sent at high speed to an external device such as a processor that receives data from the buffer memory device, thereby improving processing efficiency in the external device.

Furthermore, according to the present invention, when performing a stack operation, data near a stack top that is frequently accessed is secured in a buffer memory device,
By not securing data remote from stack tops that are accessed infrequently in the buffer memory device, it is possible to increase the probability that the data to be accessed exists in the buffer memory device and improve usage efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a diagram showing the state of the address array at a certain point in time, and FIG. 3 is a diagram showing the position and vicinity of each address shown in the operation example. 10...Main memory, 12...Address register,
17... Buffer control unit, 50... Data array, 51... Address array, 52, 53... Coincidence circuit, 54, 56... Selection circuit, 55... Selection control circuit, 57... Static top pointer, 5
8... Matching circuit.

Claims (1)

[Scope of Claims] 1. A high-speed, small-capacity data array that stores part of data stored in main memory divided into multiple columns, and holds address information corresponding to each column in this data array. a buffer memory having an address array; the address array is referred to based on the address information for accessing the main memory to determine whether or not the data to be accessed exists in the data array; In a buffer memory device that enables data in the data array to be output to a processor by specifying a column in the data array, when an address is given by the processor to refer to data, the buffer memory device depends on the determination by the address array. As a result of selecting the data output from the corresponding block in the data array specified by the column specifying access signal specifying the column in the data array without referring to the specified column in the address array, If the selected data is found to be valid as data to be accessed, means to convert it into output data of the buffer memory device, and if it is found to be invalid, the start address of the storage area used as the stack and the column. Compare this with the reference target data address given when the specified access signal is output, and if the access is to data close to the start address, the corresponding data read from the main memory is stored in the data array and sent to the processor, and the data is accessed far away. For accesses of A buffer memory device characterized in that data in an area away from a top address of the buffer memory device is not stored in the buffer memory device.