JPH0823842B2 - Store buffer merge method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] When two consecutive stores are on an 8-byte boundary, the same bank in the main memory is accessed, and the subsequent stores are kept waiting in a bank busy state. Therefore, in such a case, if consecutive next store data is stored in the store buffer before sending the previous store request to the storage controller, the two store
Data is merged and a store request is sent to the storage controller. As a result, only one store request is required for stores in the same bank,
Bank busy makes subsequent stores less likely to wait τ. In this way, the store buffer merging method is designed to improve the performance of the partial store.

[Industrial applications]

According to the present invention, in the storage control unit (S unit) of the central processing unit, when the data stored in the two store buffers can be merged, these data are merged and sent to the storage control unit. The present invention relates to the store / buffer merge method described above.

[Conventional technology]

In the prior art, for continuous partial stores, store requests were sequentially sent to the storage control device in the order in which they were stored in the store buffer.

[Problems to be solved]

In the prior art, a storage controller that accepts a partial store fetches a bank of store addresses (8 bytes) to the main memory, sees the byte mark of the data to be stored, and stores this in the store data. Set it inside and store it in the main memory. During this period, the subsequent stores have to wait for ten and more τ in order to use the same bank.

The present invention was created in view of this point,
The purpose is to avoid such a wasteful busy state.

[Means for solving problems]

FIG. 1 is a principle diagram of the present invention. The storage control device controls main storage access from the central processing unit or the channel processing unit, and has an MCU port for accepting an access request from each processing unit. The central processing unit is composed of an S unit, an E unit and an I unit. The S unit has store buffers 8-0 to 8-3, a selective merge circuit 12, and a storage controller data-in register 13. Store from E unit
The data is stored in any of the store buffers 8-0 to 8-3. When the data bus between the central processing unit and the storage controller is empty, the data in the store buffer selected by the selective merge circuit 12 is immediately transferred to the storage controller via the storage controller data-in register. Transferred. If the data bus between the central processing unit and the storage controller is not empty, wait until it becomes empty and the data in the store buffer selected by the selective merge circuit 12 is stored in the storage controller data-in register. To the storage control device.

For example, when the partial store data (A) is stored in the store buffer 8-0 and the partial store data (B) is stored in the store buffer 8-1, it is determined whether the merge condition is satisfied. It is checked whether or not the partial store data (A) and the partial store data (B) are selected and merged.
And the merged data is sent to the storage controller via the storage controller data-in register 13.

The merge condition is that the start address of the partial store data (A) and the start address of the partial store data (B) are the same.

When the byte length of the partial store data (A) is A, the byte length of the partial store data (B) is B, and the bank width of the main memory is W (for example, 8 bytes), A + B ≦ W ( Byte) 0 ≦ A <W (byte) 0 ≦ B <W (byte)

Partial store data (A) and partial
Store data (B) does not overlap within the W byte boundary.

Is to say. The start address means the start of a W byte boundary where data is stored.

〔Example〕

The types of stores of 8 bytes or less that can be performed from the central processing unit to the storage control unit, that is, the main storage unit, are the following three cases from the viewpoint of data length.

Partial store of less than 8 bytes Partial store of 8 bytes Full store of 8 bytes Where ~ is distinguished by the operation code and byte mark sent at the same time as the store request from the central processing unit. In this case, it takes 15τ for the store to be completed between the storage controller and the main memory and the next store to be executed. On the other hand, the case of is completed in 8τ.

Therefore, in the case of consecutive stores, if addresses of the same bank are used and a request is issued with the above store type, a wasteful wait state due to bank busy should be avoided.

FIG. 2 shows the pipeline in the S unit during the store operation. In Fig. 2, EAR is an effective address register, PORT
Is OP PORT (Adress Register), STAR is Store Address Register, SDR is Store Data Register, STB is Store Buffer, and MSAR is main memory address. Register (Main Storage Address Register), M
DIR is the storage controller data in register (Mcu Data In
Register) respectively. Each state of the pipeline in the S unit will be briefly described.

P: Priority cycle This is a cycle for determining the priority of each request issued from the I unit and S unit, and creates the select signal of the address and data to be set in the register for the next T cycle.

T: TLB & TAG cycle A request whose priority has been obtained in the P cycle enters the T cycle, and the TLB and the tag (TAG) of the local buffer storage (synonymous with cache) are accessed.

B: Buffer cycle The request that entered the T cycle moves to the B cycle,
The absolute address that is accessed in the T cycle and read from the TLB is the real address register (Real Address Register
r) is set. Also, TAG MATCH
Is also detected and the data in the local buffer store is accessed to read the data.

R: Result Cycle The status for the request that has entered the R cycle is reported to the I unit and the E unit.

W: Write cycle TLB and local buffer store / tag are accessed. Also, the data from the E unit is set in SDR.

S: Store cycle Set the value of the store data register to STB.
Also, the data portion of the local buffer store is accessed.

In the case of a store that accesses the same bank in the main memory in such a pipeline, the pipeline is as shown in FIG. Here, the operation of the store buffer unit will be described along the pipeline. If the store address that has flowed through the pipeline in the R cycle is valid in the previous B cycle, the address is changed to STAR.
At the same time, set STAR VALID. This address is held until the transmission of the store request to the storage controller is completed. In the W cycle, the store data from the E unit is set in SDR. If the set data is valid, the data is set in STB in the next S cycle. At this time, a READY flag indicating that the data to be sent to the storage controller is valid is attached. This is STB READY shown in FIG. At this time, a byte mark indicating the byte length of the data is also set.

With the above, the store sent from the central processing unit to the storage control unit
The data and store address have been prepared, and after that, they will be sent to the interface control unit between the central processing unit and the storage control unit. The interface control unit waits for the data bus of the central processing unit-storage control unit to become available and asynchronously transfers data. The interface control unit of the central processing unit waits for the data bus to become empty, and then sends a store request to the storage control unit. This is the MS REQUEST shown in the pipeline. Here, MS REQUEST sends a 2τ request to the storage controller. This is because the STB has a 16-byte width, but the bus width of the interface between the central processing unit and the storage controller is 8 bytes. Because there is. The central processing unit distinguishes this 16-byte data from the upper 8 bytes and the lower 8 bytes and sends it to the storage controller. This identification flag is STB UPPER FLAG. For stores of 8 bytes or less, only the upper 8 bytes are used, so STB UPPE
Set data to MDIR only when R FLAG is on. The STAR POINTER is a pointer of a STAR having four sets and indicates which STAR is used. STB OUT POINTER
Is also a pointer to an STB having four sets, and indicates from which STB the data is sent to the storage controller.

The data selected from STB by STB OUT POINTER is MD
The data is set to IR and then sent to the storage controller. In the case of a continuous store as shown in FIG. 3, the store data (A) is sent to the storage controller, but the store data (B) As explained above, is waited for 15τ to access the same bank, and is sent to the storage controller after the bank busy is released.

Now, if the store data (A) is in a busy state on the data bus between the central processing unit and the storage control unit and waits as shown in FIG. 4, or STB UPPER in FIG.
When 1 τ is sent, the store data (B) can be sent to the storage controller when the store data (A) request is issued. Even in such a state, processing the store data (A) and (B) as separate partial stores is not possible for the latter half of the stores.
You will have to wait unnecessarily for τ.

In the present invention, the partial store data in the first half is MDIR
If the store data of the latter half is stored in STB before being set to, the latter data is merged when the previous data is set in MDIR and aligned to an 8-byte boundary and sent to the storage controller. Is. However, this is possible only for stores with the following conditions.

The start addresses of consecutive store addresses are the same.

The store data has a byte length that satisfies the following conditions.

A + B ≦ 8 (bytes), 0 ≦ A <8, 0 ≦ B <8 (bytes) A and B do not overlap within an 8-byte boundary.

Next, referring to FIGS. 4 and 5, the movement of merging is A = B =
The case of 4 (bytes) will be described.

(I) Waiting due to port busy between the central processing unit and storage controller (Fig. 4) The PORT BUSY flag is set next to when MS REQUEST is turned on, but 1 τ before that in the storage controller. Has occurred in. Therefore, at this time, no data is set in MDIR. On the other hand, STB to be set in MDIR is OUT POI
It is selected from 4 STBs by NTER, but this pointer is incremented by 1 when MS REQUEST is issued. But PORT B
In USY, DELAY OU which always shows -1 of OUT POINTER value
Select STB according to the value indicated by T POINTER and set it in MDIR.

Next, paying attention to the subsequent 4-byte store, in the address match circuit (not shown), the match of the leading address with the 4-byte store address that has flowed through the pipeline earlier is performed in B cycles. It is detected and sent to the STB control unit. The STB control unit receives this signal and
Turn on the corresponding STAR MATCH MARK latch according to the POINTER value. This is the R cycle shown by the pipeline (B).

In the S cycle, the latter 4 bytes of data are
When set to STB, set STB READY, BYTE MARK. Looking again at the pipeline (A), since the port of the storage controller is busy, even if MS REQUEST is issued, it is not yet set in MDIR. Then, in the next cycle, the port busy of the storage controller is received and the PO
Turn on the RT BUSY flag and move the STB select pointer.
Switch from OUT POINTER to DELAY OUT POINTER. On the other hand, focusing on STB UPPER FLAG, the store data can be set to MDIR because it is on at this time. Also in the pipeline (B), since the store data is already stored in the STB at this time, the data (A) and the data (B) can be merged and set in the MDIR. The data of these two STBs is merged and MDIR
STB MERGE is a signal that informs that it can be set to.

Upon receiving this STB MERGE, 4-byte data is extracted from the corresponding two STBs and set in MDIR. Also, this signal sets STB MERGE END. By this MERGE END flag, when a store request of the latter 4 bytes tries to set MS REQUEST, by forcing its own byte mark to all 0s, MS R
Change EQUEST to a dummy request and stop sending the request to the storage controller. As a result, the latter 4 bytes are not transmitted to the storage control device twice after the merge. The dummy request will be described later.

The storage control device that receives the store request determines which of the three store cases described above is based on the operation code OP CODE sent at the same time. In this case, it was sent as a partial store to the storage controller, but depending on the timing, it can be sent as a full store by modifying the operation code OP CODE. This is the case in FIG.

(Ii) When the sending of the preceding MS REQUEST of the 4-byte store is delayed (Fig. 5) The MS REQUEST from the STB may be kept waiting due to the priority of the request to the storage controller. In this case, the subsequent 4-byte store data is already STB
Since it is in the state stored in, send the STB MERGE signal and set the merged 8-byte data to MDIR. On the other hand, at this time, since the first half MS REQUEST is not set, the operation code OP CODE can be modified by using the STB MREGE signal to change the partial store to the full store. As a result, when the MS REQUEST is sent in the next cycle, the operation code OP CODE is also in full store, so the storage controller performs 8-byte full store processing.

(Iii) Merging consecutive 4-byte stores as shown in FIG. 3 Even in the case as shown in FIG. 3, STB UPPER FLAG is MS REQUE
When ST is turned on (S cycle of pipeline (B)), STB MERGE condition can be satisfied, and thus merging becomes possible. However, as in the case of FIG. 4, since the operation code OP CODE cannot be modified in time, it is processed as a partial store.

As described above, specific examples of merging are described in (i) to (iii), but the present invention positively performs data merging when the STB MERGE condition occurs.
It is an effective means for continuous data processing. The STB MERGE condition for 4 bytes is as follows: (a) The STB data in the first half is the upper 4 bytes of the 8 bytes.

(B) The start address of the STB in the second half matches the store address in the first half.

(C) The STB data in the latter half is the lower 4 bytes of the 8 bytes.

(D) When the first 4 bytes of data are set in MDIR, the latter 4 bytes are also written to STB.

Is to say.

Also, regarding the processing of the 4 bytes of store data in the latter half after merging, by setting the MERGE END flag, this flag is used to force the BYTE MARK in the latter half to all 0s and control the MCU interface. Send to department. In the MCU interface control block, BYTE MARK
If all are 0, the set condition of MS REQUEST is dropped. However, this would disturb the OUT POINTER control of the STB control unit, so a copy register of MS REQUEST was provided. BYTE MARK is all 0 in this copy register
Even though it was set, by using this, it became possible to behave as if a normal MS REQUEST was sent in the STB control section.

FIG. 6 is a diagram showing the configuration of an embodiment of the present invention. In the figure, 1-0 to 1-3 are latches to which STAR MATCH is set, 2-0 to 2-3 are latches to which operation code OP-CODE is set, and 3-0 to 3-
3 is a latch in which a byte mark is set, 4-0 to 4-3 is a latch in which STB READY is set, 5 is a decoder, 6-0 to 6-3 are byte mark check circuits, 7-0 to 7- 3 is a SET STB MERGE generation circuit, 8
-0 to 8-3 are store buffers, 9-0 to 9
-3 is a latch in which MERGE END is set, 10 is a decoder, 11-0 to 11-3 are store address registers, 12 is a select merge circuit, 13 is a MCU data-in register, 14 is a select circuit, and 15 is The main memory address registers are shown respectively. Latches 1, 2, 4, 9 are 4 each
There are 4 store buffers 8 and
There are also four address registers 11. For example, 1-0
Indicates a latch for setting the 0th (first) STAR MATCH.

Which one of the latches 1-0 to 1-3 is to be set with data is designated by a STAR pointer (not shown). Latched 2-0 to 2-3, latch 3-0
The same applies to the store addresses 3 to 3 and the store address registers 11-0 to 11-3. Store data (A)
Store address of store address register 11-
If set to 0, ST of store data (A)
B READY is set in the latch 4-0. Decoder 5
Is for decoding the operation code OP CODE selected and output from the latches 2-0 to 2-3. The byte mark check circuit 6-0 uses the latch 3
The byte mark of −0 and the byte mark of the latch 3-1 are checked, and (a) the store data has a byte length that satisfies the following condition.

A + B ≦ 8 (bytes), 0 ≦ A <8, 0 ≦ B <8 (bytes) (b) A and B do not overlap within an 8-byte boundary.

If the condition is satisfied, ON is output. Other byte mark check circuits 6-1, 6-
2, 6-3 also perform the same operation. SET STB MERGE generation circuit 7
-0 to 7-3 generate SET STB MERGE. Store data from the E unit is written in the store buffers 8-0 to 8-3. For example, if STB READY of the store data (A) is set in the latch 4-0, the store data (A) is set in the store buffer 8-0. The SET STB MERGE of the latch 7-0 is set in the latch 9-0. Other latch 9
-1,9-2,9-3 have the same function. The decoder 10 is S
It converts the operation code OP CODE in the unit into a form that can be read by the storage controller. MERGE EN
When D is generated, the opcode OP DCODE is converted from partial store to full store if there is room. Store address register 11-0 to 11
-3 is selected by the selection circuit 14, and the selected store address is the main memory address.
Set in register 15. The selective merge circuit 12 receives two sets of store data when an ON SET STB MERGE is sent.
Merge the data in the buffer. At this time, it is natural to refer to the byte mark. The output of the selective merge circuit 12 is set in the MCU data-in register 13.

FIG. 7 is a diagram showing a configuration example of the STB merge circuit. In the figure, 16 to 20 respectively indicate gates.

There are four OR gates 16 and four OR gates 17. When STB BYTE MARK 0 to 3 is 0 and 3 to 7 is 1, the OR circuit 16-0 outputs a logic "0". The other OR gates 16-1 to 16-3 have the same function. When STB BYTE MARK 0 to 3 is 0 and 3 to 7 is 1, the OR circuit 17-0 outputs logic "0". The other OR gates 17-1 to 17-3 have the same function. The OR circuits 16 and 17 form a conditional circuit for merging 4 bytes at a time.

Gate 18 has -MCU PORT BUSY 0 and -MS RE
When Q WITHOUT STB is 0, -SEL OUT POINTER is set to 0, -MCU PORT BUSY is 1 or -MS REQ WITHOUT
When STB is 1, -SEL DELAY OUT POINTER is set to 0. The gate 18 constitutes a pointer dividing circuit at the time of MCU PORT BUSY.

There are four AND gates 19 and four AND gates 20. AND gate 19-0 has -STAR MATCH MARK (1),
-MERGE BYTE MARK 1st (0), -STB READY (0),-
MERGE BYTE MARK 2nd (1), -STB READY (1), -OU
T POINTER 0, -SEL OUT POINTER is input. Other AND
Similar data is input to the gates 19-1 to 19-3. AND gate 20-0 has -STAR MATCH MARK (1),
-MERGE BYTE MARK 1st (0), -STB READY (0),-
MERGE BYTE MARK 2nd (1), -STB READY (1), -DE
LAY OUT POINTERR 0, -SEL DELAY OUT POINTER is input. Similar data is input to the other AND gates 20-1 to 20-3.

FIG. 8 is a diagram showing a configuration example of the pointer. In the figure, 21 and 22 are pointers, 23 is a +1 circuit, and 24 is a selector. Pointer 21 is STB OUT POINTER
And the pointer 22 constitutes an STB DELAY OUT POINTER. When MS REQUEST is turned on, the value of pointer 21
It is incremented by 1 by the +1 circuit 23. The value of pointer 22 is one less than pointer 21. The selector 24 is -SEL in FIG.
If OUT POINTER is 0, the value of pointer 21 is output,
-When SEL DELAY OUT POINTER is 0, the value of pointer 22 is output.

FIG. 9 is a diagram showing a configuration example of the merge end circuit. In FIG. 9, 25-0 to 25-3 are AND circuits, 2
6-0 to 26-3 are latches. As shown in FIG. 9A, the AND circuit 25-0 includes -STAR MATC.
H MARK 1 and −SET STB 0 MERGE are input. AND circuit 25
The -0 output is set in latch 26-0. Similar data is input to the other AND circuits 25-1 to 25-3, and its output is set in the corresponding latch. Latch 25-0
Or the output of 25-3 becomes STB MERGE END.

As shown in FIG. 9B, the fact that -STAR MARK 1 is 0 means that the start addresses of the STB 0 store data and STB 1 store data match.
-SET STB 0 MERGE is 0 means STB 0 store
Indicates that the data and STB 1 store data have been merged. In this case, an MCU request based on STB 0 store data is issued, but STB 1 MERGE E
ND is issued. SET MERGE END is used to stop the MCU request on the merged side (STB 1 side in this case).

FIG. 10 shows an example of the configuration of the byte mark all 0 circuit. In the figure, 27-0 to 27-3 are OR circuits, 28-
Reference numerals 0 to 28-3 are AND circuits, and 29 is an OR circuit.

The OR circuit 27-0 has STB 0 byte marks 0 to 7
Is input, and if all of these byte marks are 0, 0 is output. Similar data is input to the other OR circuits 27-1 to 27-3. The AND circuit 28-0 is the OR circuit 27-
0 outputs 0 and STB OUT POINTER outputs 1 when STB 0 is selected. Other AND circuits 28-1 to 28-3
Has the same function. The outputs of the AND circuits 28-0 to 28-3 become + SUPPRESSED STORE DATA CASE. The OR circuit 29 has + SUPPRESSED STORE DATA CASE and + STB MERGE END
Is entered. The output of OR circuit 29 is + INHIBIT MCU REQ AT
BM ALL becomes 0.

+ INHIBIT MCU REQ AT MG ALL 0 is basically sent when only the byte mark is forced to all 0s when the store data is canceled for some reason. In this case, the STB control unit has already set each control register (for example, STAR VALID signal) and has reported to the own CPU that the processing has been started in the S unit, so the processing of the S unit can be stopped. Can not. Therefore, it is necessary to stop the request to the storage control device so that the normal storage is completed in the S unit. INHIBIT MCU REQ AT BM ALL 0 is a signal generated for this purpose.

FIG. 11 is a diagram showing a configuration example of the MCU store request dummy circuit. In the figure, 30-0 to 30-3
Is an AND circuit, 31 to 33 are AND circuits, and 34 and 35 are latches, respectively. AND circuit 30-0 has -STB 0-READ
Y and −SET STB OUT POINTER 0 are input. Similar data is input to the other AND circuits 30-1 to 30-3.
The outputs of the AND circuits 30-0 to 30-3 are input to the AND circuit 31. The output of the AND circuit 31 becomes -SET MCU REQ -STB. AND circuit 32 has -SET MCU REQ-STB and + INHIBIT
MCU REQ AT BM ALL 0 is input. The output of the AND circuit 32 is set in the latch 34. The store request for latch 34 is sent to the storage controller. -SET to AND circuit 33
MCU REQ-STB is input. The output of AND circuit 33 is latch 3
Set to 5. The output of latch 35 is DUMMY MCU REQ TO
Become STB CNTL.

As described above, the + INHIBIT MCU REQ AT BM ALL 0 signal stops the store request to the storage controller, but the dummy request is set in all cases. Then, by sending this dummy request to the STB control unit and counting up STB OUT POINTER by +1, the order of the data sent from the store buffer to the storage controller is maintained.

〔The invention's effect〕

As is clear from the above description, according to the present invention,
If the data of the consecutive partial stores can be merged, the data is merged and the merged data is sent to the storage controller, so that the partial store can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a diagram showing a flow of a store operation, FIG. 3 is a diagram for explaining consecutive partial stores accessing the same bank, and FIG. 4 is a central processing unit. FIG. 5 shows a case where the store data A and B can be merged due to port busy between the storage controllers, and FIG. 5 explains the merge of the store data A and B when the previous store request is waited. FIG. 6 is a diagram showing a configuration of an embodiment of the present invention, FIG. 7 is a diagram showing a configuration example of an STB merge circuit, FIG. 8 is a diagram showing a configuration example of a pointer, and FIG. 9 is a merge end. FIG. 10 is a diagram showing a circuit configuration example, FIG. 10 is a diagram showing a circuit configuration example of a byte mark all 0, FIG.
The figure is a diagram showing an example of the configuration of the storage controller store request dummy circuit. 1-0 to 1-3 ... Latch to which STAR MATCH is set, 2-0 to 2-3 ... Operation code
Latch with OP-CODE set, 3-0 to 3-3 ...
... Latches with bite marks set, 4-0 to 4
-3 ... STB READY set latch, 5 ... decoder, 6-0 to 6-3 ... byte mark check circuit, 7-0 to 7-3 ... SET STB MERGE generation circuit, 8-0 To 8-3 ... Store buffer, 9-0
To 9-3 ... Latch where MERGE END is set, 10
...... Decoder, 11-0 to 11-3 ...... Store address register, 12 ...... Selection merge circuit, 13 ...... MCU data-in register, 14 ...... Selection circuit, 15 ...... Main memory address register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsutomu Tanaka, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References JP 61-80447 (JP, A) JP 59-136859 (JP, A) JP 58-208982 (JP, A) JP 56-54558 (JP, A)

Claims (1)

[Claims] 1. A plurality of store buffers and a storage controller data-in register to which store data of the store buffer is set, wherein store data is stored in one of the plurality of store buffers. Data stored between the central processing unit and the storage controller.
In a central processing unit that is configured to wait for the bus to become empty and send the store data stored in the store buffer to the storage controller via the storage controller data-in register, a partial store If the data (A) is stored in the i-th store buffer and the partial store data (B) is stored in the i + 1-th store buffer, the partial store data (A) The start address and the start address of the partial store data (B) are the same, the byte length of the partial store data (A) is A, the byte length of the partial store data (B) is B, and the main memory When the bank width of the device is W, there is a relationship of A + B ≦ W (byte) 0 ≦ A <W (byte) 0 ≦ B <W (byte), We shall store data (A) and partial
When the conditions such as that the store data (B) do not overlap within the W byte boundary are satisfied, the partial store data (A) and the partial store data (B) are merged and merged. Storage controller data in
A store buffer merging method characterized by sending to a storage controller via a register.