JPS6386044A - Merging system for store buffer - Google Patents

Abstract

PURPOSE:To avoid a useless busy state by merging two data stored in a store buffer with each other and sending them to a memory controller when both data satisfy the specific conditions. CONSTITUTION:A central processing unit consists of units S, E and I and the data received from the unit E are stored in one of stored buffers 8-0-8-3. Then the data selected by a selecting/merging circuit 12 are transferred to a memory controller via a memory controller data in-register 13. In case the continuous partial store data A and B, for example, are stored in buffers 8-0 and 8-1 respectively, both data A and B are merged with each other by the circuit 12 when the merging conditions are satisfied. The merging conditions requires that the head addresses of both data A and B are equal to each other, that A+B<=8, 0<=A<8 and 0<=B<8 are satisfied between data lengths A and B of both data A and B and that both data A and B never overlap with each other within an 8-byte boundary.

Description

[Detailed Description of the Invention] [Summary] When two consecutive stores are on an 8-byte boundary, the same bank in the main memory is accessed, so the subsequent store will be forced to wait due to the bank being busy. Therefore, in such a case, if the next consecutive store data is stored in the store buffer before sending the previous store request to the storage controller, these two store data are merged and the storage It sends a store request to the control device. As a result, a single store request is required for a store within the same bank, and subsequent stores are less likely to have to wait for several τ due to a bank busy state. In this way, this is a store buffer merging method that improves the performance of partial stores.

[Industrial application field]

In the present invention, in a storage control unit (S unit) of a central processing unit, when data stored in two store buffers can be merged, the data is merged and sent to the storage control device. This is related to the store buffer merging method.

[Conventional technology]

In the conventional technology, for consecutive partial stores, store requests are sequentially sent to the storage control device in the order in which they are stored in the store buffer.

[Problem to be solved]

In the conventional technology, a storage control device that accepts a partial store fetches the store address bank (8 bytes) from the main memory, looks at the byte mark of the data to be stored, and stores it. Set it in the data and store it to main storage. During this time, subsequent stores will have to wait for more than ten minutes τ to use the same bank.

The present invention was created in view of this point, and aims to avoid such wasteful busy states.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention. The storage control unit controls main memory access from the central processing unit and channel processing unit, and has an MCU boat for accepting access requests from each processing unit. The central processing unit is composed of an S unit, an E unit, and an I unit. The S unit includes store buffers 10 to 8-3, a selection merge circuit 12, and a storage controller data-in register 13. Store data from the E unit is stored in store buffers 8-0 to 8-3.
The selected merge circuit 1 is stored in one of the
2, and the data in the selected store buffer is transferred to the storage controller via the storage controller data-in register 13.

For example, partial store data (A) is
When the partial store data (B) is stored in the store buffer 8-0 and the partial store data (B) is stored in the store buffer 8-1, it is checked whether the merge condition is satisfied, and if it is, the partial store data (B) is stored in the store buffer 8-1. Store data (A) and partial store data (B) are selected by the merge circuit 12
The merged data is sent to the storage controller via the storage controller data-in register 13.

The merging conditions are: (1) The start address of partial store data (A) and the start address of partial store data (B) are the same.

■ Set the byte length of partial store data (A) to A.
When the byte length of one partial store data (B) is B, A+B≦8 (bytes).

0≦Aku8 (byte).

0≦Bku8 (byte) There is a relationship.

■ Partial store data (A) and partial store data (B) do not overlap within 8-byte boundaries.

That is what it says. Note that the start address means the start of the 8-byte boundary where data is stored.

〔Example〕

There are three types of stores of 8 bytes or less that can be performed from the central processing unit to the storage control unit, ie, the main memory, in terms of data length:

■ Partial store of less than 8 bytes ■ Partial store of 8 bytes ■ Full store of 8 bytes Here, ■ to ■ are distinguished by the operation code and byte mark sent at the same time as the store request from the central processing unit. be done. In cases (1) and (2), it takes 15τ for the store to be completed between the storage control device and the main storage device and for the next store to be executed. On the other hand, the case (■) is completed in 8τ.

Therefore, in the case of consecutive stores, if the addresses are in the same bank, requests can be issued using the store types (2) and (2) above, thereby avoiding unnecessary waiting states due to bank busy.

FIG. 2 shows the pipeline within the S unit during a store operation. In Figure 2, EAR is the effective address register.
Register), PORT is OP PORT (Ad
ress Register), 5TAR is the store data register (Store Da, ta Regis
er), STB is the store buffer y (Store B
buffer), MSAR is the main memory address register (
Main Storage Address Regis
ter) and MDIR respectively indicate a storage controller data in register (Mcu Data In Register). Each state of the pipeline in the S unit will be briefly explained.

P: Priority cycle This is a cycle that determines the priority of each request issued from inside the unit and the S unit, and creates select signals for the address and data to be set in the register for the next T cycle.

T i TLB & TAG Cycle A request prioritized in the P cycle enters the T cycle and the TLB and tag (TAG) of local buffer storage (synonymous with cache) are accessed.

B: Buffer cycle The request that entered the T cycle moves to the S cycle, and the request enters the T cycle.
The absolute address accessed in a cycle and read from the TLB is stored in the real address register (Real Address Register).
ss Register). A TAG MATCH is also detected and the data in local buffer storage is accessed and read.

R: Result cycle The status of the request that entered the R cycle is
■Reported to unit and E unit.

W-write cycle TLB and local buffer storage/tags are accessed. Also, data from the E unit is set in the SDR.

S varnish door cycle Set the value of the store data register to STB.

Also, the data portion of local buffer storage is accessed.

In such a pipeline, in the case of a store that accesses the same bank in main memory, the pipeline
It will look like the figure. Here, to explain the movement of the store buffer section along the pipeline, in the R cycle,
If the store address flowing down the pipeline was valid in the previous S cycle, the address is 5TAR
At the same time, set 5TARVALID.

This address is held until the sending of the store request to the storage controller is completed. In the W cycle, store data from the E unit is set to SDR. If the sent data is valid, the data is set in the STB in the next S cycle.

At this time, a READY flag is attached to indicate that the data to be sent to the storage control device is valid. This is STB READY shown in FIG. At this time, a byte mark indicating the byte length of the data is also set.

With the above steps, the store data and store address to be sent from the central processing unit to the storage control unit have been prepared, and will then be sent to the interface control unit between the central processing unit and the storage control unit.

The interface control unit waits for the data bus between the central processing unit and the storage control unit to become free, and then asynchronously sends and receives data. The interface control section of the central processing unit waits for this data bus to become empty and then sends a store request to the storage control unit. This is the MS REQUEST shown in the pipeline. Here MS R
EQUEST sends a 2τ request to the storage controller, but this is because the STB has a width of 16 bytes, whereas the bus width of the interface between the central processing unit and the storage controller is 8 bytes. be. The central processing unit distinguishes this 16-byte data into upper 8 bytes and lower 8 bytes and sends it to the storage control unit. This identification flag is
STB UPPERFLAG. In the case of a store of 8 bytes or less, only the upper 8 bytes are used, and therefore data is sent to MDIR only when STB UPPERFLAG is on. Note that 5TARPOINTER is a 5TAH pointer that has 4 sets, and which 5TAH
STB OUT POINT indicating whether to use R
ER is also a pointer to STB with 4 sets, and any S
Indicates whether data is sent from the TB to the storage control device.

The data selected from the STB by STB QIJT POINTER 2 is set in the MDIH and then sent to the storage controller, but in the case of continuous stores as shown in Figure 3, the store data (8) is sent to the storage controller. However, as explained earlier, the store data (B) is made to wait for 15τ in order to access the same bank, and is sent to the storage controller after the bank busy state is released.

Now, if the store data (A) becomes busy on the data bus between the central processing unit and the storage control unit and is forced to wait as shown in Figure 4, or if the STB UP occurs in Figure 3,
If PER is delayed by 1τ, when a request for store data (A) is issued, store data (B) can also be sent to the storage control device. Even in such a state, processing store data (A) and (B) as separate partial stores means that the latter store has to wait for 15τ in vain.

In the present invention, the first half of the partial store data is MDI
If the second half of the store data is stored in the STB before being set to H, what about the previous data? When setting 1DIR, the latter half of the data is merged, aligned on 8-byte boundaries, and sent to the storage control device. However, this is only possible for stores that meet the following conditions.

■ The first addresses of consecutive store addresses are the same.

■ The store data has a byte length that meets the following conditions.

A+B≦8 (byte), 0≦Aku8゜0≦Bku8
(byte) ■ A and B do not overlap within 8-byte boundaries.

Next, the merging movement is shown in Figures 4 and 5 as A=B=4
(byte) will be explained.

PORT BtlSY 7lag I'lS RRQtl
It is set after EST is turned on, but it occurs 1τ before that in the storage control device. therefore,
At this time, no data is sent to MDIH. on the other hand,
The STB that should be set to MDIR is OUT POINTE
This pointer is incremented by one when an MS REQUEST is issued. However, when PORT BUSY, always OUT POIN
DELAYOUT POINT indicating -1 of the value of TER
f! The STB is selected according to the value indicated by R and sent to the MDIH.

Next, focusing on the subsequent 4-byte store, an address match circuit (not shown) matches the first address with the 4-byte store address that flowed through the pipeline earlier in S cycles. This is detected and sent to the STB control unit. The STB control section receives this signal and
5 TAR with 8 wins according to the value of TARPOINTER
Turn on the MATC:HMARK latch. This is the R cycle shown by pipeline (B).

Also, in the S cycle, the latter 4 bytes of data are
When set to TB, STB READY, BYTE
Set MARK. Here again the pipeline (A
), the port of the storage controller is in a busy state, so even if you issue the gate S REQUEST, it is not set in MDIR yet. Then, in the next cycle, in response to the storage controller's boat busy, PORT BUSY
Turn on the flag and set the STB select pointer to OU
DELAY OUT POIN from T POINTER
Switch to TER. On the other hand, STB UPPERFLA
Focusing on G, it is on at this time, so store data can be set in MDIR. Also, in pipeline (B), the store data is already stored in the STB at this time, so data (A) and data (B) can be merged and set in MDIR. Merge the data of these two STBs and use MDIR
STB MER
It is GE.

In response to this STB MERGE, the two corresponding STs
Extract 4 bytes of data from B and set it in MDIR. Also, this signal causes STB MERGE
Set END. This MERGE END flag causes the store request for the latter 4 bytes to be
When trying to set EQUEST, by forcibly setting the own bite mark to all O, MS REQ
Change UEST to a dummy request and stop sending the request to the storage controller. This prevents the latter 4 bytes from being sent twice to the storage controller after merging. Note that the dummy request will be described later.

In the storage controller that receives and receives store requests, the operation code OP C0DE that is sent at the same time
It is determined which of the three store cases mentioned above. In this case, the data was sent to the storage control device as a partial store, but depending on the timing, it is possible to send the data as a full store by modifying the operation code OP CODE. This is the case shown in Figure 5.

Depending on the priority of the request to the storage controller, the MS REQUEST from the STB may be made to wait. In this case, the subsequent 4-byte store data has already been stored in the STB, so the STB
? 1ERGE signal was sent and merged into MDIR8
Set byte data. On the other hand, at this time, M in the first half
Since S REQUEST is not set, STB
? Operation code 0 using IREGE signal
PCODE can be modified to change from partial store to full store. As a result, when MS REQUEST is sent in the next cycle, the operation code OP C0DE will also be a full store, so the storage control device will process an 8-byte full store.

(iit) Merging of consecutive 4-byte stores as shown in Figure 3 Also in the case shown in Figure 3, STB UPPERFLAG
,l! If it turns on when REQUEST turns on (S cycle of pipeline (B)), STB M
Since the ERGE condition can be met, merging is possible. However, as in the case of Figure 4, the operation code OP
Since C0DE cannot be modified in time, it is processed as a partial store.

As mentioned above, specific examples of merging have been explained in (i) to iii), but the present invention proactively merges data when the STB MERGE condition occurs. This is an effective means for processing. STB MER when 4 bytes
The GE conditions are: (a) The first half STH data is the upper 4 bytes of the 8 bytes.

(b) The start address of the STB in the second half matches the store address in the first half.

(The STB data in the second half of C1 is the lower 4 bytes of the 8 bytes.

(dl When the first 4 bytes of data are sent to MDIR, the latter 4 bytes are also written to STB.

That is what it says.

Also, store the latter 4 bytes after merging.
Regarding data processing, by setting the MERGE END flag, this flag is used to process the second half of BYT.
Forcibly set E MARK to all O's and send it to the MCI interface control unit. ? In the ICU interface control unit, if BYTE 11ARK is all O,
The set conditions for MS REQUEST have been lowered.

However, in this case, the 01lT POINT of the STB control section
Since HR control would be disrupted, a copy register for MS REQUEST was provided. This copy register is B
Since it is set even if YTE MARK is all 0, by using this, STB! 1I41
Inside the department, it became possible to behave as if a normal MS REQUEST had been sent.

FIG. 6 is a diagram showing the configuration of one embodiment of the present invention.

In the same figure, 1-0 to 1-3 are 5TARMATC
Lunch where H is set, 2-0 to 2-3 are latches where operation code 0P-CODE is sent, 3-0 to 3-3 are latches where byte mark is sent, 4-0 is absent Nb2-3 is a latch where STB READY is set, 5 is a decoder, 6-0 to 6-3
is a byte mark check circuit, 7-0 or 7-3 is a SET STB MERGE generation circuit, 8-0 or 8
-3 is store buffer, 9-0 to 9-3 is MER
Lunch where GE END is set, 10 is decoder,
11-O and 511-3 are store address registers, 12 is a selection merge circuit, 13 is an MCU data-in register, 14 is a selection circuit, and 15 is a main memory address register. Note that latches 1, 2, 4 .
9 exist, four store buffers 8 exist, and four store address registers 11 exist. For example, 1-0 is the 0th (first) STARMA
A latch for setting TCH is shown.

A 5TAR pointer (not shown) indicates which of latches 1-0 to 1-3 to set data to. The same applies to latches 2-0 to 2-3, latches 3-0 to 3-3, and store address registers 11-0 to 11-3. Store data (A)
The store address of is stored in store address register 11.
- If set to 0, STB READY of store data (A) is sent to latch 4-0. The decoder 5 decodes the operation code OP CODE selected and output from the latches 2-0 to 2-3. Bite mark check circuit 6-
Check the byte mark of latch 3-0 and the byte mark of latch 3-1. (a) The store data has a length that satisfies the following conditions.

A+B≦8 (byte), (IA<8゜0≦Bku8
(Bytes) (b) A and B do not overlap within 8-byte boundaries.

If the condition is satisfied, an ON signal is output. Other bite mark check circuit 6-1.6
-2.6-3 also performs a similar operation.

SET STB MERGE generation circuit 7-0 or 7-
3 generates SET STB MERGE. Store data from the E unit is written to store buffers 8-0 to 8-3. For example, STB READY of store data (A) is latch 4-0.
, store data (8) is set in store buffer 8-0. SET S'rB MERGE of latch 7-0 is set in latch 9-0. Other latches 9-1.9-2.9-3 have similar functions. The decoder 10 converts the operation code OP CODE in the S unit into a form that can be decoded by the storage controller. When MERGE END is generated, if there is room, use operation code OP
DCODE is converted from partial store to full store. A store address in store address registers 11-0 to 11-3 is selected by selection circuit 14, and the selected store address is set in main memory address register 15. Selective merge circuit 1
2 merges the data in the two store buffers when an ON SET STB MERGE is sent. At this time, it is natural to refer to the bite mark.

The output of the selection merge circuit 12 is set in the FIcu data-in register 13.

FIG. 7 is a diagram showing an example of the configuration of the STB merge circuit. In the figure, 16 to 20 indicate gates, respectively.

There are four OR gates 16 and four OR gates 17. STB BYTE MARK O or 3 is O
and when 3 to 7 are 1, the OR circuit 16-
0 outputs a logic "0". The other OR gates 16-1 to 16-3 have similar functions.

When STB BYTE MARK O to 3 are O and 3 to 7 are 1, the OR circuit 17-O outputs logic "0". Other OR gates 17-1 to 17
-3 has similar functions. The OR circuits 16 and 17 constitute a conditional circuit for merging 4 bytes at a time.

Gate 18 indicates that -MCU PORT BUSY is O and -MS REQ WITHOT STB is O.
When , 5EL OUT POINTER is 0
and -MCU PORT BUSY is 1 or -MS
When REQ WITHOUT STB is 1, it is 15
EL DELAYO [IT POINTER is set to 0. The gate 18 constitutes a circuit that separates the pointer during MCU PORT BUSY.

There are four AND gates 19 and four AND gates 20.
Individuals exist. AND gate 19-0 has -5 TARM
ATCHMARK (1), - Gate ERGE BYTE Gate A
RK 1st (0).

-STB READY (0), -MERGEBYTE
MARK 2nd (1), -5TBREADY (1),
-0UT POINTERO, -5EL OUT PO
INTER is input. Similar data is input to other AND gates 19-1 to 19-3. AND game) 20-0, -5 TARMATCII MARK
(1), -MERGE BYTE MARK 1st (
0), -5TB READY (0), -MERGE B
YTE MARK 2nd (1), -5TB RE
ADY(1), -DELAY OUT POINT
ERRO, -3EL DELAY OUT POINT
ER is input. Other AND gates 20-1 or 2
Similar data is also input to 0-3.

FIG. 8 is a diagram showing an example of the configuration of a pointer. In the figure, 21 and 22 are pointers, 23 is a +1 circuit, and 24 is a selector, respectively. Pointer 21 is STB
OUT POINTER is configured, and pointer 22 is ST
B Configure DELAY OUT POINTER.

The value of pointer 21 is incremented by +1 by +1 circuit 23 when MS REQUEST is turned on. The value of pointer 22 is one less than pointer 21. The selector 24 is
If -SEL OUT POINTER in Fig. 7 is O, the value of pointer 21 is output and -5EL DELAY
If OUT POINTER is O, pointer 22
Output the value of .

FIG. 9 is a diagram showing an example of the configuration of a merge-end circuit.

In FIG. 9, 25-0 to 25-3 indicate AND circuits, and 26-0 to 26-3 indicate launches. 9th
As shown in Figure (a), the AND circuit 25-0 has -5
TARMATCHMARK 1 and -SET STB O
MERGE is input. The output of AND circuit 25-0 is sent to latch 26-0. Other AND circuit 25-
Similar data is also input to bits 1 to 25-3, and their outputs are set to the corresponding latches. Is the output of latches 25-0 to 25-3 STB? It becomes IERGE END.

As shown in FIG. 9(b), -5 TARMARK 1 is 0, which means that STBO O's store data and STB
This indicates that the start addresses of the store data No. 1 match. -3ET STB OMERGE is O
This means that STBO O's store data and STB
1 store data has been merged.

In this case, based on the store data of STBO
U request is issued, but ME for STB 1
RGE END is issued. SET MERGE EN
D is M on the side to be merged (in this case, on the STB l side)
Used to stop CU requests.

FIG. 10 shows an example of the configuration of a bite mark all O circuit. In the figure, 27-0 to 27-3 are OR circuits, 28-0 to 28-3 are AND circuits, and 29 is an OR circuit, respectively.

Byte marks 0 to 7 of STBO are input to the OR circuit 27-O, and if all of these byte marks are 0, O is output. Other OR circuits 27-1 to 27
Similar data is input to -3. AND circuit 28-
0 means that the OR circuit 27-0 outputs 0 and STBO
Outputs 1 when UT POINTER selects STBO. The other AND circuits 28-1 to 28-3 have similar functions. The output of AND circuits 28-0 to 28-3 is +5UPPRHSSED 5TORE DATA
Become a CASE. The OR circuit 29 has +5UPPRE
SSED 5TORE DATA CASE and +ST
B MERGE END is input. The output of the OR circuit 29 is +INHIBIT MCut REQ AT B
? Become I ALL O.

+INIIIBIT MCU REQ AT BM A
LLO is basically sent when the store data is canceled for some reason and only byte marks are forced to be all 0's. In this case, ST8
In the control unit, each control register has already been set (for example, the 5TARVALID signal), and the process of the S unit cannot be stopped because it has reported to its own CPυ that processing has started in the S unit. Therefore, it is necessary to make it appear as if normal storage has been completed within the S unit by stopping requests to the storage control device. I
NHIBIT MC[I REQ AT BM^shiLO
is the signal generated for this purpose.

FIG. 11 is a diagram showing an example of the configuration of the MCU store request dummy circuit. In the same figure, 30-0 to 3
0-3 are AND circuits, 31 to 33 are also AND circuits, 3
4 and 35 indicate lunch, respectively. AND circuit 3
0-0 has -5TB 0-READY and -5ET S
TB OUT POINTERO is input. Other A
Similar data is also input to ND circuits 30-1 to 30-3. The outputs of the AND circuits 30-0 to 30-3 are input to the AND circuit 31. The output of the AND circuit 31 becomes 15ET MCU REQ -5TB. AN
The D circuit 32 has -5ET MCU REQ-3TB and +INHIBIT MCU REQ AT BM A.
LL O is input. The output of the AND circuit 32 is set in the latch 34. The latch 34 store request is sent to the storage controller. The AND circuit 33 has -
5ETMCU REQ-STB is input. The output of the AND circuit 33 is set in the latch 35. latch 35
The output of DUMMY MCU REQ TOSTOB C
Become NTL.

As mentioned above, +INHIBIT MCLI REQ
The AT BM ALL O signal stops store requests to the storage controller, but a dummy request is set in all cases. And this dummy
Sends the request to the STB control unit and STB OUT
By counting up POINTER by +1, the order of data sent from the store buffer to the storage controller is maintained.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, if data in two consecutive partial stores can be merged, they are merged and the merged data is sent to the storage control device. It becomes possible to store efficiently.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing the flow of a store operation, FIG. 3 is a diagram explaining consecutive partial stores accessing the same bank, and FIG. 4 is a diagram showing the central processing unit. Store data A due to boat busy between storage controllers. Figure 5 shows the case where B can be merged.
FIG. 6 is a diagram illustrating the configuration of an embodiment of the present invention; FIG. 7 is a diagram illustrating an example configuration of an STB merge circuit;
Figure 8 shows an example of the pointer configuration, and Figure 9 shows the merge and
FIG. 10 is a diagram showing an example of the configuration of the end circuit, FIG. 10 is a diagram showing an example of the configuration of the byte mark all O circuit, and FIG. 11 is a diagram showing an example of the configuration of the storage controller store request dummy circuit. 1-0 to 1-3...Latch to which 5TARMATCH is set, 2-0 to 2-3...Latch to which operation code 0P-CODE is sent, 3-
0 to 3-3...Latch where byte mark is set, 4-0 to 4-3...Latch where STB READY is set, 5...Decoder, 6-0 to 6
-3... Byte mark check circuit, 7-Q or 7-3... SET STB MERGE generation circuit, 8
-0 to 8-3...Store buffer, 9-0 to 9-3...Latch where MERGE END is sent, 10...Decoder, 11-0 to 11-3...
・Store address register, 12... Selection merge circuit, 13... MCI+data-in register, 14
. . . Selection circuit, 15 . . . Main memory address register.

Claims (1)

[Claims] Storing store data in a store buffer;
In a central processing unit configured to set the store data stored in the buffer in the storage controller data-in register and to send the data in the storage controller data-in register to the storage controller, Before the stored partial store data (A) is set to the storage controller data-in register, the partial store data (A)
If the partial store data (B) that follows is stored in the store buffer, (1) The start address of the partial store data (A) and the start address of the partial store data (B) (2) The byte length of partial store data (A) is A, and the byte length of partial store data (B) is B.
When, A+B≦8 (bytes), 0≦A<8 (bytes), 0≦B<8 (bytes), (3) Partial store data (A) and partial store・When conditions such as data (B) do not overlap within 8-byte boundaries are met, partial store data (A) and partial store data (B) are merged and the merged data is created. storage controller data-in
A store buffer merging method characterized by sending data to a storage controller via a register.