JPH03260854A - Additional bus access control system - Google Patents

Abstract

PURPOSE:To improve the system working speed by applying a read access to a storage part from a unit connected to a main bus and transferring the data on a unit connected to an additional bus to the main bus. CONSTITUTION:A storage part 4 and an access control part 6 are provided to an interface unit 3 which secures the connection between a main bus 1 and an additional bus 2. Then a read access is applied to the part 4 from a unit 7 connected to the bus 1 so that the data on a unit 5 connected to the bus 2 can be transferred to the bus 1. Under such conditions, the part 4 stores the data and the part 6 applies a cyclical read access to the unit 5 to store the read data in the part 4. Thus no direct access is required to the bus 2 from the bus 1 and therefore the time needed for a read access applied to the unit connected to the bus 2 can be shortened. Then the system working speed is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding the access control method for the auxiliary bus, it is possible to shorten the time for read access to data of units connected to the auxiliary bus from the main bus, thereby improving the operating speed of the system. The purpose is to provide an accessory bus access control method that allows the main bus to be connected to the accessory bus. An access control unit that performs cyclic read access and stores read data in a storage unit is provided, and a unit that is connected to an attached bus by read accessing this storage unit from a unit connected to the main bus. data can be transferred to the main bus.

[Industrial application field]

The present invention relates to an access control method in an attached bus,
In particular, it relates to a data transfer control system for allowing a unit connected to a main bus to read access to a unit connected to an auxiliary bus.

For example, in systems where many input/output (Ilo) units are connected via a bus, such as a system bus, there is a limit to the number of units that can be connected to the main bus as the connected system becomes larger. It is necessary to connect the units using multiple buses.

Therefore, it has multiple attached buses, and the main bus and attached buses are connected via an interface (lF) unit, and a unit (for example, a CPU) connected to the main bus
and units connected to the attached bus (I10 unit, etc.)
A method is used to control data transfer between

If a unit like this is connected to the main bus,
In a system that performs read access to a unit connected to an attached bus via an IF unit,
It is desired that the access time be short, so that the system can be made faster.

[Prior Art] Fig. 7 shows a conventional attached bus access control system, in which 11 is a CPU, 12 is a main bus, and 13 is an I/O bus.
F unit, 14 is an attached bus, and 15 is a plurality of units connected to the attached bus.

In FIG. 7, unit I5 consists of, for example, 110 units, and when CPU II accesses unit 15,
Assume that the contents of the register provided therein are to be read.

In this case, the CPU II reads the required data from the unit 15 connected to the attached bus 14 by directly accessing the attached bus from the main bus 12 via the IF unit 13 .

[Problem to be solved by the invention]

In the conventional attached bus access control method, since the CPU connected to the main bus directly accesses the attached bus from the main bus via the IF unit, it is necessary to secure the main bus and the attached bus. 1
There is a problem in that the system operation speed decreases when the frequency of access to the attached bus increases because it takes time to transfer data once.

The present invention is an attempt to solve the RH problem of the prior art, and eliminates the need to directly access the attached bus from the main bus, reducing the time required to read and access data of units connected to the attached bus. The object of the present invention is to provide an attached bus access control scheme capable of increasing the operating speed of the system.

[Means to solve the problem]

As shown in FIG. 1, the basic configuration of the present invention is such that an interface unit 3 that connects a main bus 1 and an auxiliary bus 2 is provided with a storage section 4 and an access control section 6, and is connected to the main bus 1. By read accessing this storage section 4 from the unit 7, which is connected to the main bus 2, data from the unit 5 connected to the auxiliary bus 2 can be transferred to the main bus.

Here, the storage section 4 is provided to store data, and the access control section 6 cyclically performs read access to the unit 5 connected to the attached bus 2 to store the read data in the storage section. It has the function of storing data in 4.

[Effect]

In the present invention, an address at which an attempt is made to access a unit connected to an attached bus is written in the address storage section, and the address written in the address storage section from the access control section is independent of access to the main bus. The auxiliary bus is read accessed by the auxiliary bus, and the read data is written to the data storage section.When accessed from the main bus, the data is transferred from the data storage section to the main bus.

Therefore, when you want to read data of a unit connected to an attached bus from the main bus, read access to the data storage section will read the data of the unit connected to the attached bus stored in the data storage section. This makes it possible to access the auxiliary bus in a shorter time than when accessing the auxiliary bus directly from the main bus.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which the same parts as in FIG. 14 is a data storage unit that stores data read accessed to the unit; 18 is an access control unit that controls access timing to the attached bus and write timing of read data to the data storage unit 17;

The address of the unit to be accessed via the attached bus 14 is written in advance in the address storage section 16 from a unit (for example, CPU) connected to the main bus 12.

The access control section 18 reads the address written in the address storage section 16 and outputs it to the auxiliary bus 14, regardless of the access from the main bus 12, and performs read access.

When the read access to the attached bus 14 is completed, the next address written in the address storage section 16 is read. When all addresses written in the address storage section 16 have been accessed, the process returns to the beginning and sequentially accesses them again.

By performing read access cyclically in this manner, it is possible to always read the latest data.

The data storage section 17 writes the data read out by the access control section 18 on the attached bus 14 .

Therefore, data of units connected to the attached bus 14 can be read from the main bus 12 simply by read accessing the data storage section 17.

FIG. 3 shows the configuration at initial setting.

A memory (MEM) 20 corresponds to the address storage section 16 in FIG. 21 is a flip-flop that controls access and data switching.

Flip-flop 21 generates a Q output when data is input from main bus 12, and connects the address and data from main bus 12 to memory 20.

At the time of initial setting, the address of the memory 21 is specified from the main bus 12, and the data of the address of the unit to be accessed is given on the auxiliary bus 14, and the data is written and stored in the memory 20. A plurality of addresses may be written to the memory 20.

FIG. 4 shows the configuration during automatic reading. 2
2 is a dual port memory, which corresponds to the data storage section 17 in FIG.

23 is a command control section, and 24 is a counter.

Further, FIG. 5 shows a time chart of automatic reading.

The operation for automatically reading data from the unit connected to the attached bus 14 is performed as follows.

When the command control section 23 outputs the chip select signal C3 to the memory 20, the address data ADDRESS of the unit connected to the attached bus 14, which was stored in the memory 20, is read out.

Next, the command control unit 23 sends out a read command RD, and according to the address output from the memory 20,
When a read access is made to the unit connected to the attached bus 14, data DATA is read out from the attached bus 14, and when the unit becomes readable,
A response signal ACK is sent from the attached bus 14.

As a result, the command control unit 23 sends a write command WT to the dual port memory 22,
As a result, the data DAT output from the attached bus 14
A is written to dual port memory 22.

When the read access is completed, the command control section 23 sends out a clock CLK to cause the counter 24 to count up. When multiple addresses have been written to the memory 20, this causes the next address to be written to the attached bus 14.
The address data to be read from is read from the memory 20, and the next read access is performed.

In this case, the flip-flop 21 is controlled to give the address ADDRESS from the main bus 12 to the dual port memory 22 in accordance with the data output of the dual port memory 22, thereby specifying the address of the data to be read from the dual port memory 22. be done.

FIG. 6 shows the configuration when reading memory data.

When reading data from the main bus 12, when read access is made from the main bus 12 to the dual port memory 22, the data stored in the dual port memory 22 of the unit connected to the attached bus 14 will be read. The data is read out to the main bus 12.

〔Effect of the invention〕

As explained above, according to the present invention, in a system in which a main bus and an auxiliary bus are connected via an interface unit, read access to a unit connected to an auxiliary bus from a unit connected to the main bus is possible. Therefore, even if the number of accesses to the attached bus increases, the operating speed of the system can be prevented from decreasing.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a diagram showing the configuration at initial setting, and Fig. 4 is the configuration at automatic loading. 5 is a diagram showing a time chart of automatic reading, FIG. 6 is a diagram showing a configuration when reading memory data, and FIG. 7 is a diagram showing a conventional attached bus access control system. 1 is a main bus, 2 is an attached bus, 3 is an interface unit, 4 is a storage section, 5.7 is a unit, and 6 is an access control section. Figure 1 shows the logical configuration of the present invention Figure 2 shows the configuration at the time of initial setting of the 131F unit Figure 5 shows the automatic loading time chart Figure 5/13! Figure 13 shows the configuration when F unit is automatically read. Figure 6 shows the configuration when reading unit memory data.

Claims (1)

[Claims] In an interface unit (3) that connects a main bus (1) and an auxiliary bus (2), a storage unit (4) that stores data and a unit that is connected to the auxiliary bus (2). The access control unit (6) performs cyclic read access to (5) and stores the read data in the storage unit (4).
), and by read accessing the storage section (4) from the unit (7) connected to the main bus (1), the data of the unit (5) connected to the attached bus (2) can be read from the main bus (1). An attached bus access control method characterized by being able to transfer data to a bus (1).