JPS6324349A - Memory access device - Google Patents

Abstract

PURPOSE:To obviate a predominance difference between CPUs by driving a switching circuit of a memory address, and a switching circuit of write and read-out pulses of a memory in accordance with a command of a memory controlling circuit, and connecting one piece of storage device by a time division to plural CPUs. CONSTITUTION:A memory MR 25 is shared and used against CPU 16, 17 and 18. To the CPUs 16, 17 and 18, address counters 20, 21 and 22 are connected, respectively. A memory controlling circuit CNT 19 executes a control for operating the CPUs 16, 17 and 18 by a time division. By a command of the circuit CNT 19, a switching circuit SWA 23 of a memory address, and a switching circuit SWB 24 of write and read-out pulses of the memory are driven, and the memory MR 25 is connected by a time division to the CPUs 16, 17 and 18. In this way, a predominance difference between the CPUs is obviated, and a memory access can be executed.

Description

Detailed Description of the Invention (Industrial Application Field) Between CPUs and storage circuits when multiple CPUs use one and shared storage circuit to process data and transfer data between the CPUs. This relates to transfer control, particularly high-speed signal processing and processing unrelated to data length.

(Prior Art) FIG. 3 shows an example of a memory access circuit when a plurality of cpυ use one shared storage device. FIG. 3 is an example in which three CPUs are used. 1, 2.3 is CPU, 4
is a memory control circuit (CNT), 5 is a memory address setting pulse switching circuit (SWA), 6 is a memory address counter (AD>, 7 is a write/read pulse switching circuit (SWB) for the memory device CF'lR), Note that 16 is a signal circuit for a memory address setting pulse (5) and data writing, and a successive pulse switching circuit (7), and 8 is a memory (MR). Further, 9 is a data bus for exchanging data between the CPII (1, 2, 3), the address counter (6), and the memory (MR)<81. These operations are as follows.

In FIG. 3, when data transfer is required between any of the CPUs (1, 2, 3) and the memory device (MR) +81, a memory write or read request is made to the memory control circuit (CNT) (4). from each CP[I to the control circuit (4
) via request signal lines 10.12 and 14, the control circuit (4) outputs a request signal to each CPU (12, 3) via permission signal lines 11.13 and 15 to the memory ( 8) Permission to use is granted. The above is for each CP
In the case where there is no conflict in the relationship between u and memory (8),
Next, when memory usage from multiple CPUs overlaps, the process is as follows.

Permission is granted to the CPU that made the request first, and after the data transfer is completed, permission is granted to another CPU. In this way, the memory control circuit (4) that controls the transfer between CP[I and the memory (8) generates the setting pulse of the address counter (6) and the writing of the memo (January 8).

It also controls the operation of the read pulse, and also controls the switching circuits (5) and (7) related to these so that the output of the CPU is connected to the address counter (6) and the memo (January 8). The procedure for reading and writing the memo (January 8) is as follows:
After obtaining permission to use 8), set the memory address in the address counter (6) via the data bus (9), and then write the memo 8) via the data bus (9). This is for reading. Address counter (6
) is counted up by one each time a memo (January 8) is written or continued.

With the above, data of arbitrary length can be continuously written or read. Figure 4 is an operation time chart of the circuit in Figure 3, and shows data transfer requests from CPU (11) and CPU (
An example of a case where data transfer requests from 21 are duplicated is shown below.
It is assumed that both write to the memory (8).

The a waveform in FIG. 4 is the system timing clock, and the b waveform is the data transfer request signal 01m from the CPU (11).

The C waveform is the permission signal αυ from the memory control circuit (4) to the CPU (11), the d waveform is the data transfer request signal @ from the CPU (21), and the C waveform is the permission signal αυ from the memory control circuit (4) to the CPU (21). Permission signal 0 country, l waveform is CPU (
Output from 1) to data bus (9), g waveform is from CPU
(Memory address setting pulse from 11, h waveform is CP
Memory write pulse from U (1), l waveform is CPU
(Output from 21 to data bus, l waveform is CPU (
Memory address setting pulse from 21, l waveform is CPU
The memory write pulse from (2), l waveform is the data on the data bus (9). Since the CPU (memo January 8 for the waveform requesting data transmission from 11) is in an empty state, permission for transfer is immediately granted and the address is set by the memory address setting pulse g waveform (-11J).
-), data is stored in memory by write pulse h waveform (8)
(-rollo direct rollo), thus A indicates address data and D indicates write data. CPU
(11 is C waveform note I month 8) to data bus (9)
Even if there is a data transfer request d waveform from CPU f21, permission is not given to CPU (2) immediately because the memory (8) is in operation, and as shown in waveform C, the transfer of CPt1 (11 is completed). Then the b waveform is released and later enabled by the CPU (l waveform related to 2+).

In the data bus (9), as shown in the data! waveform, when the waveforms of f and i are respectively set, the address setting and memory writing are performed by control as in the case of CPt1 (11). It takes the form of series series.

(Problems to be Solved by the Invention) In such a conventional method, if another CPU is using the memory, the use of the memory is forced to wait.

(1) When a general CPU tries to use memory, it is unknown how many CPUs and how many words of data will be transferred, so it is difficult to predict the waiting time, and (2) When assembling a program for each CPU, it is required to program it so that it can write and read immediately even after the maximum time that other CPUs would use the memory. (3) Efficiency of high-speed processing in real-time processing This is a factor that reduces the

(Means for Solving the Problems) The present invention solves the above-mentioned drawbacks, and each CP
The memory usage time for each U is allocated to each CPU by time division, and each CPU accesses the CPU and memory in a fixed time order.

(Function) With this kind of circuit, when each CPU transfers data to and from the memory, it first sets the address counter and then writes or reads the memory at each assigned timing of each CPU. .

Next, the same operation as described above is performed for the next CPU, and after checking all necessary CPUs, the process returns to the first CPII.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention. 3 CPUs
In this example, 17.18.19 is the CPU.

20 is a memory control circuit (CNT), 21.22.23
is the memory address counter (AD) for each CPU, 2
4 is a memory address switching circuit (SWA) for outputting the memory address, 25 is a memory write pulse switching circuit (SWB) for each CPU, and 26 is a memory (
MR), 27 is a data bus connecting the CPU, address counter and memory. The memory control circuit (2Φ) in the present invention operates differently from the memory control circuit (4) in FIG. These two points are also features of the present invention.

Now, in Fig. 1, the address counter (211 is CP
The address counter □□□ is fixed for U0η, the address counter (company) is fixed for CPUa, and the address counter □□□ is fixed for CPU CII. In addition, each CPU serves as a counter that also serves as a register indicating the address of the memory to be written or read, and its output is switched by the switching circuit t24) to the memory address signal by the switching signal from the control circuit t2. Become. In the present invention, the memory control circuit 120) divides the system timing clock and divides the frequency of each CPIJ (17
, 18° and 19), a time-division timing signal is applied so that the data can be transferred to and from the memory one word at a time. This is the timing signal (28, 29, 30) that is input to each CPU from the control circuit (2), and each CPU uses the address counter (2) only at the time specified by this timing signal.
Write data to (1.22 or 23) and memory (a).

A memory control circuit (2ω) that can read out the address counter (2ω) simultaneously and synchronously with these timing signals.
21, 22 or 23) and a switching signal for switching the memory write/read pulses to the switching circuit (company). The operation of the address counters (21, 22, 23) is similar to that shown in Figure 3.
Address data on the data bus is set by the address count setting pulse from U, and is counted up one by one by the memory write and read pulses.

By using such a circuit, if each CPU transfers data with the memory (A), the address counter (21
, 22 or 23), and then write or read the memory. These will be explained in detail below using the time chart of FIG. The second part is CPUa power and C
This is an example in which the PU (18) performs memory writing. In Figure 2, m is the system timing clock, and n is the CPU a.
Assignment timing signal for n (when at H level) @
, p is the allocation timing signal (to) for CPU am, q is the allocation timing signal for CPU Q91, r is the output from CPU aη to the data bus, S
is the address setting pulse (21+,
t is memory write pulse from CPU Qη, U is CP
Output from UQ8) to the data bus, V is the address setting pulse from the CPUCl group, W is the memory write pulse from the CPU Q8), and X is the data on the data bus.

The time each CPU can access the data bus is n.

The time specified by the timing signals shown in p and q (H
level), and this time is for all C as shown in the figure.
They are allocated in the order of PUs (17, 18, 19). When the CPU aη tries to access the memory, it first outputs address data to the data bus using the timing assigned to it like the r, s waveform, and then sends the address to the address counter using an address setting pulse. Set. Next, data is output to the data bus from the next self-assigned timing, and data is written into the memory by a write pulse, and this state is continued until writing of the necessary data is completed. At this time, the memory address is changed to cpu by a switching signal from the control circuit.
An address counter for η is selected.

CP 008 while writing from cpuaη continues
Even if memory access from 1 is required, a different timing is assigned by the timing signal p, so u,
As shown in the v and w waveforms, address counter setting and memory writing or reading can be performed immediately without waiting time. Also, the post regarding CPU aω is cpu Q71
It is the same as when The data on the data basket (X) and the data from the illustrated CPUs (lη and CPUCl8) perform multiple operations in a time-sharing manner.

(Effects of the Invention) As explained above about the structure and operation of the present invention, a plurality of CP
When configured with U and one memory, the conventional phenomenon in which the preceding CPU and memory occupy the data transfer and other CPUs have to wait for the completion of the preceding data transfer is eliminated, and multiple Since the CPUs can use the shared memory in a time-sharing manner, the difference in advantages between the CPUs has been successfully eliminated.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the configuration of the present invention, Fig. 2 is a time chart diagram of Fig. 1, Fig. 3 is a block diagram of the conventional configuration, and Fig. 4 is a block diagram of the conventional configuration.
The figure is a time chart diagram of FIG. 3. 1, 2. 3. 17. 18. 19...CPt
1, 4.20... memory control circuit, 5, 24...
・Memory address switching circuit, 6.21.22.23・
...Memory address counter, 7.25...Memory write/read pulse switching circuit, 8,26...Memory, 9,27...CP[I, data bus connecting address counter and memory. be.

Claims (1)

[Claims] When multiple CPUs share one memory device, each of the multiple CPUs has a memory address counter (21, 22, 23), and a memory control circuit (20) that controls the time-sharing operation of the multiple CPUs. ), and a memory address switching circuit (24) and a memory write/read pulse switching circuit (25) are driven by the command from the memory control circuit to time-divide the memory (26) for the plurality of CPUs. A memory access device characterized by having a connection configuration.