JPS6083164A - Bus control system - Google Patents

Abstract

PURPOSE:To shorten the access time and to improve the performance of a bus control system for an information processor which uses a common bus, by providing a signal which switches an operation mode between an arithmetic processor and a bus control part. CONSTITUTION:An arithmetic processor 3 has two modes for a common bus 1, and the selection between both modes is informed to a bus control part 21 by the signal of an operation mode signal line 100. Then the switching is carried out for control of the bus using right. When the reading is ended with data given from a main memory 2 of an input/output controller 4 in a certain mode, it is possible to accept the next bus using right. In this case, signals are transmitted among bus using right request signal lines 41 and 51 as well as bus using right answer signal lines 42 and 52 of input/output controllers 4 and 5, a bus using right request signal line 31 and a bus using right answer signal line 32, respectively. Thus a desired operation mode is set. Then it is possible to operate the bus 1 as if it has artificially two buses.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a common bus control system in an information processing device.

BACKGROUND OF THE INVENTION A conventional bus control system for an information processing apparatus using a common bus will be described with reference to FIGS. 1 and 3. Referring to Figure 1, in the conventional common bus control method, the common bus 1
．． Main storage device 2. It is composed of an arithmetic processing unit 3 and input/output control units 4 and 5, and the main memory has a bus control unit 21 that controls the use of a common bus. Information such as addresses, data, and control signals are transferred between each device via the common bus 1. Furthermore, in order to control the right to use the common bus, separate bus right request signal lines 31.4 are provided between the arithmetic processing unit, the input/output control device, and the bus control unit.
1 and 51, the bus control circuit 21 receives one of the request signals, and the bus control circuit 21 receives the bus use right response signal line 3.
2.42'l: or 52 to notify that the right to use the bus has been assigned.

FIG. 3 shows a time chart of the data read operation from the main memory device using the common bus. If the common bus is controlled in clock synchronization, the input/output control device 4 outputs all request signals to the bus right request signal line 41 at time To as shown in the figure. Since no request signal is output to the other bus use right request signal lines 31 and 51, the bus control unit 21 outputs a request signal to the input/output control device 4 at time T1.
It notifies the bus controller 21 that the bus usage right has been assigned via the bus usage right response signal line 42, and also sets the busy register of the bus control unit 21. The input/output control device 4, which has obtained the right to use the bus, resets the bus right request signal line 41 at time T2 and outputs a signal necessary for a read operation to the main storage device 2 to the common bus 1. The main storage device 2
receives the signal on the common bus 1, executes the bladder removal operation from time T3, and outputs read data to the common bus 1 at time T4. When the bladder removal operation is completed, the bus control circuit 21 resets the previously set busy register at time T5 and allocates the next bus usage right.

Next, between time T7 and TH, the arithmetic processing unit 3 outputs the bus right request signal 31 and the bus right response signal 32.
Data is read from the main memory device 2 when the right to use the bus is assigned in .

The operation by the common bus in this case is exactly the same as the time chart from time Illo to T5 by the input/output control device 4 described above. At this time, the access time TA1 from the output of the bus use narrowing signal 31 until the read data is output to the common/(S1) is the clock cycle t-I.
If it is T, it becomes 4T.

Now, assuming that there is a dedicated bus between the arithmetic processing unit 3 and the main storage device 2, the time required for controlling the right to use the bus from time T7 to T8 in the time chart shown in Figure 3 is The access time T'AI seen from the unnecessary data processing device 3 may be 2T.

Generally, the access time seen from the arithmetic processing unit in an information processing device is important for the performance of the information processing device. However, in an information processing device that uses a bus (common to the above), there is a deficiency in that the access time seen from the arithmetic processing device becomes slow because the bus usage right control time C is included in the access time.Purpose of the Invention SUMMARY OF THE INVENTION An object of the present invention is to provide a bus control method for shortening the access time to an arithmetic processing unit and realizing a high-performance information processing device.

Structure of the Invention The purpose of the bus control method according to the present invention is to shorten the access time of the arithmetic processing unit in an information processing device having a common bus to which a main storage device, an arithmetic processing unit, an input/output control device, etc. are connected. It is. Bus control of an information processing device that uses a common bus generally involves first generating a bus usage right request, then determining and responding to the bus usage right, and then outputting the information to be processed to the common bus. Therefore, all bus operations require time to determine the right to use the bus, which is undesirable in terms of performance.In order to solve this problem, the present invention provides the above-mentioned general operation mode from the arithmetic processing unit to the bus control unit. By providing an operation mode signal indicating that the arithmetic processing unit operates in a different mode, when the operation mode signal is valid and there is no request for bus usage rights from any processing unit connected to the common bus, the arithmetic processing unit By outputting a response signal to
Embodiments of the Invention Next, an embodiment of the present invention is shown in FIGS. This will be explained in detail using FIG.

Referring to FIG. 2, one embodiment of the present invention provides a common bus 1
, a main storage device 2 having a bus control section 21, an arithmetic processing device 3 and input/output control devices 4 and 5, and a common connection between the arithmetic processing device 3 and the bus control section 21 in the main storage device 2. An operation mode signal line 100 that transmits an operation mode signal related to bus 1, and a bus usage right request signal line 31
．． 41 and 51 and bus right response signal line 32.4
2 and 52.

In one embodiment of the present invention, the arithmetic processing unit 3 has two operating modes with respect to the common bus 1, and each mode is referred to as a first operating mode and a second operating mode.

The path control unit 21 determines in which operation mode the common bus 1 is used depending on the signal on the operation mode signal line 100.
is notified, and the bus usage right control is switched.

The first operation mode is when the operation mode signal line 100 is at logic tIO'', and this is exactly the same as the operation from time Illf to T12 in the time chart of FIG. 3 explained in the conventional bus control method. It is.

On the other hand, in the second operation mode, the operation mode signal line 100
is the case where the logic is 11". In the time chart of FIG. 4, the operation mode signal 100 becomes the logic "1" at time T4.
The operation processing unit 3 notifies the bus control unit 21 that the common bus will be used in the second operation mode. When the data read operation from the main storage device 2 of the input/output control device 4 that was accepted at time T1 is completed, the busy register in the bus control section 21 is reset at time T5,
The next bus usage right can be accepted. At this time time Ts
Since the bus right request signals 41 and 5 of the input/output control devices 4 and 5 are not outputted at , the bus control section 21 transmits the bus right request signal line 3 from the arithmetic processing device 3 to the bus right request signal line 3.
Even if no signal is output to the common bus 1, the bus usage right response signal line 32 is output at time T6 to notify the arithmetic processing unit 3 that the common bus 1 is currently available for use. In response, the arithmetic processing unit 3 outputs a bus usage right request signal 31 at time 1'7, and also outputs a signal for accessing the main storage device 2 to the common bus l. Bus control section 2
1 is the bus usage right request signal #i! 31 signal at time T
At step 8, the reception resets the previously output bus right response signal line 32 and sets the busy register. In parallel with this, the main memory device 2 receives the signal output from the arithmetic processing device 3 to the common bus 1, starts a data read operation at time T8, and outputs the read data to the common bus 1 at time T9. At this time, the access time TA2 from when the bus right request signal 31 is output until the read data is output to the common bus 1 is 2T in clock cycles. Therefore, since the access time TA1 of the conventional bus control method shown in FIG. 3 was 4T in clock cycles, the access time is significantly shortened in the second operation mode of the present invention.

In addition, the operation mode signal i! 31100 is in the second operation mode with logic "1" and the bus right response signal line 32 is output to the arithmetic processing unit 3. When the bus use right request signal line 41 or 51 is output from the input/output control device 4t or 5 first, the bus control unit 21 accepts the request signal line 41 or 51 and uses the bus that was output earlier. It resets the right response signal line 32 and notifies the arithmetic processing unit 3 that the common bus has become busy.

Further, when the arithmetic processing unit 3 is in the second operation mode and the bus right response signal line 32 is in the logic u1'' state, the bus right request signal line 31 and the bus right request signal line 41 or 51 are output simultaneously. 1 When the bus control unit 21 accepts the bus usage right request signal line 31, it resets the bus usage right response signal line 32 that was output to the arithmetic processing unit 3 and sets the busy register. As a result, the bus use request signal line 41 or 51 is not accepted until the busy register is reset. Register 200 for outputting response signal 32. Operation mode register 201
．． A register 202 for outputting the bus right response signal 32 in the first operation mode, and a register 20 for outputting the bus right response signals 42 and 52 of the input/output control device.
3 and 204. It consists of a busy register 205 and logic registers 300-313 and 400.

First, in the case of the first operation described above, since the operation mode signal 100 line is logic "0", registers 200 and 201
The output is logic u1”, bus right response signal line 32
The state of is determined by the state of register 202. For example, if the bus right request signal lines 41 and 51 are at the logic ``o'' and the bus right request signal line 31 is at the logic a1'' to control the bus right, the outputs of the bus right request signal lines 307, 308, and 309 are the logic ``u1''. , uO'' and uO''. When these are set in each register using the clock via the bus control clock line CLKI, the register 202 becomes the logical
At the same time that a signal is output to the bus right response signal line 32, the output of the bus 400 becomes logic "1".

The busy register 205 is set by the reverse lock CLK2 of the bus control clock CLKI via the logic gate 313, and the busy state is maintained. The output of the busy register 205, IJBsY, becomes logic uOpp, and signal reception on the bus right request signal line is inhibited until the busy state is released.

Therefore, the register 202 becomes logic "IO" at the next clock of the bus control clock 1cLK+, and the signal on the bus use right response signal line 32 is output for one clock period of the bus control clock line CLKI.

When the operation cycle ends, the busy reset signal line RAT
becomes logic "0", and the clock of the clock line CLK2 sets the shipping register 205 to logic "0", and the busy state is released.

Next, in the case of the second operation mode, the operation mode signal line 100
Since is the logic "'1", the output of the register 201 becomes the logic "0". Therefore, the bus right response signal line 32 is determined by the state of the register 200. Now, when the busy register 205 is reset and the signal line BSY becomes logical -, the bus right request signal lines 31, 41 and 51
If the logic is "IO", the output of the logic gate 30'6 becomes the logic "aO". The clock of the bus control clock line CLK1 sets the register 200, and the bus right response signal line 32 becomes the logic "u1". Indicates that the common bus is available. After that, when the bus right request signal line 31 becomes logic part 1'', the output of logic gate 30o becomes logic a.
□ m) Suppress the signals on the bus right request signal lines 41 and 51.

This is to give priority to the signal on the request signal line 31 when there is a conflict between the bus right request signal line 31 and the bus right request signal line 41 or 51 in the second operation mode.

Furthermore, when the output of the logic gate 3o3 becomes the logic 'Io', the output of the logic gate 306 changes to the logic η-.When each register is set by the clock of the bus control clock line CLKI, the output of the register 200 becomes the logic 1'', and the bus right response signal line 32 is reset. In addition, since the output of the register 202 becomes "logical town", the busy register 202
5 is set by the clock on the clock line CK2, and the bus control circuit becomes busy.

For controlling purposes as described above, the q-processor may use the common bus in either a first mode of operation or a second mode of operation. That is, for the arithmetic processing unit, one common bus can operate in different modes as if there were two pseudo buses. Moreover, the use of the second operation mode of the present invention has the advantage that the access time seen from the arithmetic processing unit is shortened and system performance is improved.

Effects of the Invention The present invention provides an advantageous effect by providing a signal for switching the operation mode between the arithmetic processing unit and the bus control unit in an information processing device using a common bus.

This has the effect of shortening the access time when the processing device performs a read operation to the main storage device and improving system performance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional common bus control method, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a timing chart showing the first operation mode of the common bus, and FIG. 4 is a diagram showing a common bus control method. A timing chart showing the second operation mode of the bus and FIG. 5 are diagrams showing the configuration of the bus control section of one embodiment. In Figures 1 to 5, 1...Kyoyu bus, 2.
;・Main storage device, 3...Arithmetic processing unit, 4,5・
...Input/output control device, 21... Bus control section, 31
゜41, 51... Bus usage right request signal line, 3
2,42゜52... Bus usage right response signal line, 1
00----Operation mode signal line, 200-205...
...Flip-flop, 300-313,400...
...Logic gate.

Claims (1)

[Scope of Claims] A main storage device, an arithmetic processing unit, a plurality of input/output control devices, a common bus connecting the main storage device, the arithmetic processing device, and the plurality of input/output control devices; response signal generating means for generating a response signal indicating allocation of bus usage rights in response to a bus usage rights request given from at least one of the plurality of input/output control devices and the arithmetic processing units via the common bus; a first mode signal generating means for generating a first mode signal indicating a mode in which a predetermined signal is output to the common bus in response to a signal from the response signal generating means; the plurality of input/output control devices; a second mode signal generating means indicative of a second mode for outputting the response signal to the arithmetic processing units in response to the fact that all of the arithmetic processing units do not issue a bus usage right request; 1. A bus control system comprising second mode execution means for outputting a predetermined signal to a common bus along with bus usage rights in response to the mode from the generation means.