JPH07129501A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize the suppression of the degradation of the throughput accompaing a bus right competition which becomes a problem when the memory incorporated in a microcomputer is used as a shared memory and to make the shared memory into large capacity without increasing chip area. CONSTITUTION:A microcomputer 1 provided with an internal processor 3, a RAM 4, a peripheral function module 5 and an internal bus 6 electrically connecting the internal processor 3 and the peripheral function module 5 is provided with a bus 7 for external processor for accessing to an external processor 2 and a bus switching means composed of a bus switch circuit 14 switching and connecting the RAM 4 with either one of the internal bus 6 or the bus 7 for external processor according to the access state of the RAM 4 and the access request signals from the internal processor 3 and the external processor 2, a RAM access right mediation circuit 12 and a standby signal generation circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and is particularly effective when applied to a microcomputer having a storage device accessible to an external processing device.

[0002]

2. Description of the Related Art Conventionally, in a system for realizing data transfer between a plurality of processors using a shared memory,
As a shared memory, for example, a dual port RA capable of asynchronous random access from two independent ports
M is used (FIG. 5). This dual port RA
M is used as a buffer memory between a plurality of buses of a multiprocessor system. As shown in FIG. 5, the dual port RAM 23 is constructed as a functional circuit or element independent of the processors 21 and 25. However, in a system using a microcomputer, the dual port RAM 23 can be built in the microcomputer. Has been done. FIG. 6 shows the connection relationship between a microcomputer having a built-in dual port RAM and an external processor. The microcomputer 26 includes an internal processor 27, a RAM 28, a dual port RAM 29, a peripheral function module 30, and an input / output port 33, which are connected via an internal bus 31. The dual port RAM 29 has an internal bus 3 at one port.
1 is connected to the external processor bus 32 at the other port. Access to the dual port RAM 29 from the internal processor 27 is performed using the internal bus, and the dual port R is accessed from the external processor 35.
The access to the AM 29 is performed from the external bus 34 via the input / output port 33 by using the external processor bus 32 provided in the microcomputer 26. The dual port RAM 29 is provided with an arbitration circuit that secures the bus right of the internal bus so that the internal processor 27 can access the RAM 28 or the peripheral function module 30 while accessing the external processor 35. ing.

The shared memory is described, for example, in Japanese Patent Laid-Open Nos. 62-249266 and 63-3350.

[0004]

A microcomputer having a built-in shared memory as described above is provided with a dual port function which can be accessed from two independent ports like the dual port RAM 29. Since the area of the circuit that realizes the function occupies a large proportion in the entire shared memory section, there is a drawback that the area of the chip itself increases if the capacity of the memory itself is increased. Therefore, a method of increasing the capacity of the shared memory by using a built-in RAM having only one port such as the RAM 28 as the shared memory can be considered. However, since the internal RAM has only one port, a bus right contention for the internal bus to which the port is connected occurs, and while the external processor secures the access right to the internal RAM, Since the internal processor cannot use the internal bus, it cannot access the peripheral function modules other than the built-in RAM. Therefore, there is a problem that the waiting time is significantly increased and the throughput of the entire microcomputer is deteriorated.

Therefore, the present invention realizes the suppression of the deterioration of the throughput due to the competition for the bus right, which is a problem when the memory built in the microcomputer is used as the shared memory, and the large size of the shared memory is achieved without increasing the chip area. The purpose is to increase the capacity.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a semiconductor integrated circuit including a central processing unit, a storage device, a peripheral function module, and an internal bus that electrically connects the central processing unit and the peripheral function module is accessed with an external processing device. A bus for an external processing device, a bus for the external processing device according to an access state of the storage device and a storage device access request signal from the central processing device and the external processing device. And bus switching means for switching connection with either one of them.

[0008]

According to the access state of the storage device and the storage device access request signal from the central processing unit and the external processing unit
Since the bus switching means controls the storage device to be switched and connected to either the internal bus or the bus for the external processing device, while the external processing device is using the storage device, the central processing device is the bus of the internal bus. You can secure the right to access the peripheral function module. As a result, it is possible to prevent the deterioration of the throughput due to the competition for the bus right of the internal bus, which is a problem when the built-in storage device having only one port is used as the shared memory, and the sharing is performed without increasing the chip area. It is possible to increase the capacity of the memory.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention, which is applied to a microcomputer, will be described below with reference to FIGS.

FIG. 1 is a diagram showing an overall configuration of a microcomputer and a connection relationship with an external processor (external processing device). The microcomputer 1 includes an internal processor 3 (central processing unit), a RAM 4, a peripheral function module 5, an input / output port 9, a RAM access right arbitration circuit 1
2, a bus switching circuit 14 and a standby signal generating circuit 17. The internal processor 3 is composed of a control unit and a calculation unit. The peripheral function module 5 is a ROM
(Read-only memory), a timer for generating a clock signal, an A / D converter for converting an analog signal to a digital signal, or a functional module such as a D / A converter. The internal processor 3 and the peripheral function module 5 are electrically connected by the internal bus 6. The external processor 2 and the microcomputer 1 are
It is connected through the input / output port 9 to which the external processor bus 7 is connected. The RAM 4 is configured to be switched and connected to either the internal bus 6 or the external processor bus 7 by a bus switching means composed of a RAM access right arbitration circuit 12, a bus switching circuit 14, and a standby signal generating circuit 17. is doing. Bus switching circuit 14
Is the RA from the internal processor 3 and the external processor 2.
It is controlled by the RAM access right arbitration circuit 12 which arbitrates the M access request signals 10 and 11. The standby signal generation circuit 17 generates a standby signal to the other processor when one processor has a RAM access right.

Next, the outline of the operation of the microcomputer 1 will be described.

When there is no RAM access request from the external processor 2, the bus switching circuit 14 connects the bus signal 8 of the RAM 4 to the internal bus 6 by the access right arbitration signal 13. At this time, the access right arbitration signal 13 is stored in the RAM according to the states of the access request signal 10 of the internal processor 3 and the access request signal 11 of the external processor 2.
It is generated by the access right arbitration circuit 12. In this state, the internal processor 3 operates normally.

When the external processor 2 requests access to the RAM 4, the RAM access right arbitration circuit 12 operates,
When the internal processor 3 is not accessing the RAM 4 (the access request signal 10 is in the cancel state), the access arbitration signal 13 changes and the bus switching circuit 14 causes the RAM to change.
The bus signal 8 is connected to the external processor bus 7. This enables the external processor 2 to access the RAM 4.

When the external processor 2 issues an access request for the RAM 4 while the internal processor 3 is accessing the RAM 4, the RAM access right arbitration circuit 12 holds the access right arbitration signal 13 in the access state at that time.
The bus signal 8 of the RAM remains connected to the internal bus 6 and is not connected to the external processor bus 7. At this time, the standby signal generation circuit 17 determines that the access right arbitration signal 13
Then, a standby signal 16 is generated for the external processor 2 in accordance with the states of the two access request signals 10 and 11. As a result, the external processor 2 enters the standby state.
When the internal processor 3 finishes the RAM access, the access request signal 10 is canceled, so that the standby signal generation circuit 17 operates and the standby signal 16 is canceled.
When the external processor 2 requests RAM access again in this state, the RAM access right arbitration circuit 12 and the bus switching circuit 14 operate, and the bus signal 8 of the RAM is connected to the external processor bus 7. This allows the external processor 2 to access the RAM 4. At this time, since the internal bus 6 is separated from the access of the external processor 2, the internal processor 3 can access the peripheral modules 5 other than the RAM 4 without stopping the operation. When the access to the RAM 4 from the external processor 2 is completed, the RAM access right arbitration circuit 14 operates again, the bus signal 8 of the RAM is connected to the internal bus 6, and the normal state is restored.

When the internal processor 3 issues a RAM access request while the external processor 2 is accessing the RAM 4,
Since the RAM access right arbitration circuit 12 holds the access right arbitration signal 13 in the access state at that time, RA
The M bus signal 8 remains connected to the external processor bus 7 and is not connected to the internal bus 6. At this time, from the standby signal generation circuit 17, the access right arbitration signal 13
A standby signal 15 is generated for the internal processor 3 in accordance with the states of the two access request signals 10 and 11. As a result, the internal processor 3 enters the standby state. When the external processor 2 finishes the RAM access, the access request signal 11 is canceled so that the standby signal generation circuit 17 operates and the standby signal 15 is canceled. When the internal processor 3 requests RAM access in this state, the RAM access right arbitration circuit 12 and the bus switching circuit 14 operate, and the RAM bus signal 8 is connected to the internal bus 6. This enables the internal processor 3 to access the RAM 4.

FIG. 2 is a circuit diagram of the RAM access right arbitration circuit 12. Access request signal 10 from internal processor 3 and access request signal 1 from external processor 2
1 is synchronized by the clock signal 18, and the access right arbitration signal 13 serving as an output signal is synchronized with the clock signal 19 having a non-overlapping phase with respect to the clock signal 18 and output. The arbitration operation is performed by three flip-flops and NAND gate 2 for the above synchronization.
It is realized as follows by using two units, two OR gates, and two inverters. When the internal processor 3 issues a RAM access request while the external processor 2 is accessing the RAM 4, both access request signals 10 and 11 become "1". In that case, the access right arbitration signal 13 is "1", that is, the RAM. The bus signal 8 is held in a state of being connected to the external processor bus 7. Even if the access request signal 10 becomes "0" when the access request signal 11 is "1", the access right arbitration signal 13 is held at "1". Further, even if the access request signal 11 becomes "0" (the access to the external processor 2 is completed) from that state, the access right arbitration signal 13 is held at "1". After that, when the access request signal 10 from the internal processor 3 returns to "1", the access right arbitration signal 13 becomes "0", and the RAM bus signal 8 is connected to the internal bus 6. Even if the access request signal 11 becomes "1" from that state, the access right arbitration signal 13 is held at "0". After that, the access request signal 11 becomes “0”, and the access request signal 10
The access right arbitration signal 13 is held at "0" even if "0" (the access to the internal processor 3 is completed). When the access request signal 11 eventually becomes "1", the access right arbitration signal 13 changes to "1". By performing such an operation, while one of the processors is accessing the RAM 4, the access state can be maintained without being interrupted by the access request signal of the other processor, and one processor can access the RAM 4. When the process is completed, the bus can be switched by the access request signal of the other processor.

FIG. 3 is a circuit diagram of the standby signal generating circuit 17. The circuit is composed of 1 gate each of NAND, OR, and inverter, and operates as follows. When the access right arbitration signal 13 is "1" (the RAM bus signal 8 is connected to the external processor bus 7), the RAM access request signal 11 from the external processor 2 becomes "0" (access to the RAM 4 is completed). The standby signal 15 becomes "0", and the standby state of the internal processor 3 is released. RAM from the internal processor 3 when the access right arbitration signal 13 is "0" (the bus signal 8 of the RAM is connected to the internal bus 6)
When the access request signal 10 becomes "0" (end of access to the RAM 4), the standby signal 16 becomes "0", and the standby state of the external processor 2 is released.

FIG. 4 shows a circuit diagram of the bus switching circuit 14. This circuit consists of 7 inverters and 4 AND gates.
, And four clocked inverters, depending on the states of the access right arbitration signal 13 and the read / write signal 20,
1 out of 4 clocked inverters 14a to 14d
Only one of them is in the ON state and the other three are in the OFF state, so that the bus signal 8 of the RAM is connected to either the internal bus 6 or the external processor bus 7. When the read / write signal 20 is set to "1" for reading and "0" for writing, the operation of this circuit has the following four patterns.

First, when the internal processor 3 reads data from the RAM 4, the access right arbitration signal 13 becomes "0", the read / write signal 20 becomes "1", and only the clocked inverter 14a is turned on, and the RAM is turned on.
Bus signal 8 is connected to the internal bus 6. When writing data from the internal processor 3 to the RAM 4, the access right arbitration signal 13 becomes "0", the read / write signal 20 becomes "0", and only the clocked inverter 14b is turned on.
Then, the internal bus 6 is connected to the bus signal 8 of the RAM.

Next, when the external processor 3 reads data from the RAM 4, the access right arbitration signal 13 becomes "1", the read / write signal 20 becomes "1", and only the clocked inverter 14c is turned on. RAM
Bus signal 8 is connected to the external processor bus 7.
When data is written from the external processor 3 to the RAM 4, the access right arbitration signal 13 becomes "1", the read / write signal 20 becomes "0", only the clocked inverter 14d becomes ON, and the external processor bus 7 becomes RA
M bus signal 8.

Since the external processor 2 is separated from the internal bus 6 when the external processor 2 accesses the RAM 4 by providing the bus switching circuit 14, the internal processor 3 always maintains the bus of the internal bus 6. The right can be secured.

The operation and effect of this embodiment will be described below.

(1) A microcomputer having a built-in RAM, an external processor bus independent of the internal bus,
By providing the bus switching means for switching the internal RAM to the internal bus or the bus for the external processor, the internal RAM can be used as a shared memory.

(2) Since the built-in RAM having a storage capacity larger than that of the dedicated shared memory can be used as the shared memory, the storage capacity can be increased as the shared memory without increasing the chip area.

(3) Depending on the access state of the internal RAM and the RAM access request signals from the internal processor and the external processor, the bus switching means switches the internal RAM to either the internal bus or the external processor bus for connection. Since the internal processor secures the bus right of the internal bus while the external processor uses the internal RAM, the internal processor can access the peripheral function module without causing the bus right conflict of the internal bus. it can. Therefore, it is possible to prevent the throughput from being deteriorated due to the bus right competition.

(4) A RAM access request signal from the internal processor according to the access state of the built-in RAM,
By providing an arbitration circuit that arbitrates a RAM access request signal from an external processor and generates an access right arbitration signal for connecting the internal RAM to either the internal bus or the external processor bus, Even if one of the processors is accessing the built-in RAM and the RAM access request signal is generated from the other, the one processor can continue to access the built-in RAM without interruption.

(5) By providing the bus switching circuit which operates in accordance with the access right arbitration signal generated from the RAM access right arbitration circuit, switching between the internal RAM and the internal bus or the external processor bus can be performed by an interrupt access. It can be done without interruption.

(6) Since the standby signal generating circuit is provided, the internal processor can recognize the fact by the standby signal while the external processor is accessing the RAM. can do.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the RAM built in the microcomputer is used as a shared memory between the internal processor and the external processor, but any electrically rewritable storage device may be used, such as a flash memory (electrical memory). A rewritable non-volatile memory) can be used as a shared memory as well.

A microcomputer using the present invention is
When used in a multiprocessor system, it is not necessary to provide a dedicated shared memory (dual port RAM) externally, so the area of the entire system can be reduced, and high-speed data transfer between multiple processors is possible. , Can be done efficiently.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the bus switching means switches and connects the storage device to either the internal bus or the external processing device bus depending on the access state of the storage device and the storage device access request signal from the central processing unit and the external processing unit. Thus, the central processing unit can secure the bus right of the internal bus and can access the peripheral function module while the external processing unit is using the storage device. As a result, it is possible to prevent the deterioration of the throughput due to the competition for the bus right of the internal bus, which is a problem when the built-in storage device having only one port is used as the shared memory, and the sharing is performed without increasing the chip area. It is possible to increase the capacity of the memory.

[0033]

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a microcomputer that is an embodiment of the present invention.

FIG. 2 is a circuit diagram of a RAM access right arbitration circuit provided in a microcomputer that is an embodiment of the present invention.

FIG. 3 is a circuit diagram of a standby signal generation circuit provided in a microcomputer that is an embodiment of the present invention.

FIG. 4 is a circuit diagram of a bus switching circuit provided in a microcomputer that is an embodiment of the present invention.

FIG. 5 is a diagram showing a system for realizing data transfer between two processors using a dual port RAM.

FIG. 6 is a diagram showing a connection relationship between a microcomputer including a dual port RAM and an external processor.

[Explanation of symbols]

1 ... Microcomputer, 2 ... External processor,
3 ... Internal processor, 4 ... RAM, 5 ... Peripheral function module, 6 ... Internal bus, 7 ... External processor bus, 8 ... RAM bus signal, 9 ... Input / output port,
10 ... Access request signal, 11 ... Access request signal, 12 ... RAM access right arbitration circuit, 13 ... Access right arbitration signal, 14 ... Bus switching circuit, 14a ...
14d ... Clocked inverter, 15-16 ... Standby signal, 17 ... Standby signal generating circuit, 18-19 ... Clock signal, 20 ... Read / write signal, 21 ... Processor, 22 ... External bus, 23 ...... Dual port RA
M, 24 ... External bus, 25 ... Processor, 26 ...
Microcomputer, 27 ... Internal processor, 28
...... RAM, 29 ...... Dual port RAM, 30 ......
Peripheral function module, 31 ... Internal bus, 32 ... External processor bus, 33 ... Input / output port, 34 ... External bus, 35 ... External processor,

Claims (6)

[Claims] 1. A semiconductor integrated circuit comprising a central processing unit, a storage device, a peripheral function module, and an internal bus electrically connecting the central processing unit and the peripheral function module, the external processing comprising: A bus for an external processing device for accessing the device, a storage device access port for the storage device, and a storage device access request signal from the central processing unit and the external processing device. A semiconductor integrated circuit comprising: bus switching means for switching connection with either one of the processing device buses. 2. The bus switching means is responsive to a storage device access request signal from the central processing unit and a storage device access request signal from the external processing unit according to an access state of the storage device. 2. The semiconductor device according to claim 1, further comprising an arbitration circuit for generating an access right arbitration signal for connecting the storage device to either the internal bus or the external processing device bus. Integrated circuit. 3. A bus for switching connection between the storage device and either the internal bus or the external processing device bus according to the access right arbitration signal and the read / write signal. 3. The semiconductor integrated circuit according to claim 2, further comprising a switching circuit. 4. The bus switching means is responsive to a signal generated from the arbitration circuit, a storage device access request signal from the central processing unit and a storage device access request signal from the external processing unit. 4. A standby signal generation circuit for generating a standby signal is provided to the central processing unit and the external processing unit.
The semiconductor integrated circuit described. 5. The semiconductor integrated circuit according to claim 1, wherein the memory device is electrically rewritable. 6. The semiconductor integrated circuit according to claim 1, wherein the storage device is a random access memory.