JP2718661B2 - Dual port memory controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dual-port memory control device in a system in which two data processing devices are connected via a plurality of dual-port memories. 2. Description of the Related Art Conventionally, as shown in FIG. 1, this type of device has been configured so that only one memory system of a dual port memory is interposed. [Problems to be Solved by the Invention] Therefore, when a data processing device accesses a dual-port memory, there is always a conflict with another data processing device, and the access time becomes extremely long. In addition, there is a drawback that processing when memory capacity is insufficient, such as when a dual port memory is used as a temporary storage of data from one data processing device to another data processing device, is complicated. . [Means for Solving the Problems] The present invention has been made in view of the above points, and is connected to respective buses of two data processing devices, and the two data processing devices are accessed via the respective buses. An object of the present invention is to make a part of a plurality of possible dual-port memories available as only a single data processing device as a single-port memory capable of high-speed processing without contention for memory access. A plurality of dual ports respectively connected to both the bus of the first data processing device and the bus of the second data processing device, wherein the first and second data processing devices are accessible via the respective buses. The memory and the plurality of dual-port memories may be used as dual-port memories accessible from both the first and second data processing devices, or the first data may be used. Setting means for individually setting each of the plurality of dual-port memories to be used as a single-port memory accessible only from the data processing device, and the setting means as a single-port memory of the first data processing device. Blocking means for blocking access to the dual port memory set to be used from the second data processing device. [Operation] That is, the present invention provides a plurality of dual port memories,
The bus is connected to both the bus of the first data processing device and the bus of the second data processing device, and the first and second data processing devices are configured to be accessible via the respective buses. Each of multiple dual port memory,
Whether to use as a dual port memory accessible from both the first and second data processing devices or as a single port memory accessible from only the first data processing device is determined for each of the plurality of dual port memories. The setting is performed individually, and the access from the second data processing device to the dual port memory set to be used as the single port memory of the first data processing device is prevented. As a result, the first and second data processing devices can access a plurality of dual-port memories asynchronously and in parallel, and can perform efficient data processing. As a single-port memory, only the first data processing device can access it, so that the first data processing device can use the dual-port memory as a dedicated memory without conflict with the second data processing device, The high-speed ratio of the processing of the first data processing device becomes possible. Embodiment An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is a block diagram of one embodiment of the present invention. In FIG. 2, A and B are data processing devices, each having a microprocessor 1,2 and memories 3,4. Reference numerals 9, 10 and 11 denote dual-port memories, each of which independently forms one dual-port memory block. 5 is a decoder, 6 is an address conversion device (register file) for converting a logical upper address of the data processing device A into a physical upper address, 7 is a multiplexer for branching a control signal 17 from the data processing device B to a dual port memory, 8 Is a decode / latch circuit,
The multiplexer 7 is controlled by a control signal 13 from the data processor A, decodes the data signal 14 from the processor A, latches the result, and controls the multiplexer 7. 12 is the logical upper address of the data processor A, 15 is the logical upper address 12 or the physical upper address converted by the address converter 6, 16 is a control signal to the multiplexer 7 latched by the circuit 8,
18 is a memory select signal to the dual port memories 9, 10 and 11 decoded by the decoder 5, and 19 is a control signal branched by the multiplexer 7. The address translator (register file) 6 stores the physical upper address corresponding to the logical upper address, using the logical upper address as the address of the register file as shown in FIG. 3A. When the register address of the address translator 6 is accessed by the logical upper address 12, the corresponding physical upper address stored therein is sent to the decoder 5 as an address 15. In this way, the logical upper address is converted to the physical upper address. Since the contents of the address translator 6 can be freely rewritten by the data processor A, the logical upper address can be freely assigned to the physical upper address. When rewriting the contents of the address translation device 6, the data of the physical upper address is added to the data signal 14, and as shown in FIG. Apply the switching signal. In response to the dual port switching signal, the dual port memory (such as the dual port memories 9, 10, 11 in FIG. 2) corresponding to the data of the physical upper address simultaneously placed on the other data signal lines is subjected to dual port or data processing. Make a single port from device A. For example, if the signal line on which the dual-port switching signal is placed is set to “1”, the corresponding memory becomes a dual port, and if it is set to “0”, it becomes a single port. The decode / latch circuit 8 decodes the physical upper address on the data signal line 14 and the dual port control signal, outputs a signal to the multiplexer 7 indicating which dual port memory has been set to the dual port, and outputs the signal. Latch signals until changed. According to the signal from the circuit 8, the multiplexer 7 branches the control signal 17 only to the memory set as the dual port. Therefore, the memory from which the control signal 17 is not branched automatically becomes the single port memory of the data processor A. FIGS. 4A and 4B show examples of correspondence between a logical address block (hereinafter abbreviated as LAB) and a physical address block (hereinafter abbreviated as PAB). However, the case where the number of blocks is 3 is described. PAB0 corresponds to the dual-port memory 9, PAB1 corresponds to the dual-port memory 10, and PAB2 corresponds to the dual-port memory 11. In (a), LAB0 corresponds to PAB0 and LAB1
Corresponds to PAB1, and LAB2 corresponds to PAB2. And PA
B0 is a dual port, which indicates that 9 is a dual port in the real memory. The other PAB1 and PAB2 are single ports. By rewriting the contents of the register of the address translation device 6 from this state and controlling the dual port switching signal at the same time, the setting state as shown in FIG. In this case, the contents of the register of the address translator 6 are set to LAB0 to PAB1, LAB1 to PAB2, and LAB2 to PAB0.
At the same time, the dual port switching signal is set to "0" when rewriting the address translation device 6 so that LAB0 corresponds to PAB1, and set to "1" when rewriting LAB1 to PAB2. , LAB2 is set to “0” when corresponding to PAB0. Thereby, it is possible to make only the PAB2, that is, only the dual-port memory 11 dual port. 1) In the above embodiment, the case where both the logical address block and the physical address block are three has been described, but the number of blocks may be plural. 2) In the above embodiment, the register file is used for the address translator, but the present invention is not limited to this as long as it performs the same operation. 3) The present invention is not limited to the configuration example of the above embodiment, and various modifications of the configuration are possible within the technical scope. As described above, in the present embodiment, the logical address and the physical address of the dual port unit can be freely associated with each other on a block basis, so that data transfer on the logical address can be performed without transferring data between memories. The process is very fast because it gives the same result as In addition, since the memory can be freely switched between a dual port and a single port, by making the memory a single port, the access time can be much reduced as compared with the dual port, and the processing can be speeded up. [Effects of the Invention] As described above, according to the present invention, a plurality of dual port memories are connected to the bus of the first data processing device and the second port memory.
Connected to both of the data processing device buses,
Are configured to be accessible via respective buses, so that the first and second data processors can access a plurality of dual-port memories asynchronously and in parallel,
Efficient data processing becomes possible, and furthermore, each of a plurality of dual port memories
Whether to use as a dual port memory accessible from both the first and second data processing devices or as a single port memory accessible from only the first data processing device is determined for each of the plurality of dual port memories. Since it is set individually and the access from the second data processing device to the dual port memory set to be used as the single port memory of the first data processing device is prevented, one of the plurality of dual port memories The unit can be accessed as a single port memory only from the first data processing device, so that the first data processing device can use the dual port memory as a dedicated memory without conflict with the second data processing device. It can be used, and the processing speed of the first data processing device can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a system having a conventional dual-port memory, FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. FIG. 3B is a diagram showing the contents of a data signal, and FIGS. 4A and 4B are diagrams showing the correspondence between a logical address space, a physical address space and a dual port memory. 1,2 ... microprocessor, 3,4 ... memory, 5 ... decoder, 6 ... address converter (register file), 7 ...
Multiplexer, 8 ... decode and latch circuit, 9, 10, 11
... Dual port memory, 12 ... Logical upper address of data processing device, 13 ... Control signal of data processing device,
14: data signal of the data processing device, 15: physical upper address of the data processing device, 16: multiplexer control signal, 17: control signal of the data processing device, 18: memory select signal, 19: control signal of the data processing device.

Claims (1)

(57) [Claims] A plurality of dual-port memories respectively connected to both the bus of the first data processing device and the bus of the second data processing device and accessible by the first and second data processing devices via the respective buses; Using each of the plurality of dual port memories as a dual port memory accessible from both the first and second data processing devices, or a single port memory accessible only from the first data processing device Setting means for individually setting for each of the plurality of dual-port memories; and for the dual-port memory set to be used as a single-port memory of the first data processing device by the setting means. Blocking means for blocking access from the second data processing device. Li controller. 2. 2. The dual port memory control device according to claim 1, further comprising: a conversion unit configured to convert a logical address for accessing the dual port memory from the first data processing device into a physical address of the dual port memory. A dual-port memory control device, comprising: