JPS6356573B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a storage controller that controls access to a main storage device, and particularly to a plurality of storage controllers that mutually transmit data.

Prior Art and Problems As shown in Figure 1, there are multiple storage controllers MCU, MCU0 and MCU1 in this example, and each storage controller has multiple access generators (central processing units) CPU0 and MCU1. CPU1 and CPU2
CPU3, main storage MSU0, MSU1, MSU2
and MSU3 are connected, and MCU0 and MCU1 are connected to each other to form a complex system capable of data transmission. In such a complex system
Since the CPU and MSU are only connected to each MCU (does not have an interface),
Own system (MCU and CPUs connected to it, MSU)
Access within the system is normal, but access across other systems is CPU - local MCU - other system MCU - its
He will take the MSU route. For example, CPU0
When accessing MSU2, the access is performed by the CPU.
0-MCU0-MCU1-MSU2, MSU2 is activated, and if the access is a read request, the read data is transmitted to CPU0 via the reverse path. In the case of self-system access, for example, the CPU
When CPU 2 accesses MSU 3, the access generated by CPU 2 (which is also a fetch request) is passed to MCU 1, and MCU 1 receives it.
MSU3 starts up and transfers the read data to MCU1, which transfers it to the CPU.
The procedure is to pass it on to 2.

In this way, the MCU in a complex system receives access from its own system and other systems, and the own system also receives multiple accesses.
Since there is a CPU, accesses from each of them enter,
These must be selected based on priority, MSU busy status, etc., and delivered to the relevant MSU. When considered simply, this access selection process is as shown in FIG. 2.

In Figure 2, P is a register called a port, etc.
S and RS are selectors, ADCNV is an address converter, and subscripts 0, 1, . . . are used to distinguish them from each other. Other system access For example, CPU0 is MSU2
When accessing, the access is set in the access acceptance register P1 of the CPU0 to MCU0 and selected by the access selection circuit S0. The selected access is converted by the circuit ADCNV that converts the address (real address) into a physical address, and in this example, the converted address (physical address) is in MSU2, so register P7 or It is input to the remote access selection circuit RS0 via P8, selected there and sent to port P13 of MCU1. MCU
1, the selection circuit S1 selects the access received at the port P13, the address is converted by the address conversion circuit ADCNV1 (although it simply passes through since it has already been converted), and the access is sent to the MSU2 via the port P15.

The accessed MSU2 reads the memory if the access is a fetch request, and the read data is sent to the MSU2 via MCU1 and MCU0.
Send to CPU0 (this path is not shown). Also
The MCU also includes an access pipeline to receive read data from the MSU, but is not shown here.

In the device shown in Fig. 2, the access selection circuit S0 is accessed by the CPU of its own system and by the CPU of another system.
The accesses from
At this stage, it is known whether the access is to the local MSU or the other system's MSU, and the access to the other system's
If it is an MSU, it will be sent to the other MCU.
In the case of accessing an MCU of another system, the data should be sent to the MCU of the other system before being selected by the selection circuit S0, so the method shown in FIG. 2 is wasteful.

OBJECTS OF THE INVENTION The present invention is intended to rationally perform access processing in a storage control unit MCU incorporated in a complex system and to enable efficient access selection.

Composition of the Invention The present invention provides a method for controlling a plurality of storage unit controllers in which a plurality of access generators and main storage devices are connected to each other, and which are connected to each other and perform access and data transmission/reception. An address conversion circuit that converts an access address into a physical address, and an address conversion circuit that converts an access address into a physical address, and receives an access that is determined to be an access to the own system's main memory as a result of the address conversion, and an access to the own system's main memory from another system. The present invention is characterized by comprising an address selection circuit for the own system that performs access selection based on the address conversion, and an address selection circuit for the other system that selects an access that is determined to be an access to the main memory of the other system as a result of the address conversion. Next, this will be explained with reference to examples.

Embodiment of the Invention FIG. 4 shows an embodiment of the invention, in which the same parts as in FIG. 2 are given the same reference numerals. As is clear from comparing the two, in the present invention, the address conversion circuit is
Bring ADCNV in front of address selection circuit S. Further, the address selection circuit is divided into an S for the own system MSU and an RS for the other system MSU. In the figure, the system is a combination of two systems, but of course it may be a combination of any n (n>1) systems, in which case a selection circuit for other systems (remote access selector)
If (n-1) are provided and dedicated to each system, they can be directly connected to the MCU of each system via port P7' or the like.

The address converter ADCNV converts a real address into a physical address, but a physical address is an address that indicates somewhere in the actual memory.
A real address is an address assigned during mapping, and although it is not as virtual as a logical address, it does not yet reach the level of accessing actual memory. To give a concrete example, if the main memory MSU is made up of eight memory chips each having 256 addresses, the size of the address space is 2048. Part 0
~255, 256~511, 512~765, ... as the first, second,
The memory chips 0 to 15, 16 to 31, 32 to 47, and so on may be allocated to the first, second, and so on.
3rd, 128 after allocating to the memory of...
~143, 144~159, 160~175, ... again as the first,
It is also possible to allocate it to the second, third, etc. memories, and do the same thing thereafter. In this case, addresses 0 to 2047 are real addresses, addresses on the actual memory chip,
In the latter example above, address 16 is the memory cell address in the first row and first column of the second memory, and so on are physical addresses. Address translator ADCNV performs such real-to-physical address translation. FIG. 5 shows its internal structure. It consists of registers R1 to RN and selectors Sb and Sc, and the registers R1 to RN are provided in the same number as the memory chips, and each one consists of a physical address of the memory chip and a valid bit V indicating validity of the address. CPU0,
Accesses RA0 and RA1 issued by CPU1 enter selectors Sb and Sc, and the upper bits of the accesses are
One of the corresponding registers R1 to RN is selected and the physical addresses PA0 and PA1 stored therein are read. In this example, there are two accesses input to the address converter, RA0 and RA1, so the selector is
There are two selectors, Sb and Sc, but if the number (types) of accesses input to the address converter is large, the number of selectors Sb, Sc, etc. is increased accordingly, and if it is small, the number is decreased. For example, if there is one access input to the address converter ADCNV0 as shown in FIG. 2, only one selector, Sa, is sufficient.

The operation in Figure 4 is performed using CPU0 in the same way as in Figure 2.
To explain the case where MSU2 is accessed, the access from CPU0 is from port P of MCU0.
It is set to 1' and the address is translated by ADCNV0. This address translated access is set to port P1, and this access is
Since it indicates MSU2 of the other system rather than the MSU, it is not input to the address selection circuit S0 for the own system, but is input to the other system (remote) address selection circuit RS0, where it is selected and sent through port P7'.
Sent to MCU1. Access sent to MCU1 is set to port P13, and address selection circuit S
1 is selected by MSU2 via port P15.
sent to. Once accessed, MSU2 will
If the access is a data fetch request, a memory read is performed, and the read data is transferred to MCU1,
It is sent to CPU0 via MCU0, but this route is not shown.

In the circuit shown in Figure 4, the access is address-converted and sent to the own-system address selection circuit or the other-system address selection circuit after it is determined whether it is for the own system or another system, and there, it is accessed according to the priority level, etc. There are no wasted choices because the choices are made. In Figure 2, the access is first selected, then the address is converted, and if it is determined that it is for another system, it is sent to the other system, where it is selected again.
Since the process takes a long time, there is a lot of waste, and there is a risk that the time required will be long. However, in FIG. 4, since the access input to the MCU is first input to the address converter, the number of inputs to ADCNV is large, and the number of selectors S is large.

In the embodiment, the self-system address selection circuit has two
Although this is common to all MSUs, it may be possible to have multiple numbers corresponding to individual MSUs, or if an MCU has many
When MSUs are connected, they may be divided into groups and an address selection circuit may be provided corresponding to each group.

Effects of the Invention As explained above, according to the present invention, the access selection circuit is divided into one for the own system and one for the other system, and these circuits perform access selection after address conversion, eliminating unnecessary access selection. Effective use of circuits and more efficient access processing can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of a complex system to which the present invention is applied, FIG. 2 is a block diagram showing an example of the configuration of a storage controller in the system of FIG. 1, and FIG. 3 is a part of FIG. 2. FIG. 4 is a block diagram showing an embodiment of the present invention.
FIG. 5 is a block diagram showing details of a portion of FIG. 4. In the drawing, CPU is an access generation device, MSU is a main storage device, MCU is a storage controller, ADCNV is an address translation circuit, S is an access selection circuit for the main storage of the own system, and RS is an address selection circuit for other systems.

Claims (1)

[Scope of Claims] 1. In a plurality of storage control devices each connected to a plurality of access generation devices and main storage devices and connected to each other to perform access and data transmission/reception, an access generation device of the own system occurs. An address conversion circuit that converts an access address into a physical address; and an address conversion circuit that converts an access address into a physical address; A memory comprising: a self-system address selection circuit that performs access selection based on the address conversion; and a foreign-system address selection circuit that selects an access that is determined to be an access to a main storage device of another system as a result of the address conversion. Part control device. 2. The storage unit control device according to claim 1, wherein the access selection circuit for other systems is provided as many as the number of other systems, and is dedicated to each of the other systems. 3. Claim 1, characterized in that a plurality of self-system access selection circuits are provided corresponding to individual or groups of main storage devices connected to the storage controller and are dedicated to each of them. The storage unit control device described above.