JP2555123B2 - Memory access management method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] A memory access management method, particularly a method of performing access management of a main storage device by a BUSY-FF (busy FF) system, has a simple configuration and is capable of resetting a busy of the main storage device. ,
A main memory and an access management unit that manages access requests from multiple processors to the main memory for each predetermined division unit of the main memory for the purpose of optimally performing the busy time peculiar to the access request. A main storage control unit that has an area in the access management unit corresponding to the storage area of the main storage device that is currently in a busy state with an access request permitted, and a permitted access that is provided for each division unit In a system comprising a pipeline for outputting an address signal related to a request at least by a busy time specific to the access request, and then outputting as a signal for resetting a busy-on area in the access management unit. , Provided for each pipeline, when the reset signals output from each pipeline conflict In addition, a selection circuit for selecting only the reset signal with the longer busy time in the pipeline is provided, and the address signal related to the unselected reset signal is shifted to the next stage.

[Industrial applications]

The present invention relates to a memory access management system, and more particularly to a system for performing access management of a main storage device by a BUSY-FF system.

A data processing system such as a computer system usually has a large capacity main memory. This main storage device is accessed by a plurality of processing devices (terminals) in the system. Therefore, at the same time (per machine cycle)
When there are multiple access requests, it is necessary to control contention of access requests.

[Conventional technology]

Various methods for controlling the competition of access requests have been proposed. Of these, the BUSY-FF method is one of the widely used control methods. The BUSY-FF method has a memory that manages access requests from multiple processing devices to the main memory for each division unit of the main memory, and the memory area of the main memory that is currently busy with access requests being permitted. It uses a main memory control unit that busy-on areas in the memory corresponding to. This memory is especially
It is called BUSY-FF (busy FF) and corresponds to the memory area of the main memory currently in the busy state (in use).
FF is set, and it is reset where it is not busy. When the processor requests access to the main memory, the main memory control unit refers to the busy FF and checks the busy FF corresponding to the memory of the main memory for which the access is requested. If the busy FF is set, this storage area is in a busy state and the access request is not permitted. On the other hand, if the busy FF is reset, this storage area is not in the busy state and the access request is permitted. In this case, when there are two or more access requests, the main storage control unit permits only one access request according to a predetermined priority order.

The access request has a busy time unique to the access request. Therefore, after the access request is granted and a predetermined busy time has passed, the busy FF must be reset to return the corresponding storage area of the main storage device to the usable state again. Because of this, conventional busy
The FF method uses a pipeline consisting of shift registers. When the access request is permitted, the address of the storage area of the main storage device related to this request is input to the pipeline. This address propagates through the pipeline one machine cycle per machine cycle. For example, if the busy time of an access request is 10τ (τ is one machine cycle), the address related to this access request is transferred at least 10τ in the pipeline, and then the busy FF related to this access request is reset. Is taken out from the pipeline as a reset signal for. This pipeline is provided for each division unit in response to the main storage device being managed for each predetermined division unit. For example, when the main storage device is divided into four, four pipelines are prepared.

As described above, the busy time has a value unique to the access request. For example, fetch and partial store have different busy times. Therefore, 1 at the same time
More than one reset signal may be output from one pipeline. In this case, there are a method of supplying all the two or more reset signals to the busy FF and a method of supplying only one reset signal to the busy FF. In the former method, a signal line is drawn from each stage of the pipeline and logically connected to the busy FF. The latter method draws a signal line from the stage of the pipeline corresponding to the longest busy time and connects it to the busy FF.

[Problems to be solved by the invention]

However, the conventional memory access management system has the following problems.

Busy signal lines from each stage of the pipeline
The memory access management system configured to connect to the FF has a problem that the number of signal lines becomes enormous.

In addition, the memory access management method, in which the signal line is pulled out from the stage of the pipeline corresponding to the longest busy time and connected to the busy FF, all reset signals are output according to the longest busy time. However, there is a problem that the reset state is retained and the use efficiency of the main storage device is reduced.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve the above-mentioned problems, and to perform a busy reset of a main memory device optimally with a busy time peculiar to an access request with a simple configuration.

[Means for solving problems]

 FIG. 1 is an explanatory view of the principle of the present invention.

The main storage device 10 is divided into module units (bus units) (4 divisions in the example of the figure).

The main memory control unit 20 has access management units 21 _{0 to} 21 ₃ (busy FF) that manage access requests from the plurality of processing devices 30 ₀ to 30 ₃ to the main memory device 10 for each of the division units,
Area of the storage area (e.g., Ma) region of the access management section 21 _{0-21 3} corresponding to (e.g., region Mb access management unit 21 ₀₎ of the main memory 10 of the current Bijii state access request is allowed Let's call it a busy on. The main storage control unit 20 includes a branch control unit 20 _{0-23 3} and network 23, a contention access request from the processor 30 ₀ - 30 ₃ Controls in accordance with a predetermined priority order, these main memory Logically connect with 10.

The pipeline 40 is composed of pipelines 40 ₀ to 40 ₃ provided for each division unit. Each pipeline 40 ₀ ~ 40 ₃
An address signal in accordance with the access request has been granted, at least after being delayed by a unique Bijii time the access request, Bijiion the region of the access management section 21 _{0-21 3} (e.g., the Mb) for resetting Output as a reset signal of.

Select circuits 50 ₀ to 50 ₃ are provided for each pipeline 40 ₀ to 40 ₃ , and when the reset signals output from each pipeline compete, only the reset signal with the longer busy time in the pipeline is output. select. Then, the address signal related to the unselected reset signal is shifted to the next stage.

[Action]

When the main memory control unit 20 is an access request from the processor 30 ₀ - 30 _3, it refers to the access management unit 21 _{0-21 3,}
Regions of the access management section 21 _{0-21 3} corresponding to the storage area of the main memory 10 according to the access request is checked or not or Bijiion (set state) (reset state). If Bijiion, the main storage control unit 20 does not allow an access request, if not Bijiion, to allow this request, Bijiion the area according to the access request of the access management section 21 _{0-21 3} (set state) And At this time, when access requests to the same storage area are simultaneously issued from a plurality of processing devices, the main storage control unit 20 permits only one access request according to a predetermined priority order.

For example, when the access request to the storage area Ma of the main storage device 10 is permitted, the main storage control unit 20 sends the address of the storage area Ma to the main storage device 10 and also the access management unit 21 corresponding to the storage area Ma. Area of ₀ (Busy F
F) Mb is busy on (set state). Further, the address is input into the pipeline 40 ₀ of the corresponding division unit, is shifted every 1 machine cycle (tau).

Each pipeline 40 ₀ to 40 ₃ outputs an address as a reset signal from each stage of 10τ to 12τ. Here, shifts Adosu the pipeline 40 ₀ respectively according Bijii time to an access request 10τ and 11Tau, simultaneously at a certain time, 1
Reset signal according to Bijii time access request 0τ is output from the stage of 10τ of the pipeline 40 _0, a reset signal according to Bijii time access request 11τ is output from the pipeline 40 ₀ stage. Reset signal for these conflicts are supplied to the selection circuit 50 ₀ corresponding to the pipeline 40 _0. Selection circuit 50 ₀ checks these reset signals, to select only the longer reset signal Bijii time. In the above example, pipeline 40 ₀ of 11
The reset signal output from the τ stage is selected. The selected reset signal is sent to the access management unit 21 _{0-21 3} of the main storage control unit 20 to reset the Bijiion region of the address specified by the reset signal.
On the other hand, the unselected reset signal is sent to the next stage,
Withdrawn from the pipeline 40 ₀ again at the next machine cycle, are handled similarly.

Note that it is not possible to access a bank that is already busy, but it is possible to access other banks. Therefore, the pipeline 40 ₀ There are multiple addresses, will be shifted until the timing of the reset, the reset signal is transmitted when it becomes reset timing, and resets the Bijii FF. At this time, if the reset conflicts in one pipeline 40 ₀ , the signal selected by the selection circuit 50 ₀ is transmitted, and the busy FF is reset.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram of the main part of one embodiment of the present invention. Circuit illustrated pipeline 40 ₀ in the last three stages (10
and τ~12τ), corresponding to the circuit inside the selection circuit 50 _0.

Pipeline 40 ₀ is constituted by a shift register, the shift register of each stage validity bit V, the address ADRS, the operation code (hereinafter, simply referred to as an opcode) storing OP and parity bits P. The valid bit V is "1" until the address ADRS is selected as the reset signal, and is set to "0" once it is selected. Address AD
RS corresponds to the lower the address, the main memory access managing unit 21 _{0-21 3} address of the control unit 20 of the address given in the main memory 10 from the main memory control unit 20 of FIG. 1. The opcode OP indicates the busy time of the access request. The parity bit P is information for error correction.

Decoders (DECs) 61a and 61b for decoding the operation code OP are connected to the shift registers 60a and 60b. The outputs of the decoders 61a and 61b are supplied to one inputs of the AND gates 62a and 62b, respectively. The valid bits V read from the shift registers 60a and 60b are supplied to the other inputs of the AND gates 62a and 62b, respectively. And gate 62
The outputs of a and 62b are supplied to the priority circuit 70, respectively. The valid bit V read from the shift register 60c at the final stage is directly supplied to the priority circuit.

The priority circuit 70, together with the selector 71, is the first
Constituting the selection circuit 50 ₀ as shown in FIG. The priority circuit 70 is based on the valid bit V of the decoders 61a and 61b and the shift register 60c, and the address ADRS having the longest busy time.
To determine. Then, the levels of the three reset enable signals RESET ENABLE A, RESET ENABLE B, and RESET ENABLE C are set according to the determination result. These reset enable signals are supplied to the selector 71. Also,
Reset enable signal RESET ENABLE A and RESET EN
ABLE B is respectively inverted and AND gates 63a and 63b
Is supplied to. The valid bits V read from the shift registers 60a and 60b are supplied to the other inputs of the AND gates 63a and 63b, respectively. In addition, AND gate 63a
The outputs of 63b and 63b are shift registers 60b and 60c, respectively.
Is supplied to.

 Next, the operation of this embodiment will be described.

First, the operation codes OP read from the shift registers 60a and 60b are decoded by the decoders 61a and 61b, and the respective busy times are determined. Now, assuming that the valid bit V of each of the shift registers 60a and 60b is "1", that is, the respective address ADRS is not yet selected, the outputs of the decoders 61a and 61b pass through AND gates 62a and 62b, respectively, and the priority is given. It is supplied to the circuit 70. Also, the final stage shift register 60c
The effective bit V of is output to the priority circuit 70 as it is. The priority circuit 70 is a shift register
If the valid bit V from 60c is "1", shift register 6
In order to select the address ADRS stored in 0c as the reset signal, the RESET ENABLE C signal is set to the high level and the rest is set to the low level. On the contrary, if the valid bit V from the shift register 60c is "0", that is, if the address ADRS of the shift register 60c is already selected as the reset signal, the output signals of the decoders 61a and 61b are checked.

Here, the decoder 61a connected to the shift register 60a having a delay time of 10τ has a decoded opcode OP of 1
When the busy time of 0τ or more is instructed, the access request relating to this is resettable, and a high level is output. Also, a shift register with a delay time of 11τ
When the decoded opcode OP indicates a busy time of 11τ or more, the decoder 61b connected to 60b outputs a high level because the access request related to this is resettable.

The priority circuit 70, which has received the outputs of the decoders 61a and 61b, selects the one having the longer busy time when both outputs are at the high level. That is, in order to select the address ADRS of the shift register 60b, the priority circuit 70 sets only the RESET ENABLE B signal to the high level and the rest to the low level. If only the output of any of the decoders is at the high level, the priority circuit 70 selects the address ADRS related to this.

The reset signal whose level is set in this way is sent to the selector 71, and only the address ADRS corresponding to the high level is selected. It is sent to the corresponding access management unit of the access management section 21 _{0-21 3} of the main storage control unit 20 to reset the Bijiion of area specified by the selected address ADRS. Reset enable signal from the priority circuit 70 RESET ENABLE B and RESET ENABLE C
Are respectively inverted and supplied to AND gates 63a and 63b. In this case, the address ADRS of the shift register 60a
When is selected, Since the signal becomes low level, the AND gate 63b blocks the transfer of the valid bit V of the shift register 60b. As a result, the valid bit V of the shift register 60c is set to "0". That is, it indicates that the address ADRS of the shift register 60c is newly selected. In the above case, ▲ ▼ Since the signal becomes the high level, the AND gate 63a allows the valid bit V "1" of the shift register 60a to pass as it is and transfers it to the shift register 60b.

As described above, the address ADRS of the final-stage shift register 60c is selected with the highest priority, and in other cases, the address ADRS with the longer busy time is selected, and the address ADRS that is not selected has the valid bit “1”. "Is transferred to the next stage as it is.

As described above, the busy of the main storage device can be optimally reset within the busy time unique to the access request.

The above description was an explanation of the pipeline 40 _0, but the pipeline 40 _{0-40 3} is similar.

〔The invention's effect〕

As described above, when the reset signals output from the respective pipelines compete with each other, a selection circuit that selects only the reset signal with the longer busy time in the pipeline is provided, and the reset signal that is not selected is related to the reset signal. By shifting the address signal to the next stage, with a simple configuration,
The main memory busy reset can be optimally performed with the busy time specific to the access request.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a circuit diagram of essential parts of an embodiment of the present invention. In the figure, 10 is a main storage device, 20 is a main storage control unit, 21 _{0-21 3} access management unit, 22 _{0-22 3} branch-control unit, 23 network, 30 ₀ - 30 ₃ processor # 0 # 3, 40 _{0-40 3} pipeline 50 _{0-50 3} is a selector circuit.

Claims (1)

(57) [Claims] 1. A main storage device (10), access management for managing each predetermined division unit in the main memory access requests from a plurality of processing devices (30 ₀ - 30 ₃₎ to the main memory (10) part has a (21 ₀ to 21 _3), Bijiion the region in the access management unit corresponding (21 ₀ to 21 ₃₎ in the storage area (10) of the main memory of the current Bijii state access request is allowed And a main memory control unit (20) for each division unit, and after shifting an address signal related to the permitted access request by at least a busy time unique to the access request, the access management unit ( 21 _{0-21 3)} in the pipeline (40 ₀ to 40 ₃₎ and a system having a output as a reset signal for resetting the region which is a Bijiion of, each pipeline (40 ₀ to 40 ₃₎ for each Set up Is, when the reset signal output from each pipeline conflict,
A memory characterized by providing a selection circuit (50 ₀ to 50 ₃ ) for selecting only a reset signal having a longer busy time in a pipeline and shifting an address signal related to a reset signal not selected to the next stage. Access control method.