JPS58150196A - System for updating and controlling main storage key - Google Patents

Abstract

PURPOSE:To minimize the influence of the updating of reference bits and change bits on the access of data to a main storage device, by effectively utilizing the key cue and reducing the access frequency to the key storage device. CONSTITUTION:A key cue 8 is composed of n-stages of unit memories 8-1- 8-n, and each unit memory has a unit block address, reference bit (R bit), change bit (C bit), effective bit (V bit), and key storage access request bit (RQ bit). Addresses, OPCs, and key data fed from a main storage and control part are set in a key register 9 and processed by the fetch or store or key instruction of data. An entry in the key cue 8 designated by an out cue counter 13 is read out in parallel with the processing to set the content in a key storage access register 11.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention updates a key storage device in which a storage protection key, reference bits, and change bits are stored corresponding to each unit block of a main storage device. This invention relates to a main memory key update control method.

(2) Prior art and problems In a key storage device in which a storage envelope key, reference bit, and change bit are stored corresponding to each unit block of the main storage device, when reading data (7), refer to B) 1 logic "l", change bit logic rOJ, in the case of writing (store) data, it is necessary to update both the reference bit and the change bit to logic "1". In general, there is one key on the main memory for a unit block of, for example, 2 bytes or 4 bytes, and each time a fetch or store is performed to the main memory, the key in the corresponding unit block is Reference bits and modification bits and all must be updated as above.

Data access to the key storage device is controlled in an interleaved manner, but if access to the key storage device is also controlled in the same way, the price will increase, the processing will become complicated, and the amount of data will increase. 0 For this reason, the key storage device is an element faster than the main storage device1. For example, if the main storage device is configured with MO8@RAM, the key storage device is configured with dynamics RAM, but the capacity of the main storage device When , becomes large, cost and structural problems arise.

(3) Purpose of the Invention The present invention provides that even if the main storage device and the key storage device have the same processing speed, for example, are configured with MOS/RAM, or even if the storage capacity increases, When accessing data to the device.

It is an object of the present invention to reduce the influence of updates on reference bits and changed bits. includes a main storage device, a key storage device in which a memory protection key, a reference bit, and a change bit are stored corresponding to each unit block of the main storage device, and a main storage control device that controls access to the main storage device. a storage control unit for controlling access to the key storage device; a storage control unit for controlling access to the key storage device; In a data processing device configured to issue an access request to a storage control unit and send an access request to the key storage control unit when the processing device accesses the key storage device,
An operating code section, an address section, a key data section, a key register in which a key storage access request sent from a request source is set, and a unit block address and a reference bit in each stage. The key/key of the station in which the change bit, valid bit, and key storage access request bit are written, the contents of the above key/key, and the above key e.
Comparison means for comparing with the contents of the register, data input stage specifying means for specifying the above-mentioned key/stage weight - 0 stage weight to be input into the data storage, and data specifying the stage of the above-mentioned key fist cue to be outputted from the data meeting. Output stage designation means and operation
a key storage access register having a code section, an address section, and a key data section and in which an access request to be sent to the key storage device is set; means for detecting all empty spaces in the key queue; It is characterized by a control means for performing control and a pipe provided in all the above key storage control sections.

(5) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 1 is a diagram showing the system configuration of a data processing unit 1ifi7& This is a diagram showing details of the system.

#I1 In the diagram, 1 is the main storage device, 2tj key storage device, 3 is the main memory control unit, 4 is the key storage control unit, 5IIi
A central processing unit group, 6, represents a channel processing unit. The key storage device 12 stores storage protection keys, reference bits, and change bits corresponding to each unit block of the main storage device l. The main memory controller 3 controls access to the main memory IK, and the key memory controller 4 controls access to the key memory 2. The main memory control unit 3 is the main memory 11
Every time mIK is accessed, a key storage access request is issued to the key storage control unit 4, and when the processing units of the central processing unit group 5 or the channel embedding device group 6 access the key storage device 2t, the key storage control unit 4 is accessed. It is configured to issue a request. When the central processing unit group 5 or the channel processing unit group 6 first accesses a unit block in the main memory device 1, it issues a command to I8 to retrieve the corresponding entry in the key storage device 112, and then accesses the unit block by itself. Find out if you are eligible for access. A block diagram of the key storage control section 4 is shown in FIG. In Figure 2, 7 is the in-key counter, 8 is the key key-19 is the key register, and 10 is the comparison group %.
11 is a key storage access register, 12 is a #-1t selector, 13 is a comparison circuit, and 14 is a control circuit 1.

The key key 8 consists of a unit memory 8-1 to 8-bit of a calculation unit, and each unit memory 8-1 to 8-bit is a unit block--address, reference bit (R bit), change bit (C bit), and valid bit. bit (v bit) key storage access request bit) (Contains RQC bit. Comparison (b) Short answer 10 contains unit memories 8-1 to 8 of keys 1-8, respectively.・Ki-
- Counter 7 specifies the unit memory of key -8 to be input during the data session, so when the address of key register 9 and the data of RC are registered in key -8, the counter +1 count. Specifies the primary unit memory that has been uploaded. Register 9 is the request source, for example central tin salt equipment group 5.
or channel processing value m group 6, or a key storage access request sent from the main memory system [3].
f! 1I9-1, address section 9-2 and key data @
9-31 has an operating code (OPC).
) is a code that specifies f-1 (D7 Etch/Store, key command), the address is a unit block address, and the key data is the key write data when the key command is executed.Key memory access・Register 11 is a key *Similar to register 9, the operation code (O
P C) 1fBll -1 door)"xl$11-
2 and key data 1ls11-3. The output terminals of the key register 9 are the 020 section 11-1 and the address section 11-1 of the corresponding key storage access register 11, respectively.
2 and the input terminal of the key data section 11-3, and the output terminal of OPC@9-1 is connected to the comparison (b) input terminal.
The output terminal of the address section 9-2 is also connected to the address/data input terminal of the key Φ key nose-8 and the input terminal of the comparator circuit group 1O. key cue 8
The readout terminals of the address bits of the unit memories 8-1 to 8-1 are respectively connected to the input terminals of the corresponding comparison circuits 1O-1 to 10-s and the corresponding input terminals of the selector 12, The terminals are connected to the input terminals of the corresponding comparator circuits 10-1 to 10-s and the key terminals, respectively.
Connected to the input terminal of the data section 11-3, V, RQ
The C bit read terminal is connected to the corresponding comparator circuit 1O-.
1 to 10-s input terminals.

The output of the comparison circuit group IO is supplied to a control circuit 14 which performs all controls according to the contents of the comparison results. The output terminal of the out queue counter 13 is connected to the select terminal of the selector 12 and 0.
The 0-out fist counter 3 connected to the input terminal of the PC1fB11-1 is a key storage access register 9.
If the contents of the key storage access register IK unit memory 8-1 to 8-% are set, the keys set to -8 specify the unit memory 8-1 to 8-%. The corresponding RQC bit is set to logic "0", and then the out Φ key-e counter 3 is counted up by +1. The output terminal of the selector 12 is connected to the input terminal of the address register 1-2. The output of key storage access register 1 is provided to the key storage device. The input terminal of the comparison circuit 13 is supplied with the contents of the in-key counter 7 and the contents of the out-key fist counter 3.
If it matches by counting up the counter 3, the out key 1-counter 3 matches and the unit memory 8-1 to 8-uta of the key key and -8 matches. It is determined that all are vacant. The control circuit 14 receives input from various parts within the device, and! ! The main memory key update control system of the present invention, which is configured as described above and is executed by the friend key storage control section, will be explained below.

Address sent from main memory control ff1s3, opc.

Key data is set in key register 9.

The data is processed as follows depending on whether it is an 7-etch, a store, or a key command.

■ In the case of 7-etch data, the entry data of the unit memories 8-1 to 8s are read out, and among these entry data, those whose V bit is logic "1" and the contents of the key register 9 are compared to the comparator circuit 10.
−1 to 10 s.

If address-a is displayed, the key update is terminated,
Key register 9/l'i becomes a trap capable of accepting the next request.

If there is an address mismatch and the key key 8 is not full, the address and the RC bit of rlOJ are written to the unit memory specified by the in-queue Φ counter 7, and the V bit and RQ bit are set to logic "L". , increment the in-work key counter by 7 +1. Key register 9 is then enabled to accept the next request.

If there is a mismatch, and if keys K and -8 are full, wait until keys K and -8 become free.

In this case, the key storage controller becomes busy 11 and the key register 9 cannot accept the next request.

■ In the case of data storage, the entry data of unit memories 8-1 to 8-1 are read out, and the V bit of these entry data is
1” and the contents of the key register 9 are compared to the comparison circuit group 10.
-1 to 10%.

If the RC bit of the address-at indicating friend entry data is rlOJ and the key key &-8 is not full, the V bit of the corresponding entry data is set to logic "o", and the RQ bit is also set to Logic "0" K. Next, in
Key - Write address of key register 9 to unit memory specified by counter 7, RCC pit rllJ
Finally, set the counter to 7t+1.

When such processing is completed, the key register 9 can accept all subsequent requests.

If the RC bit of the address matching control data is rlOJ and the key Φ key 8 is full, wait until there is space in the key key &-8.

In this case, the key storage controller becomes busy and the key register 9 cannot accept the next request.

If the RC bit of the data indicating the address is rllJ, the key update is completed, and the next request can be accepted in the key register 9.

If the address does not match and the key -8 is not full, write the address and all RC bits of rlIJ to the unit memory specified by the counter 7, and set the V bit to logic "1" KL. , the RQ bit is also logic “1”
”. In this case, the key-register 9 will be able to accept all subsequent requests.

If the addresses do not match and the key register -8 is full, wait until the key e-queue 8 becomes free. cannot accept the request.

■ In the case of a key command The key command is a % friend queen key setting command (88K) that sets the first operand's internal column to the main memory key of the block specified by the second operand.

Main memory key insertion instruction (ISK) specified by the second operand and inserted into the next block's main memory key 1-first operand
% and the second operand address, there is an instruction such as a reference bit reset instruction (RRB) that resets the reference bit tube included in the main memory key of the friend block. ○ Unit memory 8-1 to 8-% entry. The data is read, and these entry data and the contents of the key register are compared. If so, it is considered a match.

If there is a match, wait until there is a mismatch. In this case, the key storage controller is busy and the key register 9 cannot accept the next request t-.

If there is a mismatch, the contents of key register 9 are set in key storage access register 11.

Activates the operation on the key register [2. The key register 9 is then ready to accept the next request.

The above is in parallel with ■ or ■ operating procedure.

If the key key 8 is not empty and there is no mismatch in the case of a key command, the entry in the key key 8 specified by the out key counter 13 is read, and the key memory access is - The contents of the entry in register IIK are set.

■If the bit is logic “1”, the key storage device [2 internal RC
Bitu's brand new sophisticated operating system is launched. When an entry in key queue 8 is read and the contents of that entry are set in key storage access register 11, the RQ bit of the corresponding entry in key queue 8 is set to "0". , then out key, - counter 1
3t+1.

The control system of the key storage control unit is shown in more detail in FIG. 3 below. 21 to 41 are and gates, sha to 46 are not gates, 47 to edicts are or gates, words to 57 are flips, 7 stomachs, edicts to i) are decoder tubes, ◎Kitame-yen entry. R bit (reference bit) of 1 is RtbC bit (change bit) t
The ict-V bit (valid bit) is indicated by Vs, and the RQC bit (key storage access request bit) is indicated by RQt. An entry in the key is synonymous with a unit memory in the key &-8. l added to the symbol...
The rice cake is key, so there is an endrido in the middle...% and 4 in the song part (
1<4<饅) corresponds to entry 1 in the key. Namely, in the and gate.

For example, 29-- corresponds to the entry in the key range of the AND gate reviews, and for example, R4m C
4* Vi+ RQ4 is 'tz P3! The bits corresponding to R bit, C bit, V bit, and RQC bit correspond to bit 4.

Figure w43 (a) shows a busy signal generation circuit for the key register 9 and key storage access register 11. When a key memory access request (same as a key operation request) arrives from the main memory control s3, central processing unit it5, etc., the 7 lip and 70 knob 8 are set in the reset state, and the key becomes logic "1". A write register busy signal is output. As shown in the figure, the reset conditions for the flip/70-turn condition are that a match signal with an entry in which the data fetch is To and the V bit is logic "1" is logic "1", and the data fetch is "1". The key registration signal is logic rlJ, and the matching signal with the entry in the data store where the data store is active and the V bit is logic rlJ is logic "1".
9 and the matching entry's R bit) and C bit are both logic "1", and the match signal with the entry in the data store where To is present and the V bit is logic "1" is logic "1".
and the key entry signal is logic rlJ, or it is a key command and both the V bit and RQC bit are logic "rlJ".
The mismatch signal with the entry "1" is logic "1" and the key storage access register busy signal is logic "r".
Since it is OJ, the set output of the 60 clip flops becomes the key register busy signal. AND gate n has a key command, and a mismatch signal with an entry with logic "1" for both the V bit and RQC bit is logic "1".
”, and the key storage access register e-busy signal is logic “0”? If the condition is positive output is logic “1”
”, and the negative output becomes logic “0”.

The output of AND gate 4 becomes logic "1" provided that the key-empty signal is logic "0" and the negative output of AND gate 27 is logic "1". The positive output of AND gate n and that output of AND gate are input to OR gate 48.

Also, the output signal of AND gate 28 becomes a key read signal. The group of seven rip-flops is set when the output of the OR gate is a logic rlJ, and reset when the key storage access signal is a logic "1".

Its set output becomes the key storage access-register busy signal. The decoder group checks whether the operation code set in the 020 section 9-1 of the key register 9 is a data fetch, a data store, or a key command.

FIG. 3(b) is a diagram showing a circuit for determining whether the entry data and the contents of the key register 9 match or do not match.

Comparing circuits 10-1 to 10-s check the entry in the key whose address t matches the address in the address field 9-2 of the key Φ register 9, and from among the entries whose addresses match, the V bit is set to logic "1". Select from 29-1 to 29-%, and from among the entries with matching addresses, both the V bit and the RQC bit are logical "1".
Select with . AND GATE 29-1 to 29-s
The output of the AND gate is input to the OR gate 49, and the output of the AND gate (+1 or 5) is input to the OR gate group. Next, the lower circuit in FIG. 3(b) will be explained. If the address currently written to the entry lc in the key register matches the address of the key register 9, and the R bit and C bit of the entry l are both logic "1", the gate blade -1 becomes the logic "1". '', and when the R bit is logic rlJ and the C bit is logic rOJ, the AND gate 34-1 outputs the logic rlJ output. The same goes for entries in other queues.60 AND gate 33-1
The outputs of the AND gates 34-1 and 34-1 are input to the OR gate 51, and the outputs of the AND gates 34-1 and 34-1 are input to the OR gate 52.

FIG. 3 e1 is a diagram showing the key registration signal generating circuit.

The output of the AND gate word is data 7-etch, ■ The mismatch signal with the entry of logic rlJ is logic "l", and the full signal is logic "o".
The logic becomes ``1'' on the condition that it appears. The output of the AND gate is a store, the %V bit is a logic 'l' entry and the mismatch signal is a logic 'l', and the Kijima-@full signal is a logic 'o'. If all the conditions are set, the logic becomes "1" K. The output of AND gate 37 is a data store, and the V bit is a logic "1".
”, the matching signal with the entry “1” is logic “1”, −
The R bit of the scattered binary is logic “1” and the C bit is logic “1”.
If all conditions are for the output to be 0, the logic becomes 1.

The output of AND gate easy or 37 is OR gate 53
is input. The output of the Or Gate group becomes the cue sickle signal.

Figure 3) shows the in-key counter and its related circuits, and the out-key counter and its related circuits (b).
A diagram showing the pipes. The contents of the counter 7 are decoded by the decoder 59.

Assume now that the fourth output signal of decoder 59 is logic "1". At this time, the KIE upgrade signal is logic “1”
Then, the AND gate (2) outputs all logic "1", and this signal sets the V bit and RQC bit of the entry in the key to logic "1". Also, the key 2 registration signal becomes logic "1". When this happens, the contents of the in-key counter 7 are incremented by +1.

The contents of the input counter 7 become the key 1 write address. The contents of the out-key counter 13 are deconidized by the decoder ω. Assuming that the first output signal of the decoder ω is logic "1", when the key readout signal becomes logic "1", the AND gate 3
9-4 outputs logic ``111rl'', and this signal causes the 8Q bit of entry 1 in the key to become logic ``0''. Further, when the key output signal becomes logic "1", the contents of the out-fist key counter 13 are incremented by one. out·
The contents of the key counter 13 become the key read address.

#! Figure 3 shows the V-bit reset signal generation circuit. The output of the AND gate 41 is a data store, the V bit matches the logic rlJ entry, the signal is a logic "l", and the key crystal full signal is a logic "0". , the R bit of the matching entry is logical rl
In J, the C bit becomes logic "1" on the condition that it is cleared by logic "o". Under the condition in which the AND gate 41 outputs a logic "1", for example, when the match signal 1 becomes a logic "1", the AND gate 40-4 outputs all logic "1",
This signal causes the V bit of entry 1 in the key to be a logic "0".

FIG. 3 shows a configuration for storing V bits and RQ bits. 7 lip/70 tube 56-4
9 is used to store all the V bits of the entries in the key, and 57-i is used to store all the RQ bits of the entries in the queue.

(6) Effects of the invention As is clear from the above explanation, if the present invention is used, medium-
Since the Φ keys are effectively utilized, the number of accesses to the key storage device can be reduced, and the influence of updates of the axis reference bits and change bits on data access to the main storage device can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the system configuration of a data processing device applied to the present invention, FIG. FIG. 3 is a diagram showing a detailed tube of one embodiment. l...Main storage device, 2...Key storage device, 3...
Main memory control unit, 4...Key storage control unit, 5...; Central escape device group, 6... Channel processing device group, 7... In-key counter, 8... Key・Ki 1-9...
Key register, 10...Comparison (b) brief explanation, 11.
...Key storage access register, 12...Selector, 13...Comparison circuit, 14...Control circuit,
21 to 41...and fight gate, heart to 46.
...not gate, 47 or edict...or gate% word or 57...flip flop, cabinet or ω
···decoder. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Kyotani Yobe■ 1 Figure C2 3 Figure (A) Y3 Page (C) Z3 Figure (E)

Claims (1)

[Claims] a main storage device; a key storage device in which a memory retention key, a reference bit, and a change bit are stored corresponding to each unit block of the main storage device; and an access t to the main storage device;
A main memory control unit that controls iIlI, a key memory control unit that controls access to the key storage device, and a plurality of @embedded types, each time the main memory control device accesses the main memory device, the key storage control unit A storage access fee is issued to the key storage control section, and when the processing device accesses the key storage device, the key storage control i! In a data processing device configured to issue an ISK access request,
A key register that has an operating code section, an address section, and a key data section, and in which a key storage access request sent from a request source is set, and a unit block address and a reference bit in each stage. The key of the Kamo stage where the change bit, valid bit, and key storage access request bit are written, the contents of the above-mentioned key, and the above-mentioned key.
Comparison means that performs all comparisons with the contents of the register, data input stage designation means that specifies the stage height of the above-mentioned keys for inputting data, and data input stage designation means that specifies the stage height of the above-mentioned keys for data output. Specify the data output stage specification method, operation
a key storage access register having a code section, an address section, and a key data section and in which an access request to be sent to the key storage device is set; means for detecting an empty state of the key; A main memory key update control method characterized in that control means for performing various control pipes are installed in the key memory control unit.