JPS62296263A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To avoid each processor from waiting for data transfer by allowing each processor to always and exclusively use one out of two or more memories selected according to the same address. CONSTITUTION:In accordance with the states of switching circuits 3 and 5, a master processor 1 is connected to a memory 4 or 6. A slave processor 2 is connected to the memory 6 or 4, whereby each processor can use the memory exclusively without fail. As for data transfer, the master processor 1, for instance, transfers data to the memory 6. Upon the completion of the data transfer, the switching circuit 3 is switched. The master processor 1 transfers data to the memory 6, and the slave processor 2 reads data out of the memory 4. Upon the completion of the data reading, the salve processor 2 switches the switching circuit 5, and reads data in the memory 6. By repeating such actions, data transfer can continue.

Description

3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a data transfer circuit between processors, particularly to a data transfer circuit with short latency.

Conventional technology FIG. 4 shows an example of the configuration of a conventional data transfer circuit.

Data transfer from the master processor 7 to the slave processor 8 was performed by writing the data of the master processor 7 to the memory 9 using the access control circuit 1o, and reading the data from the memory 9 by the slave processor 8.

Problems to be Solved by the Invention In such conventional methods, while one processor is writing to or reading from memory, that processor has exclusive access to the memory, and other processors have exclusive access to the memory. Writing to and reading from memory is prohibited until it is released, reducing data transfer speed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a data transfer circuit that reduces the waiting states of other processors that occur due to monopolization of memory by one processor.

Means for Solving the Problems In order to solve the above problems, the present invention provides a plurality of processors, the same number of memory circuits as the processors that can be written and read by the same address, and the processors and the A data transfer circuit is provided which is constituted by the same number of switching circuits as the processors, which switches the connection of bus lines so that the memory and the circuit are connected in a one-to-one relationship.

Operation According to the above-described configuration of the present invention, each processor can always exclusively use one of two or more memories selected by the same address, and there is no need for a processor to wait for data transfer.

Embodiment FIG. 1 is a block diagram showing an embodiment of a data transfer circuit of the present invention. In FIG. 1, reference numeral 1 denotes a master processor, which is connected to a bus line 11. As shown in FIG. 2 is a slave processor connected to the bus line 21;

Reference numeral 3 denotes a switching circuit which connects either one of the bus line 31 connected to the bus line 11 and the bus line 32 connected to the bus line 21 to the bus line 33. 4 is memory. The switching circuit 6 is connected to the bus line 51 . One of the bus lines 52 connected to the bus line 21 is connected to the bus line 63. 6 is a memory. bus line 33
is connected to the memory 4 and the memory 6 via the bus line 41, and the bus line 63 is connected to the memory 6 via the bus line 61, respectively.

FIGS. 2 and 3 show the connection state of the switching circuit. The state of the switching circuit takes either the state shown in FIG. 2 or FIG. 3. The master pro-sensor 1 is connected to the memory 4 in FIG. 2, and to the memory 6 in FIG. The slave processor 2 is connected to the memory 6 in FIG. 2, and to the memory 4 in FIG. 3, so that each processor can exclusively use the memory circuit at all times. For example, in the state shown in FIG. 2, data is transferred from the master processor 1 to the memory 4, and upon completion of the transmission, the switching circuit is switched to the state shown in FIG. 3. In the state shown in FIG. 3, the master processor 1 transfers data to the memory 6, and the slave processor reads data from the memory 4. When the data reading is completed, the slave processor 2 switches the entire switching circuit to the state shown in FIG. 2 and reads the data from the memory 6. By repeating this operation, data transfer is continued.

Effects of the Invention As described above, according to the present invention, data can be transferred between processors without waiting during data transfer, and extremely high performance can be provided in terms of processing speed. It is something.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transfer circuit according to an embodiment of the present invention, FIGS. 2 and 3 are state diagrams of the switching circuit of the present invention, and FIG. 4 is a block diagram of a conventional data transfer circuit. . 7.1...Mask processor, 2,8...
...Slave processor, 3...Switching circuit, 4
...Memory, 5...Switching circuit, 9,
6...Memory, 11゜21.31.32,3
3, 41.51.52゜53.61...Bus line, 10...Access control circuit. ◇(r＋
gradient
”）

Claims (1)

[Claims] the plurality of processors, the same number of memory circuits as the processors capable of writing and reading selected by the same address, and switching the connection of the bus line so as to connect the processors and the memory circuits in a one-to-one relationship; A data transfer circuit consisting of the same number of switching circuits as processors.