JP2579008B2 - Time-division multitasking execution device - Google Patents

Description

The present invention relates to a central processing unit (hereinafter referred to as a CPU).
The present invention relates to a time-division multitasking execution device capable of performing time-division parallel processing of two or more tasks (jobs) and processing one interrupt or exception arbitrarily selected at high speed. .

2. Description of the Related Art When a task is executed using a microprocessor, a set of register files including a group of registers, a stack pointer, a status register, and the like is prepared for one CPU, and a register is prepared according to an instruction from the CPU. There are many systems that execute a task while transferring necessary data to a file. However, in this method, only one task can be executed at any time, so that the execution efficiency is deteriorated. Therefore, conventionally, a method of executing a plurality of tasks in a time-division manner using a set of register files provided for one CPU in a time-division manner has been considered. Among them, the most typical one is a method of switching tasks for each instruction of the CPU. However, with this method, every time you switch tasks,
The data previously stored in the register file is
It is necessary to temporarily save the data in the memory (stack) area and call the data necessary for the next task from another memory space or the like into the register file. During the data switching time, the task cannot be executed, so that the time loss increases.

In order to solve such problems, prepare multiple register files for one CPU, switch multiplexers according to CPU instructions, and execute multiple tasks in a time-division manner while sequentially switching multiple register files Methods are also being considered. In this way, since one register file is prepared for one task, there is no need to save or recall data at the time of switching, so that time loss is reduced.

Problems to be Solved by the Invention However, in the above-described conventional multitask execution device, only the task that performs system management can rewrite the scheduler. Specifically, when a task other than the system management task issues a new task, the execution of the system management task is interrupted first. Then, the task for system management registers a new task in the scheduler, and resumes the process before the interruption. Therefore, it is necessary to save and restore data including a program counter and the like necessary to execute a task for performing system management.

Generally, exception processing such as interrupt processing is performed by a task for performing system management. For this purpose, data including a program counter and the like necessary to execute the task for performing system management must be saved and restored. did not become.

The present invention provides a time-division multitask execution device that solves such a conventional problem.

Means for Solving the Problems To achieve this object, a time-division multitask execution device of the present invention includes two sets of queue switching scheduling registers for a plurality of task execution queues each executing a plurality of tasks. A single CPU is occupied by multiple task execution queues in a time-sharing manner under the control of a common control register group, queue switching control unit, and occupation processing specification register that specifies interrupts and exceptions for high-speed processing, and multiple tasks The configuration is such that a task execution queue that performs time-division parallel processing and receives only one arbitrary interrupt or exception is provided.

Operation As described above, by providing a rewritable scheduling register from a task other than the system management task, a task other than the system management task can issue a new task.

Further, by providing the occupation processing designation register, the interruption designated by this register can be processed only by switching the register file.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic configuration of an embodiment of the present invention. The time-division multitasking execution device of this embodiment is realized by one microprocessor, and eight task execution queues (hereinafter simply referred to as queues) 0 to 7 are provided for one CPU (not shown). . Each of the queues 0 to 7 includes a register file 8 including a register group, a data register, an address pointer, and the like, and executes a task while referring to data and addresses stored in each of the register files 8. In order to control the execution order of these queues 0 to 7, a control register group 9 common to all the queues 0 to 7, which are write-accessible from the queue 0, and a queue switching control unit 13 are provided. I have. That is, the plurality of queues 0 to 7 occupy one CPU in a time-sharing manner under the control of the control register group 9 and the queue switching control unit 13, and perform time-sharing parallel processing of up to eight tasks.

The control register group 9 includes an occupation processing designation register 10 for setting an interrupt or an exception to be occupied for one of the queues 0 to 7 (queue 1 in the following description).
And queue switching scheduling registers 11 and 12 for designating the execution order of queues 0-7. Here, the queue switching scheduling register 12 can be write-accessed from the queue 1 as well. The program counter 14 receives an address from a register in the register file 8 of each of the queues 0 to 7, and indicates the address of the currently executed instruction or the instruction following the next instruction. ROM15 contains
A so-called object code is stored, and sequentially executes instructions according to the address from the program counter 14. The RAM 16 sequentially reads and writes various data generated with the execution of the instruction. The arrow line and the center line 17 shown between the blocks are bus lines for data or address.

FIG. 2 shows a queue switching scheduling register 11.
FIG. 3 shows the configuration of the queue switching scheduling register 12. As shown in FIG. Each bit of the queue switching scheduling registers 11 and 12 is
The queue is selected when the bit is 1, and is not selected when the bit is 0. The difference between the queue switching scheduling registers 11 and 12 is that the queue switching scheduling register 11 is write accessible only from queue 0, whereas the queue switching scheduling register 12 is write accessible from queues 0 and 1. That is, the queue in which the logical sum of the bits in which 1 of the two queue switching scheduling registers 11 and 12 is set is executed. In other words, since the entire system executes tasks scheduled in at least one of the scheduling registers, the queue 1 can practically only issue a new task. Can be executed. in this way,
By providing the queue 1 other than the queue 0 that performs system management with a function of registering a task in the scheduling register, it is not necessary to interrupt the processing of the queue 0. In the present embodiment, the case where the number of the scheduling registers 12 as the second scheduling register is one has been described, but a plurality of scheduling registers 12 may be provided. In this case, the processing speed of the entire system can be improved.

FIG. 4 shows the configuration of the occupation processing designation register 10. Each bit corresponds to interrupt factors 1 to 6 and exception factors 1 and 2. The queue 1 is exclusively allocated to the interrupt factor or the exception factor in which 1 is set, and when the above factor occurs, the queue 1 is activated and processed.

FIG. 5 is a diagram showing that queues 2, 3, and 7 are selected by the setting of the queue switching register 11, and three tasks are processed in a time-division parallel manner. By setting 1 to bits 2, 3, and 7 of the queue switching register 11 shown in FIG.
3,7 is automatically switched.

FIG. 7 is a diagram showing processing when an interrupt / exception cause set by the occupation processing designation register 10 occurs. In the time-sharing parallel processing setting of the first queue, queues 2 and 3 are selected as indicated by the queue switching scheduling register 11 in FIG. Also, as shown in FIG. 8, the occupation processing designation register 10 has the bit 6 corresponding to the interrupt factor 2 set to 1. On the other hand, the queue switching scheduling register until the interrupt factor 2 occurs
The contents of 12 are all 0s. When the queues 2 and 3 shown in FIG. 7 are executed, an interrupt cause 2 is generated. In order to perform the interrupt processing, the queue 1 is activated because the interrupt cause is specified by the occupation processing specification register 10, and the sequence is started. a is started. Since the queue 1 is set to exclusively process the interrupt factor 2, the tasks other than the interrupt factor 2 are not executed. Therefore, it is not necessary to save the data of the register file corresponding to the queue 1 to the stack, and no overhead is caused by the stack saving. Further, even when the interrupt processing is completed, there is no data to be returned from the stack, so that there is no overhead due to the return from the stack. In order to allocate the task generated by the interrupt in the sequence a of the queue 1 to the queue 6, the queue switching scheduling register shown in FIG.
As shown at 12, 1 is set to the bit 6 corresponding to the queue 6. The queue switching control unit 13 determines the contents of the two sets of queue switching scheduling registers 11 and 12, and selects the queues 2 and 3 selected by the queue switching scheduling register 11 and the queue switching scheduling register 1
After the sequence a is completed, a total of three queues including the queues 6 selected in 2 are executed in a time-division parallel manner.

FIG. 9 shows interrupts / exceptions other than interrupt factor 2 in the settings of the queue switching scheduling register 11 and the occupation process designating register 10 in FIG. 8 (interrupt factor 5 in this case).
FIG. 9 is a diagram illustrating a process when the error occurs. When an interrupt / exception other than the cause set in the occupation processing specification register 10 occurs, activation is applied to a queue other than the queue 1 (here, the queue 0). At this time, since another task is being executed in queue 0, the contents of the register file in queue 0 are saved to the stack in sequence b, and overhead is caused by saving from the stack. Also, as shown by the sequence d, the contents of the queue 0 are returned from the stack, so that an overhead due to the stack return occurs.

In this way, the user can determine the task execution specification only by setting necessary information in the registers in the control-like register group according to the user's specification. Also,
It is possible to provide a system with high real-time performance for a factor that requires a high-speed interrupt / exception response. Therefore, even if the user does not have sufficient knowledge of the program, the desired specification can be set only by setting information of 1 or 0 on a register, so-called hardware, so that the multitask execution specification and the real-time processing specification can be set. The burden on the user when setting is greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a time-division multitask execution device according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration of a queue switching scheduling register 11, and FIG. FIG. 4 is a diagram showing the configuration of the occupation processing designation register, FIG. 5 is a diagram showing the operation when the queues 2, 3, and 7 are automatically switched, and FIG. 6 is a register of the operation of FIG. FIG. 7 shows an example of setting of the interrupt and the interrupt set by the occupation processing designation register.
FIG. 8 is a diagram showing an operation when an exception factor occurs, FIG. 8 is a diagram showing an example of register setting in the operation of FIG. 7, and FIG. 9 is a diagram showing interrupt / exception factors other than those set by the occupation process designation register. FIG. 9 is a diagram illustrating an operation when the error occurs. 0 to 7 task execution queue, 8 register file, 9 control register group, 10 occupation process designation register, 11 queue switching scheduling register, 12 queue switching scheduling register
13: Queue switching control unit, 14: Program counter, 15: ROM, 16: RAM, 17: Bus line.

Claims (1)

(57) [Claims] 1. A time-division multitasking execution device for executing a plurality of tasks in a time-division manner, wherein a first scheduling register rewritable from a task for performing system management and a rewritable from a task other than the task for performing system management are provided. A time-division multitasking execution device, comprising: a second scheduling register; and executing a task scheduled in at least one of the first scheduling register and the second scheduling register.