JPH02242434A - Task scheduling method - Google Patents

Abstract

PURPOSE:To efficiently allocate a processor on a task in a multiprocessor consisting of the processors with different instruction sets by providing a flag representing the kind of the processor capable of executing the task at each task. CONSTITUTION:The processors 1011 and 1012 are the processors of type 0 having the same instruction sets, and the processor 1013 is the processor of type 1 having another instruction set, and the type of the processor can be shown by processor kind identifiers 1021-1023. Feasible/infeasible flags 1071-1073 are provided at unprocessed tasks 1061-1063 in a queue stored in a main memory 104, and the flag at respective bit position corresponds to the kind of the proces sor. The task can be executed by the processor of corresponding kind when the flag is set at 1, and no task can be executed when it is set at 0. Thereby, it is possible to efficiently allocate the processor on the task with the multiprocessor including the processors with different instruction sets.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for scheduling tasks in a multiprocessor, and particularly to a method for scheduling tasks in a multiprocessor including processors with different configurations.

[Conventional technology]

Conventional multiprocessors were often conditioned on the condition that a plurality of processors constituting the multiprocessor had exactly the same configuration, and therefore had the same instruction cell 1.

Furthermore, in the case of a multiprocessor or multicomputer in which processors with different configurations and therefore different instruction sets are connected, each processor has a queue in which tasks to be processed are placed. It was necessary for the processor to decide on which processor the task should be executed, and to place the task in the queue of the decided processor.

Further, Japanese Patent Laid-Open No. 62-208157 describes a program execution method for a computer system consisting of a plurality of computers having partially different instruction sets, although it is not a scheduling method. In this method, the compiler outputs object code that can be executed on any computer. That is, a compiler analyzes a program and divides it into parts that can be executed by common instructions between processors and parts that cannot. A single object code is output for parts that can be executed in common, but multiple object codes corresponding to the type of processor are output for parts that cannot be executed. Then, the compiler inserts a program for branching to the object code corresponding to the type of processor being executed immediately before the unexecutable portion.

[Problem to be solved by the invention]

The conventional task scheduling method for multiprocessors or the program compilation method for multiprocessors described above has the following problems.

In other words, when configuring a multiprocessor using only processors with the same configuration, when adding a processor with an enhanced function, such as a processor equipped with a vector processor or a processor for AI processing, to the system, only one processor is required. You can only replace one processor and have to make all processors the same.

With the method of having a queue for each processor, when there are multiple processors with the same configuration, there is a possibility that the load will be uneven among the processors.

The method in which the compiler outputs multiple object codes has the disadvantage that the object code becomes large.
The disadvantage is that a new compiler must be created.

An object of the present invention is to provide a task scheduling method for efficiently allocating processors to tasks on a multiprocessor in which part or all of the instruction set consists of different processors, without creating a compiler that outputs multiple object codes. Our goal is to provide the following.

Another object of the present invention is to provide a multiprocessor in which a certain process includes a fast processor and a slow processor, such as a processor with a vector processor and a processor without a vector processor, in which a task with such a process is performed by the fast processor. The object of the present invention is to provide a method for scheduling tasks that can be assigned preferentially to tasks.

Another object of the present invention is to preferentially allocate a task including a certain process to a processor that is fast;
To provide a task scheduling method that prevents a task including a certain process from being assigned to a processor incapable of the process.

[Means to solve the problem]

The above objective is achieved by providing each task with a flag indicating the type of processor on which it can run, and giving each task a priority that indicates the priority of each type of processor according to the speed at which it can process the task. This is achieved by providing a table, and by providing a disable value for the priority and making it impossible for a processor of the specified type to process the task.

[For production]

The flags provided for each task consist of as many flags (1 bit) as there are types of processors included in the system. Each flag corresponds to each type of processor and indicates whether the task can be executed by that type of processor. Tasks that are ready to be executed are placed in a queue that can be accessed by any processor. Each processor that performs idle processor scheduling sequentially checks the flags of tasks starting from the head of its queue, and if it finds a task that can be executed by its own processor, it picks it up and executes it. This prevents load sharing between processors of the same type.

Furthermore, the priority information table provided for each task is an integer array of the size of the number of types of processors included in the system. Each array element corresponds to each type of processor and indicates the priority that the task has with respect to that type of processor.A processor that can execute the task at high speed is given a high priority. When the priority is set to the lowest level, it means that the task cannot be executed by that type of processor. When each task with the above table is ready to execute,
It is connected to a queue that can be accessed by any processor. Each processor that has become idle or that performs scheduling looks at the tasks in its queue, selects and executes the task that can be executed by its own processor and has the highest priority.

This method makes it possible to efficiently allocate processors to tasks using multiple processors, including processors with different instruction sets and processors that are particularly fast at certain processes.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows one embodiment of the present invention, in which processors 1011-1013 can all access main memory 104 through shared bus 103. FIG.

Of these, processors 1.03.1.10F and 2 are type 0 processors with the same instruction set, processor]
013 is a type 1 processor with a different instruction set. The type of this processor is indicated by processor type identifiers 1021 to 1023.

Unprocessed tasks 1061 to 106 are stored in the main memory 104.
3 queues are stored. This queue is formed by connecting each task with pointers 1561 and 1562 that each task has. Header 10 is at the beginning of the queue
It is 5. Tasks 1064-1066 are currently being executed on processors 1011-1013. Tasks 1061 to 1063 in the queue have executable flags 1071 to 1063.
1073 are provided, and the flag at each bit position corresponds to the processor type. And the flag is ``]ノ'
When , the task can be executed by the corresponding type of processor, and when it is 00'', it cannot be executed.For example, the executable flag 1071 indicates whether task 061 is type 2 or type 1.
This indicates that it can be executed on a type 0 processor, but cannot be executed on a type 0 processor.

FIG. 2 shows the contents of the processor type identifiers 1021 to 1023, which consist of 3 bits, of which only 1 bit is 1".
21-1023 are executable flags 1071-J073
By calculating the logical sum of products, it is possible to check whether the task can be executed by that type of processor.

FIG. 3 shows a flowchart of a scheduler program (hereinafter simply referred to as a scheduler). This scheduler is provided in each of the processors 1011 to 1013, and is activated when the task being executed by the processor ends and when a timer interrupt for scheduling occurs.

Timer interrupts enter each processor at regular time intervals.

Assuming that a timer interrupt occurs in the processor 1011 and the scheduler is activated, first, in step 201, an identifier 1021 indicating the type of the own processor is read. The read value is "100". Next step 202
The task 1061 pointed to by the header 105 of the queue is seen.

In step 203, it is checked whether there are any tasks in the queue, and if there are no unprocessed tasks, step 2 of idle processing
Move to 04. In FIG. 1, there is a task 1061, so in step 205, the logical sum of products S of the task executable flag and the processor type identifier is calculated. This is done by ANDing each bit of both and ORing the results. If the AND of any bits becomes 111 II, this indicates that the task can be executed by the processor. In this case, the executable flag 1071 is "110"
", and the processor type identifier 1021 is "001
”, therefore, the AND for each bit is all “0”, so it is S-O, which means that the processor 1011 cannot execute the task 1061.Then, the process advances to step 207 and looks at the next task in the queue.Continuing steps In step 203, it is checked whether there is any task, and when task 1062 is found, in step 205, the logical sum of products S of the executable flag 1072 and the processor type identifier 1021 is calculated.
Since “O1” and “OO1”, the AND of each bit is “OI”.
I II O"1", and the or is II 111
This means that it is possible to implement it. So step 208
removes task 1062 from the queue. The task being executed by processor 1011 at this time (interrupted by a timer interrupt) is connected to the rear end of the queue in step 209. The exit of tasks from these queues is done by changing pointers.

Task 1 is then removed from the queue in step 209.
Execute 062.

FIG. 4 is a time chart showing an example of task execution by each processor. In the figure, processor 10
The time chart of processing by 11 to 1013 is PO to P
2, the scheduler program is operated by timer interrupts 301 to 309 and task termination 350, and tasks 360 to 370 are executed on each processor. That is, initially processor 1
011 to 1013 are task T3. T4. T5
Suppose you are running When timer interrupt 301 occurs in processor 1011, task T1 is scheduled for this processor as explained in FIG. Next, a timer interrupt 304 enters the processor 1012 and the task T
2 is executed and a timer interrupt 30 is sent to the processor 10]3.
7 is entered and task TO is executed. Processor 101
2, task T3 is executed again due to termination 350 of task T2 that was being executed. Processing continues in the same manner.

FIG. 5 shows a task table for implementing tasks 1061 to 1066 in FIG. 1. The task identifier 150 is a serial number attached to a task, and is used to identify the task when sending a signal to the task. The task state 151 represents the current state of the task, and includes the following states.

User Running: A state where the user program of the task is running on the processor.

Kernel Running...Make a system call while a user program is running on the processor,
A state in which a system program is being executed due to an interrupt.

Ready to Run: The task is ready to be executed, but no processor has been assigned yet. Tasks are queued.

5leep: Waiting for a certain event to occur, such as waiting for Ilo's response.

Priority 152 is a numerical value representing the priority at which a task is executed; the larger this numerical value is, the earlier the task is executed by the processor.

The queue of tasks waiting to be assigned a processor is sorted in descending order of priority.

The execution possibility flag 107 is the flag 1071 to 1 in FIG.
It is the same as 073 and was provided for realizing the present invention. This contains information about what type of processor can execute the task. The signal field 153 indicates interruption and termination of tasks between tasks.

This field contains signals that send information such as errors. The timer 108 is a field in which time information such as task execution time and system execution time is entered. The region table 154 contains a pointer pointing to a page table of a region in which programs and data used in a task are stored, and information about the size of the region. The register save area 155 is an area for saving register information of the task before the task is interrupted when the task is interrupted by a timer interrupt. When a suspended task is resumed by a schedule,
The task is restarted based on the information in the registers saved here. Pointer 156.1.57 is a pointer used to connect the task described in FIG. 1 to a queue.

In the embodiment shown in FIG. 1 described above, the scheduler program is provided in each processor, and each processor performs its own scheduling.
This can also be scheduled on the least loaded processor. FIG. 6 shows such an embodiment. This configuration is almost the same as the configuration shown in FIG. 1, but the difference is that a table 110 storing the types of processors in the system is stored in the main memory. When starting up the system, each processor reads out its own processor type identifiers 1021 to 1023 and writes them into the table 110, thereby allowing the scheduler 109 to identify the type of processor that is currently being scheduled.

FIG. 7 is a flowchart of the scheduler program in this embodiment, which is executed by any processor with a low load when a timer interrupt for scheduling occurs. In the state shown in FIG. 6, that is, when a timer interrupt occurs in the processor 10]2 and the scheduler program is executed, first, in step 701, the header 1 of the queue is
．． [Task pointed to by 05] Look at 061. In step 702, a check is made to see if there are any tasks in this visible area. If there are no unprocessed tasks, the scheduler program ends without doing anything, but now that there is task 1061, the process proceeds to step 703. In step 703, among the processors that are executable according to the task executable flag (
Check this using table 110 in main memory 104)
, if there is an idle processor, select that processor; if not, check the processing time of the task currently being processed using the timer 108 in FIG. 5, and select the processor with the longest time. In Figure 6, the executable flag is “1]0”
Therefore, the types of processors that can be executed are type 1 and type 2. This applies to processor 1.013t
, so this processor is selected here. In step 704, the task being executed by the selected processor is interrupted and its state is saved. Since task T5 was being executed on the selected processor 1o13,
This task is interrupted, and the contents of the register at the time of interruption are stored in the register save area 15 in the task table of task T5.
Evacuate to 5. In step 705, the interrupted task T
Queue 5. They are inserted in the order of priority 152 written in the task table. Finally, the task 1061 selected in step 706
(T6) is taken out of the queue and executed on the selected processor 1.013.

FIG. 8 is a time chart showing an example of task execution by each processor. Processor 1011
A time chart of the processing in ~1013 is shown as PO~P2, and the end of the scheduler program S 330
~332, execution tasks are switched by context switches 340-342.

Initially, it is assumed that the processors 1011 to 1013 are respectively executing task T3, scheduler program S, and task T5. As explained using FIG. 7, the scheduler S interrupts the task T5 being executed by the processor 2013 using the context switch 342, and causes the task TO to be executed. When the scheduler S terminates, the processor 1012 executes the previously executed task T.
Return to execution of step 4. After a certain period of time has elapsed, a timer interrupt 310 is generated again, and the scheduler S is executed. This scheduler takes out task T1 of FIG. 6 from the queue.

Since the executable flag 1072 of task T1 is "001", it can be executed by a type O processor. These are processors 1011 and 1.012, but since both processors are currently executing a task, the processor with the longer execution time of the currently executing task is selected.

In FIG. 8, assuming that processor 1011 is longer,
This processor 1011 executes task TI. Similarly, the scheduler is executed in one of the processors by a timer interrupt at fixed time intervals, and the tasks in the queue are scheduled.

FIG. 9 is a diagram showing another embodiment of the present invention.

In this embodiment, the processors 1011 to 1013 have different configurations and partially different instruction sets, as indicated by their identifiers 1021 to 1023. Tasks 1061 to 1061 queued in the main memory 104
1063 each includes a table 10 that stores what priority each type of processor has for tasks.
81 to 1083 are provided. The first row of table 1081 indicates that a type 0 processor with processor type identifier 001 has a priority of 0 for task 1061, i.e., a type 0 processor has
Indicates that this task cannot be performed. The following line represents that a processor of type ]- has a priority of 10, and a processor of type 2 has a priority of 20.

FIG. 10 is a flowchart of the scheduler program used in the embodiment of FIG. Similar to the scheduler program shown in FIG. 3, this schedule program is executed when the task being executed ends and when a timer interrupt for scheduling occurs. Timer interrupts enter each processor at regular time intervals. 9th
A case will be described in which a timer interrupt is generated in the processor 1013 in the state shown in the figure, and the scheduler program is executed. First, in step 1001, the processor type identifier 1021 of its own processor is read. The read value is 01
It is 0. Next, in step 1002, the Helada 10 in the queue is
Checking whether a task is connected to 5. If no task is connected, this indicates that there is no task to be processed, so the idle processing 1003 is performed. Here, since task 1061 is connected, the process advances to Yes and in step 1004, the task with the highest priority corresponding to the processor type identifier is selected from among the tasks connected to the queue. In Figure 9, tasks 1061 to 10
63 are connected to the queue, and the priorities corresponding to the processor type identifier 010 are 10.0.20, respectively. Therefore, task 1063 with priority 20 is selected. Since the priority of the selected task is not 0,
Proceed from step 1005 to step 1006 (if 1
If the priority of the selected task is O, this means that there is no task that can be executed by the type of the current processor, so idle processing 1003 is performed). Step 1006
Now remove task 1063 from the queue. That is, pointer 1562 is eliminated. Finally, in step to 07, task 1063 is executed.

FIG. 1j shows a task table 106 for implementing each task in FIG. 9. What is different from the table in FIG. 5 is that the executable flag 107 in FIG. 5 is removed.
Priority 152 in Figure 5 is priority 1 for each processor type.
It is the same except that it is now 58.

The feasibility of executing a task for each type of processor, which was expressed by the execution capability flag, is expressed by whether the priority level 158 is 0 or not.

FIG. 12 is a diagram showing another embodiment of the present invention.

In the embodiment shown in FIG. 9, each processor has a scheduler program and schedules its own processor, but in this embodiment, the table 110 storing the types of processors is stored in the main memo January 04. Using this, one of the processors performs the necessary scheduling at that time. Therefore, when starting up the system, each processor enters its own processor type identifier 1021 to 102.
3 is read out and written in table 110.

FIG. 13 shows a flowchart of the scheduler in this embodiment. The scheduler program is executed on any processor with a low load when a timer interrupt for scheduling occurs.

Therefore, as shown in FIG. 12, a timer interrupt is generated in the processor 1011, and the scheduler program 1
The case where 09 is executed will be explained. First, step 13
At 0I, we look at the task 1061 pointed to by queue header 1.05. In step 1302, it is checked whether there are any tasks, and if there are no unprocessed tasks, the scheduler program ends without doing anything. Here, since there is a task 1061, the process advances to step 13o3, looks at the priority table 1081 of the task 106I, and selects the processor type with the highest priority.

Here, processor type identifier 100 with priority 20
(Type 2) processor is selected. Step 13
Table 1 shows the selected processor types in 04.
10, it is found that processor 1012 is that type of processor. Here, only one processor of that type is selected, but if there are multiple processors, the processor that takes the longest to execute the task currently being executed by that processor is selected. In step 1305, the task being executed by the selected processor is interrupted and its state is saved. The selected processor 1012 performs task T
4 is being executed, this task is interrupted, and the contents of the register at the time of interruption are saved in the register save area 155 (FIG. 11) of the task table of task 1065 (T4). In step 1306, the interrupted task T4 is placed at the end of the queue. Finally step 1307
The task 1061 selected in is taken out from the queue and executed by the selected processor 1012.

FIG. 14 is a diagram showing another embodiment of the present invention.

In this embodiment, three processors 1011 to 1013 are connected to a network 300, and each processor has a local memory 3.
101 to 3103. Figure 1, Figure 6, Figure 9
In the embodiments shown in FIGS. 10 and 12, the queue is stored in the main memory 104 that can be accessed by all processors, but in this embodiment, the queue is stored in the local memory 3101 of the processor 1011 that is the master. There is.

When a processor other than processor 1011 needs to access the queue for scheduling, it accesses local memory 3101 through network 300 and processor 101. whether it is practicable or not;
The priority-based scheduling method is the same as in the previously described embodiments.

FIG. 15 is a diagram showing another embodiment of the present invention.

This embodiment is a modification of the embodiment shown in FIG. 14, in which there is no master processor and the same queue is stored in all local memories. That is, in the headers 1051 to 1053 of each local memory 3101 to 3103,
Identical tasks 1061 and 1062 are connected, and each processor schedules tasks by looking at its own local memory queue. The queue is updated in its own local memory after obtaining permission from all other processors, and a message is sent to the network 300 instructing other processors to update their local memory as well.
Broadcast on.

FIG. 16 is a diagram showing another embodiment of the present invention.
This configuration is such that each of the local memories 3101 to 3103 in the embodiment shown in FIG. 5 is accessed as one virtual shared memory 320. Any local memory can be accessed from any processor, and the queue used for scheduling is also stored in this virtual shared memory.

FIG. 17 shows an example of mapping of logical addresses and physical addresses of the virtual shared memory 320. Each address area of the logical address space 500 of the virtual shared memory corresponds to the physical address spaces 5101 to 5 of the local memories 3101 to 3103.
103. An address conversion table for making this association is shown in FIG. 8. For example, suppose that a certain processor accesses a page having a logical address O. If the processor number IDO of this page is the number of the own processor, the page is read from the page of physical address 0 in the own local memory. If the processor numbers are different, the accessed processor is number 1 IDO
sends a message through network 300 to transfer the page at physical address 0 to the processor with physical address 0. The processor that receives the message converts the requested page into a message and sends it to the requester. In this embodiment as well, the control based on whether or not each task can be executed or the priority level is the same as in the previous embodiment.

〔Effect of the invention〕

According to the present invention, when there is a multiprocessor consisting of processors with different architectures and partly different instruction sets, the user does not need to be aware of which processor executes a task, which greatly improves task management efficiency. improves.

Further, according to the present invention, scheduling is provided that allocates an optimal processor depending on the processing content of a task in a multiprocessor including processors that have a common instruction set but are enhanced with certain types of processing such as vector processors. system throughput is improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the correspondence between the types of processors constituting the system and processor type identifiers, and FIG. 3 is a flowchart of the scheduler used in the embodiment of FIG. 1. , FIG. 4 is a time chart showing an example of the operation of the embodiment shown in FIG. 1, FIG. 5 is a diagram showing an example of the configuration of a task table in the embodiment shown in FIGS. The figure is a diagram showing another embodiment of the present invention, a flowchart of the scheduler used, and a time chart showing an example of operation. FIG. 9, FIG. 1(), and FIG. 11 are diagrams showing another embodiment of the present invention. , a flowchart of the scheduler used and a diagram showing an example of the configuration of a task table, 12th and 13th are diagrams showing another embodiment of the present invention and a flowchart of the scheduler used, 14th
15 and 15 are diagrams showing an embodiment of the present invention in a system in which each processor has a local memory and are connected via a network, and FIG. 16 shows an example in which the local memory of each processor is accessed as one virtual memory. FIG. 1 shows an embodiment of the present invention in a system configured to
FIG. 7 and FIG. 18 are explanatory diagrams of the correspondence between the logical space and physical space in the embodiment of FIG. 1b, and an explanatory diagram of an address translation table for making the correspondence between the two spaces. 10] 1-10] 3-...puo Sera+j, 1021~
1023-Processor type identifier, 1o; 3... Shared bus, 104... Main memory, 105... Header, 1061-1o66... Task, 1071-107
3... Executable flag, 1081-1o83... Priority table, ], 09... Scheduler program, 110... Processor type identifier table, 3101-3
1o3...Local memory, 3zO...Virtual shared memory. Representative Patent Attorney Masami Akimoto [n]] Figure 1G] 3 Figure Figure Figure Figure

Claims (1)

[Claims] 1. A method for scheduling tasks in a multiprocessor system in which a plurality of processors, all of which do not have the same configuration, and a main memory accessible by each of the processors are connected via a shared bus. It has a scheduling means for its own processor and a means for recognizing an identifier indicating the type of its own processor, stores a queue of unprocessed tasks in the main memory, and indicates for each task the type of processor that can execute the task. A task table including executable flags is provided, and when scheduling is required for any processor, the scheduling means of the processor sequentially reads out the tasks connected to the queue of the main memory and executes the tasks of the own processor. A task scheduling method characterized in that the first task determined to be executable based on a comparison between an identifier and the executable flag of the read task is set as an execution task. 2. A method for scheduling tasks in a multiprocessor system in which a plurality of processors, not all of which have the same configuration, and a main memory that can be accessed by each of the processors are connected via a shared bus, in which some of the processors have scheduling means. Finally, a queue of unprocessed tasks and an identifier table indicating the type of each processor are stored in the main memory, and each task is provided with a task table including an executable flag indicating the type of processor that can execute the task. At the same time, when scheduling is required for any of the processors, if one of the processors having the scheduling means is processing a task, it interrupts the task processing, starts the scheduling means, and fills the queue in the main memory. The tasks connected to the above are sequentially read out, and the first task determined to be executable is set as the execution task by comparing the executable flag of the read task with the identifier read from the identifier table of the processor that requires the scheduling. A task scheduling method characterized by: 3. In a task scheduling method in a multiprocessor system in which a plurality of processors, all of which do not have the same configuration, and a main memory accessible by each processor are connected via a shared bus, each processor is provided with its own scheduling means. a recognition means for an identifier indicating the type of the own processor, a queue of unprocessed tasks is stored in the main memory, and each task is given a priority for each processor type in executing the own task. In addition to providing a task table including a priority table, when scheduling is required for any processor, the scheduling means of that processor sequentially reads out the tasks connected to the queue of the main memory and schedules the tasks of its own processor. 1. A task scheduling method comprising: selecting a task with the highest priority for an identifier by referring to the priority table for each task; and setting the selected task as an execution task. 4. A method for scheduling tasks in a multiprocessor system in which a plurality of processors, not all of which have the same configuration, and a main memory accessible by each of the processors are connected via a shared bus, in which some of the processors have scheduling means. A queue of unprocessed tasks and an identifier table indicating the type of each processor are stored in the main memory, and each task has a priority table indicating the priority of each processor type in executing its own task. and when scheduling is required for any of the processors, if one of the processors having the scheduling means is currently processing a task, the processing is interrupted and the scheduling means is activated; The tasks connected to the queue in the main memory are sequentially read out, the task with the highest priority for the identifier of the processor that requires scheduling is selected by referring to the priority table for each task, and the selected task is A task scheduling method characterized in that an execution task is: 5. The task according to claim 3 or 4, characterized in that the priority level is provided with a disable value indicating that the task cannot be executed, and the task is not assigned to a type of processor for which the disable value is specified for a certain task. scheduling method. 6. In place of the main memory, a local memory is provided corresponding to each processor, and in place of the shared bus, a network is provided that connects each processor, and the queue is connected to one processor designated as the master. 6. The task scheduling method according to claim 1, wherein the task is stored in a local memory, and the queue is accessed from other processors via the network. 7. In place of the main memory, a local memory is provided corresponding to each processor, in place of the shared bus, a network is provided to connect the processors, and the queue is stored in the local memory corresponding to all the processors. 6. The task scheduling method according to claim 1, 2, 3, 4, or 5, wherein updating of the queue is performed in all local memories via the network. 8. A local memory is provided for each processor in place of the main memory, a network is provided to connect each processor in place of the shared bus, and the physical space addresses of all local memories are changed to logical space addresses. Claim 1, 2, 3, 4 or 5, characterized in that a single virtual memory is formed by providing each processor with an address translation means for making the correspondence, and the virtual memory is used as a shared memory of each processor. How to schedule the tasks described.