JPH02242434A - Task scheduling method - Google Patents

Task scheduling method

Info

Publication number
JPH02242434A
JPH02242434A JP6221689A JP6221689A JPH02242434A JP H02242434 A JPH02242434 A JP H02242434A JP 6221689 A JP6221689 A JP 6221689A JP 6221689 A JP6221689 A JP 6221689A JP H02242434 A JPH02242434 A JP H02242434A
Authority
JP
Japan
Prior art keywords
processor
task
processors
kind
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6221689A
Inventor
Tadashi Kamiwaki
Yoshiki Kobayashi
Tomoaki Nakamura
Masahiko Saito
Shinichiro Yamaguchi
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6221689A priority Critical patent/JPH02242434A/en
Priority claimed from DE4007998A external-priority patent/DE4007998A1/en
Publication of JPH02242434A publication Critical patent/JPH02242434A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To efficiently allocate a processor on a task in a multiprocessor consisting of the processors with different instruction sets by providing a flag representing the kind of the processor capable of executing the task at each task.
CONSTITUTION: The processors 1011 and 1012 are the processors of type 0 having the same instruction sets, and the processor 1013 is the processor of type 1 having another instruction set, and the type of the processor can be shown by processor kind identifiers 1021-1023. Feasible/infeasible flags 1071-1073 are provided at unprocessed tasks 1061-1063 in a queue stored in a main memory 104, and the flag at respective bit position corresponds to the kind of the proces sor. The task can be executed by the processor of corresponding kind when the flag is set at 1, and no task can be executed when it is set at 0. Thereby, it is possible to efficiently allocate the processor on the task with the multiprocessor including the processors with different instruction sets.
COPYRIGHT: (C)1990,JPO&Japio
JP6221689A 1989-03-16 1989-03-16 Task scheduling method Pending JPH02242434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6221689A JPH02242434A (en) 1989-03-16 1989-03-16 Task scheduling method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6221689A JPH02242434A (en) 1989-03-16 1989-03-16 Task scheduling method
DE4007998A DE4007998A1 (en) 1989-03-13 1990-03-13 Process planning method for multiple computer system - using process control table from which computer are selected for each process

Publications (1)

Publication Number Publication Date
JPH02242434A true JPH02242434A (en) 1990-09-26

Family

ID=13193733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6221689A Pending JPH02242434A (en) 1989-03-16 1989-03-16 Task scheduling method

Country Status (1)

Country Link
JP (1) JPH02242434A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05216844A (en) * 1991-07-17 1993-08-27 Internatl Business Mach Corp <Ibm> Method for improved task distribution in multiprocessor data processing system and method for the same
WO2007020739A1 (en) * 2005-08-15 2007-02-22 Sony Computer Entertainment Inc. Scheduling method, and scheduling device
JP2007257280A (en) * 2006-03-23 2007-10-04 Yokogawa Electric Corp Distributed processing system and distributed processing method
US7356666B2 (en) 2003-06-27 2008-04-08 Kabushiki Kaisha Toshiba Local memory management system with plural processors
US20110161975A1 (en) * 2009-12-30 2011-06-30 Ibm Corporation Reducing cross queue synchronization on systems with low memory latency across distributed processing nodes
JP2012252413A (en) * 2011-05-31 2012-12-20 Toshiba Corp Information processing apparatus, information processing method, and control program
US9038079B2 (en) 2009-12-30 2015-05-19 International Business Machines Corporation Reducing cross queue synchronization on systems with low memory latency across distributed processing nodes

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05216844A (en) * 1991-07-17 1993-08-27 Internatl Business Mach Corp <Ibm> Method for improved task distribution in multiprocessor data processing system and method for the same
US7356666B2 (en) 2003-06-27 2008-04-08 Kabushiki Kaisha Toshiba Local memory management system with plural processors
US7739457B2 (en) 2003-06-27 2010-06-15 Kabushiki Kaisha Toshiba Local memory management system with plural processors
WO2007020739A1 (en) * 2005-08-15 2007-02-22 Sony Computer Entertainment Inc. Scheduling method, and scheduling device
JP2007052511A (en) * 2005-08-15 2007-03-01 Sony Computer Entertainment Inc Scheduling method and scheduling device
US8375390B2 (en) 2005-08-15 2013-02-12 Sony Computer Entertainment Inc. Scheduling method and scheduling apparatus
JP2007257280A (en) * 2006-03-23 2007-10-04 Yokogawa Electric Corp Distributed processing system and distributed processing method
US20110161975A1 (en) * 2009-12-30 2011-06-30 Ibm Corporation Reducing cross queue synchronization on systems with low memory latency across distributed processing nodes
US8819690B2 (en) * 2009-12-30 2014-08-26 International Business Machines Corporation System for reducing data transfer latency to a global queue by generating bit mask to identify selected processing nodes/units in multi-node data processing system
US9038079B2 (en) 2009-12-30 2015-05-19 International Business Machines Corporation Reducing cross queue synchronization on systems with low memory latency across distributed processing nodes
JP2012252413A (en) * 2011-05-31 2012-12-20 Toshiba Corp Information processing apparatus, information processing method, and control program

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