JP3546694B2 - Multi-thread computer system and multi-thread execution control method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a parallel computer system, and more particularly, to a multi-thread computer system for efficiently scheduling a plurality of threads on a shared memory multiprocessor computer without passing through an operating system.
[0002]
[Prior art]
There is a multi-processor computer system having a plurality of processor elements in one system in order to obtain higher processing performance. Among such computer systems, a system in which each processor element shares a main memory is called a shared memory multiprocessor computer system, which has an advantage that a program can be easily described as compared with a distributed memory system. .
[0003]
On the other hand, on the software side, there is a parallel execution method called multi-thread execution in which one process is divided into control flows called threads and a plurality of threads are executed in parallel. On a multiprocessor computer system, processing performance is improved by allocating a plurality of threads to a plurality of processor elements and executing them simultaneously.
[0004]
The management of threads in a multiprocessor computer system is usually performed by a multiprocessor operating system. That is, when creating a new thread, synchronizing with another thread, or deleting a thread, the thread calls a service of the operating system.
[0005]
Thread preemption is also performed through the operating system. Preemption is a process of interrupting the execution of a thread that has occupied the processor for a long time and switching to the execution of another thread. A computer system having a preemption function has a hardware timer device and a mechanism for transmitting an interrupt signal from the timer device to a processor when a predetermined time has elapsed. When a certain time has elapsed since the start of the execution of the user program, the control is transferred to the operating system by a timer interrupt, and the operating system switches the execution thread.
[0006]
In order to efficiently execute a plurality of threads on a multiprocessor computer system, it is important to reduce thread management overhead such as thread generation, synchronization, switching, and deletion.
[0007]
In the Sun Microsystems Solaris operating system, threads can be managed by a user-level library instead of the operating system. This allows for thread management with lower overhead, but in the case of preemption the operating system intervenes (Introduction to Multithread Programming, ASCII Publishing, September 1996, p69-p70 and p76-p77).
[0008]
The preemption processing circuit described in JP-A-5-158900 accepts preemption not by an operating system but by dedicated hardware, but the switching process after the acceptance is performed by a normal interrupt to the operating system. I do.
[0009]
On the other hand, when reading / writing a computer resource shared by a plurality of threads, for example, a shared variable in a main memory, it is possible to prevent a plurality of threads from accessing the computer resource at the same time to obtain an erroneous processing result. For this purpose, it is necessary to perform a process called exclusive control (exclusive control is described in, for example, AS Tanenbaum, “Basics and Application of OS”, Prentice Hall Toppan, Chapter 2, Section 2.2, etc.) Has been).
[0010]
Exclusive control is usually realized by a processor instruction for exclusive control such as test and set or exchange. These instructions inseparably test the value of a certain memory cell in the main memory and set a new value to that memory cell. For example, the test and set instruction performs the following three operations without interruption or division by another processor.
(1) Reading the value of a certain memory cell in the main memory to a computer register
(2) Writing value 1 to the memory cell
(3) Comparison between the value read into the computer register and the value 0
[0011]
In a shared memory multiprocessor computer system, since exclusive control is performed between different processors, these exclusive control instructions act on a shared main memory. That is, access to the main storage memory is required for exclusive control itself.
[0012]
[Problems to be solved by the invention]
A first problem of the prior art is that a sufficiently high-speed interrupt response process cannot be performed due to multi-thread execution, and a thread switching overhead is large. This is because, since the interrupt processing is processed in the operating system, a context switch from the user program to the operating system occurs.
[0013]
The second problem is that an access to the main memory occurs due to the exclusive control processing itself, and the overhead of exclusive control and synchronization processing between threads, which is indispensable for multi-thread processing, is large. Since the processing speed of recent processors is much faster than the access speed of the main memory, many processors have a high-speed, small-capacity memory called a cache memory between the processor and the main memory. To avoid processing delays due to memory access. However, since the exclusive control instruction always accesses the main storage memory, the processing speed is reduced.
[0014]
All of the above-mentioned problems cause an increase in the overhead of multithread processing, and in particular, greatly affect multithread processing in units of small-grained threads (threads containing a small number of instructions).
[0015]
[Object of the invention]
An object of the present invention is to provide a high-speed user-level interrupt without the intervention of an operating system, and to improve the efficiency of multi-thread processing.
[0016]
Another object of the present invention is to provide a high-speed lock mechanism between processor elements in a multiprocessor computer system, and to improve the efficiency of multithread processing.
[0017]
[Means for Solving the Problems]
Of the present inventionFirstMulti-thread computer systemA processor including a plurality of processor elements and a main memory shared by the plurality of processor elements, dividing one user process into a plurality of threads having a small granularity, and under control of a thread scheduler in the user process. In a multi-threaded computer system that assigns multiple threads to multiple processor elements and executes them simultaneously,
Each of the processor elements includes, in addition to a register set, an operation unit, and a control unit, a counter whose value is decreased every clock, and a zero comparison which generates an interrupt request signal when the value of the counter becomes zero. A user handler register that holds a memory address where a thread scheduler in a user process is placed, and a user save PC that is a save destination register of a value of a program counter,
The processor starts user level interrupt processing in the processor element where the interrupt request signal is generated from the zero comparator, sets a value of a program counter in the user save PC, and sets a value of the user handler register in the program. An interrupt control unit to be set in the counter, and a set of 1-bit storage devices accessible from each processor element by a computer instruction set capable of exclusively operating values between the processor elements;
The thread scheduler in the user process sets the time quantum value to be allocated to the next thread to be executed in the counter in the processor element to which the next thread to be executed is allocated, and sets the own thread scheduler in the user handler register. Setting the memory address where it is located, causing the processor element to start execution of the next thread to be executed,
Exclusive control among a plurality of threads executed by a plurality of processor elements is performed using a set of the 1-bit storage devices.
[0018]
In addition, the present inventionSecondMulti-thread computer systemA processor including a plurality of processor elements and a main memory shared by the plurality of processor elements, dividing one user process into a plurality of threads having a small granularity, and under control of a thread scheduler in the user process. In a multi-threaded computer system that assigns multiple threads to multiple processor elements and executes them simultaneously,
Each of the processor elements includes, in addition to a register set, an operation unit, and a control unit, a counter whose value is decreased every clock, and a zero comparison which generates an interrupt request signal when the value of the counter becomes zero. A user handler register that holds a memory address where a thread scheduler in a user process is placed, and a user save PC that is a save destination register of a value of a program counter,
The processor starts user level interrupt processing in the processor element where the interrupt request signal is generated from the zero comparator, sets a value of a program counter in the user save PC, and sets a value of the user handler register in the program. A set of a queue structure that stores an interrupt control unit to be set in a counter and a token having an identification number corresponding to a processor element in the order of arrival, and a computer that can exclusively add, search, or delete tokens among the processor elements. And a set of queue structures accessible from each processor element by the instruction set.
The thread scheduler in the user process sets the time quantum value to be allocated to the next thread to be executed in the counter in the processor element to which the next thread to be executed is allocated, and sets the own thread scheduler in the user handler register. Setting the memory address where it is located, causing the processor element to start execution of the next thread to be executed,
Exclusive control among a plurality of threads executed by a plurality of processor elements is performed using a set of the queue structures.
[0019]
Also, a first multi-thread execution control method of the present invention includes a processor including a plurality of processor elements and a main storage memory shared by the plurality of processor elements, and converts one user process into a plurality of threads having a small granularity. In a multi-thread execution control method in a multi-thread computer system for dividing and assigning a plurality of threads to a plurality of processor elements under the control of a thread scheduler in the user process, a high-speed user level without an operating system is involved. To provide an interrupt,
(A) The memory address where the thread scheduler of the user process is placed is set in the user handler register in the processor element to which the thread of the user process is allocated, and the time quantum value to be allocated to the thread in the counter in the processor element. The setThen, the execution of the thread is started by the processor element, and the exclusive control between the thread that started the execution and another thread is provided in the processor and the operation of the value is exclusively performed between the processor elements. Performed using a set of 1-bit storage accessible from each processor element by a set of executable computer instructions.Stage
(B) updating the value of the counter in the processor element at a constant period simultaneously with the start of execution of a thread in the processor element, and generating a user-level interrupt when the count value reaches a predetermined count value
(C) In the processing of the user-level interrupt, the current program counter value of the processor element of the interrupt request source is set in the user save PC in the processor element, and the memory address set in the user handler register in the processor element Transferring control to a thread scheduler in a user process by setting
IncludingIt is characterized by the following.
[0020]
Further, a second multi-thread execution control method of the present invention includes a processor including a plurality of processor elements and a main storage memory shared by the plurality of processor elements, wherein one user process is provided with a plurality of threads having a small granularity. In a multi-threaded execution control method in a multi-threaded computer system in which a plurality of threads are assigned to a plurality of processor elements under the control of a thread scheduler in the user process and executed simultaneously, a high-speed user without an operating system intervenes. To provide a level interrupt,
(A) The memory address where the thread scheduler of the user process is placed is set in the user handler register in the processor element to which the thread of the user process is allocated, and the time quantum value to be allocated to the thread in the counter in the processor element. The setThen, the execution of the thread is started by the processor element, and the exclusive control between the thread that started the execution and another thread is performed in the processor that stores the token having the identification number corresponding to the processor element in the order of arrival. Using a set of queue structures that can be accessed from each processor element by a computer instruction set that allows exclusive addition, search, or deletion of tokens among the processor elements.
(B) updating the value of the counter in the processor element at a constant period simultaneously with the start of execution of a thread in the processor element, and generating a user-level interrupt when the count value reaches a predetermined count value
(C) In the processing of the user-level interrupt, the current program counter value of the processor element of the interrupt request source is set in the user save PC in the processor element, and the memory address set in the user handler register in the processor element Transferring control to a thread scheduler in a user process by setting
IncludingIt is characterized by the following.
[0021]
[Action]
When the counter reaches zero, the interrupt controller starts user level interrupt processing. In the user level interrupt processing, the value of the user handler register set in advance to the start address of the thread scheduler of the user process is set in the program counter, and control is transferred to the thread scheduler without passing through the operating system.
[0022]
Exclusive control among a plurality of threads executed by a plurality of processor elements is performed using a set of 1-bit storage devices or a set of queue structures provided in the processor,Provides a lock acquisition and release function that does not require access to main memory.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
[Description of configuration]
Embodiments of the present invention will be described in detail with reference to the drawings.
[0024]
FIG. 1 is a diagram illustrating an example of a computer configuration in which the present invention is implemented. The processor 1 has a plurality of processor elements 11, 12, and 19 therein, and these processor elements access a common main memory 2.
[0025]
Referring to FIG. 2, a first embodiment of the present invention relates to a processor 1 having a plurality of processor elements therein, an operating system 50 operating on the processor, and a user process 100 operating on the operating system. It is composed of
[0026]
Each processor element in the processor 1 includes a counter 26 and a zero comparator 25 for generating a user-level preemption interrupt, a user-level pre-emption interrupt, and a register set, an operation unit, and a control unit of a general computer processor. It has a user handler register 20 and a user save PC 23 used for control movement when an interrupt occurs.
[0027]
The value of the counter 26 is decremented every clock by the clock signal. The zero comparator 25 compares the value of the counter 26 with zero. The user handler register 20 is a register holding a program counter value to which execution control is to be transferred when a user level interrupt occurs, and the user save PC 23 is a register for saving the program counter value immediately before the user level interrupt occurs. is there.
[0028]
The program counter (PC) 22 and the interrupt control unit 41 of FIG. 2 have the same functions as the program counter and the interrupt control unit of a general computer processor, and the kernel handler register 21 and the kernel evacuation PC 24 are common. It has the same function as an interrupt handler register and a program counter saving register used when a normal interrupt occurs in a processor of a simple computer.
[0029]
The user process 100 is an entity of an execution program generated by the operating system 50. The user process 100 is composed of a plurality of threads 102, 103 and 104 sharing a main memory space, and these threads are assigned to processor elements and executed. The thread scheduler 101 exists inside the user process 100 in a form linked to the user program, and manages all threads constituting the user process.
[0030]
In the processor, there are a lock variable set 30 and an access arbitration mechanism 40 shared by all processor elements. The lock variable set 30 is a set of lock variables that can store a 1-bit state, and the access arbitration mechanism 40 is a mechanism for arbitrating access to the lock variable between the processor elements.
[0031]
[Description of operation]
The operation of the present exemplary embodiment will be described in detail with reference to FIG.
[0032]
When the operating system 50 starts the user process 100, the user process 100 calls a thread scheduler 101 incorporated therein. The thread scheduler 101 schedules a set of threads in the user process 100 according to a certain scheduling algorithm. When the thread scheduler 101 selects a thread to be executed next (here, the thread 102), the thread scheduler 101 sets a time quantum value to be assigned to the thread 102 in the counter 26 of the processor element 11 to which the thread 102 is assigned, and After setting the memory address where the scheduler 101 is located in the user handler register 20 of the processor element 11, the processor element 11 starts executing the thread 102.
[0033]
In parallel with the execution of the thread 102, the value of the counter 26 is reduced at regular intervals by the clock signal. When the value becomes zero, the zero comparator 25 sends an interrupt request signal to the interrupt control unit 41. The interrupt control unit 41 starts processing of a user-level interrupt in the processor element 11.
[0034]
When the user level interrupt process starts, the processor element 11 sets the current value of the program counter 22 in the user save PC 23 and sets the value of the user handler register 20 in the program counter 22. Thereby, the control is promptly transferred to the thread scheduler 101 inside the user process 100 without going through the operating system 50. The thread scheduler 101 saves the execution state of the thread 102 including the value of the register set in a management data area inside the thread scheduler 101, selects the next thread to start execution according to a predetermined scheduling algorithm, and The value of the register set of the thread is restored, and the time quantum value corresponding to the thread is set in the counter 26, and the execution of the next thread is started.
[0035]
On the other hand, a case where the conventional interrupt processing is used will be described below. First, the context is switched from the user program to the operating system at the start of the interrupt processing. For this context switch,
○ Setting the current value of the program counter 22 in the kernel save PC 24
○ Setting of the value of the kernel handler register 21 to the program counter 22
○ Switching processor operation mode to kernel mode
○ Save required register set contents to main memory
Is included. By this context switching, control is transferred to the kernel level interrupt handler 51 inside the operating system 50 and then to the process scheduler 52. The process scheduler 52 analyzes an interrupt factor and determines a process to be executed next according to a predetermined scheduling algorithm. Then, the context is switched again and the execution of the next process is started. For this context switch,
○ Setting of register set for next process
○ Setting the logical address space for the next process
○ Processing to switch the processor operation mode to user mode
Is included. After a series of these processes, control is finally transferred to the user process.
[0036]
In other words, the introduction of the user-level interrupt mechanism makes it possible to use a preemption mechanism that is faster than in the past, without the overhead of passing through the operating system, in the user program.
[0037]
Note that the interrupt factor of the user-level interrupt mechanism is not limited to the preemption interrupt due to the zero match of the down counter. If only the interrupt control unit is used, it can be used for the purpose of processing an invalid instruction interrupt in a user process, for example.
[0038]
Next, a high-speed lock mechanism using the lock variable set 30 will be described with reference to FIG. Each processor element accesses a lock variable inside the lock variable set 30 by using a test and set instruction provided in the present processor. When one processor element 11 uses a test and set instruction on a lock variable, the access arbitration mechanism 40 temporarily inhibits access to the lock variable from another processor element, during which the processor element 11 returns to the value of the lock variable. Is compared with zero and reflected in the status flag in the processor element 11, and the value 1 is set in the lock variable. From the viewpoint of software, the operation of the test and set instruction described in the present embodiment is similar to the operation of the test and set instruction provided in the conventional processor, but the access to the main storage memory causing a large delay is performed. Because it is not accompanied, variables can be locked with much less overhead than before.
[0039]
The number of lock variables mounted in the processor is suitably 8, 16, or 32. The reason is that a sophisticated exclusive control and synchronization control mechanism for the user can be easily constructed using a more basic exclusive control mechanism, and such a basic exclusive control mechanism uses a small number of lock variables. This is because the number of lock variables is set to a small power of 2 so that the width of an instruction field for specifying the number of a lock variable can be reduced and the instruction efficiency can be improved. Further, by setting the number of lock variables within 32 or 64 which is the general number of bits of the register set, the entire lock variable set can be handled as one special register. This makes it possible to include the lock variable set in the context corresponding to the process, and to use a logically independent high-speed lock mechanism for each process.
[0040]
The introduction of the user-level interrupt mechanism and the high-speed lock mechanism described above enables parallel processing in smaller units than before, thereby improving the effective performance of the multiprocessor computer and expanding its application field. This is the effect of the present embodiment.
[0041]
Another embodiment of the present invention
Next, another embodiment of the user level interrupt mechanism will be described.
[0042]
In FIG. 2, the input of the counter 26 is a clock signal, but this signal is not limited to the clock signal of the computer system. If the system clock signal obtained by dividing the system clock signal by a suitable frequency divider to a fraction is used as the input to the counter 26, the number of bits of the hardware constituting the counter 26 and the computer The bit width of the counter value field can be reduced, and the efficiency of both hardware and software can be improved. Instead of the system clock signal, a signal of the instruction execution control mechanism of the processor element may be input to the counter 26 so that the counter 26 is reduced every time one instruction is executed.
[0043]
Next, another embodiment of the high-speed lock mechanism will be described.
[0044]
Referring to FIG. 3, the second embodiment of the high-speed lock mechanism is such that each lock variable has a queue structure. Each of the queues 61, 62 and 69 can store tokens up to the number equal to the number of processor elements. The token is issued by each processor element, and the token is assigned the number of the issued processor element. If there is one or more tokens in the queue, it means that the processor element that issued the token at the head of the queue has locked the lock variable corresponding to the queue. To operate the lock variable, two types of computer instructions, a lock trial instruction and a lock release instruction, are provided. The queue control mechanism 60 provided between the processor elements 11, 12,..., 19 and the queues 61, 62,. , The operations of adding, searching, and deleting tokens are exclusively performed between the processor elements.
[0045]
When the processor element 11 executes the lock attempt instruction, the queue control mechanism 60 determines whether or not the token of the processor element 11 exists in the queue designated by the operand of the lock attempt instruction (here, the queue 61). Check, and if token does not exist, insert a new token. Further, the queue control mechanism 60 checks whether or not there is a token corresponding to the processor element 11 at the head of the designated queue 61, and sets the result in the status flag of the processor element 11. The user program determines whether or not the lock has been acquired by executing a branch instruction that refers to the status flag following the lock attempt instruction.
[0046]
When the processor element 11 executes the lock release instruction, the queue control mechanism 60 checks whether or not the token of the processor element 11 exists in the queue specified by the operand of the lock attempt instruction (here, the queue 61). Then, the token is removed from the queue 61, if any.
[0047]
This embodiment has an advantage that a more fair exclusion control mechanism can be realized in that the order in which locks are requested is stored in a queue and locks are acquired on a first-come, first-served basis.
[0049]
【The invention's effect】
A first effect of the present invention is that a user-level interrupt mechanism that does not pass through an operating system can be realized. As a result, the overhead for thread switching is reduced, and multi-thread execution with smaller granularity than before becomes possible.
[0050]
A second effect of the present invention is that exclusive control between processor elements can be realized without accessing a main storage memory having a relatively slow response speed. This reduces overhead related to thread management and communication between threads, and enables multi-thread execution with smaller granularity than before.
[0051]
Due to these low overhead effects, the application field of the shared memory type multiprocessor computer is expanded, and the performance can be improved by multithread execution even for a program with large granularity and low parallelism.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a computer on which the present invention is implemented.
FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a view showing a second embodiment of the high-speed lock mechanism according to the present invention.
[Explanation of symbols]
1 processor
2 Main memory
11-19 processor element
20 User handler register
21 Kernel handler register
22 Program Counter
23 User evacuation PC
24 Kernel save PC
25 Zero comparator
26 counter
30 Lock Variable Set
40 Access Arbitration Mechanism
41 Interrupt control unit
50 Operating system
51 Kernel level interrupt handler
52 Process Scheduler
60 Queue control mechanism
61-69 queue
100 user process
101 Thread scheduler
102-104 threads

Claims (4)

A processor including a plurality of processor elements and a main memory shared by the plurality of processor elements, dividing one user process into a plurality of threads having a small granularity, and under control of a thread scheduler in the user process. In a multi-threaded computer system that assigns multiple threads to multiple processor elements and executes them simultaneously,
Each of the processor elements includes, in addition to a register set, an operation unit, and a control unit, a counter whose value is decreased every clock, and a zero comparison which generates an interrupt request signal when the value of the counter becomes zero. A user handler register that holds a memory address where a thread scheduler in a user process is placed, and a user save PC that is a save destination register of a value of a program counter,
The processor starts user level interrupt processing in the processor element where the interrupt request signal is generated from the zero comparator, sets a value of a program counter in the user save PC, and sets a value of the user handler register in the program. An interrupt control unit to be set in the counter, and a set of 1-bit storage devices accessible from each processor element by a computer instruction set capable of exclusively operating values between the processor elements;
The thread scheduler in the user process sets the time quantum value to be allocated to the next thread to be executed in the counter in the processor element to which the next thread to be executed is allocated, and sets the own thread scheduler in the user handler register. Setting the memory address where it is located, causing the processor element to start execution of the next thread to be executed,
A multi-thread computer system according to claim 1, wherein exclusive control among a plurality of threads executed by a plurality of processor elements is performed using the set of 1-bit storage devices. A processor including a plurality of processor elements and a main memory shared by the plurality of processor elements, dividing one user process into a plurality of threads having a small granularity, and under control of a thread scheduler in the user process. In a multi-threaded computer system that assigns multiple threads to multiple processor elements and executes them simultaneously,
Each of the processor elements includes, in addition to a register set, an operation unit, and a control unit, a counter whose value is decreased every clock, and a zero comparison which generates an interrupt request signal when the value of the counter becomes zero. A user handler register that holds a memory address where a thread scheduler in a user process is placed, and a user save PC that is a save destination register of a value of a program counter,
The processor starts user level interrupt processing in the processor element where the interrupt request signal is generated from the zero comparator, sets a value of a program counter in the user save PC, and sets a value of the user handler register in the program. A set of a queue structure that stores an interrupt control unit to be set in a counter and a token having an identification number corresponding to a processor element in the order of arrival, and a computer that can exclusively add, search, or delete tokens among the processor elements. And a set of queue structures accessible from each processor element by the instruction set.
The thread scheduler in the user process sets the time quantum value to be allocated to the next thread to be executed in the counter in the processor element to which the next thread to be executed is allocated, and sets the own thread scheduler in the user handler register. Setting the memory address where it is located, causing the processor element to start execution of the next thread to be executed,
A multi-threaded computer system, wherein exclusive control among a plurality of threads executed by a plurality of processor elements is performed using a set of the queue structures. A processor including a plurality of processor elements and a main memory shared by the plurality of processor elements, dividing one user process into a plurality of threads having a small granularity, and under control of a thread scheduler in the user process. A multi-threaded execution control method in a multi-threaded computer system in which a plurality of threads are assigned to a plurality of processor elements and executed simultaneously,
(A) The memory address where the thread scheduler of the user process is located is set in the user handler register in the processor element to which the thread of the user process is allocated, and the time quantum value to be allocated to the thread in the counter in the processor element. To start the execution of the thread in the processor element, and exclusive control between the thread that started the execution and another thread is provided in the processor and exclusive value is set between the processor elements. the mosquito operations in a thread at the same time the processor elements perform the start and the in step (b) the processor elements to perform using a set of storage devices 1 bit accessible from each processor element by capable computer instruction set (C) generating a user-level interrupt when the count value reaches a predetermined count value. In the process of the user-level interrupt, the current program counter of the processor element that issued the interrupt request is updated. set the value to the user save PC within the processor element, including the step of transferring control to a thread scheduler in user process by setting a memory address that is set in user handler registers within the processor element to the program counter A multi-thread execution control method characterized by the above-mentioned. A processor including a plurality of processor elements and a main memory shared by the plurality of processor elements, dividing one user process into a plurality of threads having a small granularity, and under control of a thread scheduler in the user process. A multi-threaded execution control method in a multi-threaded computer system in which a plurality of threads are assigned to a plurality of processor elements and executed simultaneously,
(A) The memory address where the thread scheduler of the user process is located is set in the user handler register in the processor element to which the thread of the user process is allocated, and the time quantum value to be allocated to the thread in the counter in the processor element. Is set, the execution of the thread is started in the processor element, and the exclusive control between the thread that started the execution and another thread stores a token having an identification number corresponding to the processor element in the order of arrival. A set of queue structures in the processor, which is set using a set of queue structures that can be accessed from each processor element by a computer instruction set in which tokens can be added, searched, or deleted exclusively between the processor elements. Step (b) step of the value of the counter in the thread at the same time the processor elements perform the start and the in the processor elements is updated at a constant period, generates a user-level interrupt when it reaches a count value set in advance (c) In the processing of the user-level interrupt, the current program counter value of the processor element of the interrupt request source is set in the user save PC in the processor element, and the memory address set in the user handler register in the processor element is stored in the program counter. setting multithread execution control method the step of transferring control to a thread scheduler in user process is characterized in including that by the.

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