JPH05151064A - Tightly coupled multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce the traffic of a system bus and to improve the performance of the whole system by performing assignment in consideration of the effect of a cache memory when processors of threads are scheduled. CONSTITUTION:A shared memory is stored with the storage 1 of execution threads, an array assignable processor set 2, an executable thread set 3, a task set, an execution thread set 5, and an execution interruption thread set 6 respectively. One of the processors is provided with a scheduler 7 which assigns the threads of the processors according to the execution history of the execution threads, the assignable processor set 2, executable thread set 3, task set 4, execution thread set 5, and execution interruption threads 6 by referring to the relation between the threads and tasks. Then the threads whose processing is to be restarted are assigned preferentially to the processors to which the threads are assigned before.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tightly coupled multiprocessor system in which each processor has a cache memory, and more particularly to a thread scheduling system.

[0002]

2. Description of the Related Art Conventionally, there is a tightly coupled multiprocessor system including a shared memory connected to a system bus and a plurality of processors. FIG. 3 is a main part configuration diagram showing an example of this type of multiprocessor system. Each processor 10, 20, 30 is composed of a microprocessor unit MPU and a cache memory CM.
Each processor MPU may have a dedicated processor such as a floating point unit FPU. Each of these processors is connected to the shared memory 50 via the system bus 40.

The terms task and thread used in the present invention are defined here. A task is a unit that manages the resources of the system or computer required to actually perform the calculation, and refers to the unit of the address space. A thread is a unit of calculation execution, and a CPU
A unit of resource allocation. According to this definition, threads are executed in an environment managed in task units. In addition, a recent calculation model has proposed a multi-thread model in which multiple threads exist in one task, and such a concept of multi-thread is high in that it has good affinity with a multiprocessor system. Has been evaluated.

In the memory sharing type multiprocessor system based on such bus coupling, as the number of processors coupled increases, the traffic on the system bus 40 coupling the processors increases. Therefore, competition between processors occurs in memory access. When competition occurs between processors, the waiting time becomes long, and the performance of the entire system deteriorates. System bus 4
If the traffic of 0 can be reduced, the number of processors can be increased and the performance of the entire system can be improved. However, if the number of processors is increased, the traffic on the system bus 40 also increases, which causes more competition. To reduce the system bus traffic, it is effective to add a cache memory to each processor as shown in FIG.

[0005]

However, in the conventional scheduling method, that is, in the method of resuming a thread suspended in the middle of execution, the thread is assigned to an executable processor,
There is a problem that the cache memory that is effective in terms of hardware is not fully utilized. In other words, it does not mean that scheduling is performed with the effect of cache taken into consideration. In addition, the conventional method has a problem in that it does not consider the new programming model of multithreading.

The object of the present invention has been made in view of the above circumstances, and when a thread is scheduled to a processor in a multiprocessor system, the system bus of the system bus is allocated by allocating the effect of a cache memory. It is an object of the present invention to provide a tightly coupled multiprocessor system adopting a scheduling method that can reduce traffic and improve the performance of the entire system.

[0007]

In order to achieve such an object, according to the present invention, in a tightly coupled multiprocessor system, execution threads are stored in the shared memory, and an assignable processor set, an executable thread set, Each of the task set, the execution thread set, and the execution suspending thread set is stored, and the execution history of the execution thread, the assignable processor set, the executable thread set, and the task are stored in any one of the plurality of processors. A scheduler for allocating processor threads is provided by referring to the relationship between threads and tasks from a set, an execution thread set, and an execution suspension thread set.

[0008]

According to the present invention, when scheduling threads to processors, allocation is performed in consideration of the effect of the cache memory. That is, as a thread for resuming processing, the thread is preferentially assigned to the previously assigned processor. If the assignment is impossible, another thread belonging to the same task is assigned to the assigned processor. Since the logical space is shared in the same task, there is a high possibility that the cache data used by another thread in the same task will be reused. This can reduce system bus traffic.

[0009]

The present invention will be described in detail below. In a system with cache memory, if the thread that resumes execution is assigned to a different processor than before the suspension,
The operation of transferring the cache-missed data from the shared memory is always required, which increases the system bus traffic. On the other hand, when the thread that resumes execution is assigned to the processor that was executing before the suspension, if the data that was used before the suspension remains in the cache memory, use the data in the cache memory as is. This improves the program execution speed. Furthermore, data transfer from the shared memory is unnecessary, which reduces system bus traffic.

In view of this, the present invention preferentially allocates a thread for restarting processing to the processor to which the thread was previously allocated. If the allocation cannot be done, another thread belonging to the same task is allocated to the allocated processor. Since the same task shares a logical space, there is a high possibility that the cache data used by another thread in the same task can be reused. It is obvious that the data previously transferred in the cache memory can be effectively reused by adopting such a method. In order to realize such a scheduling method, a scheduler that implements the above-described scheduling algorithm and a memory that stores threads executed by each processor are required.

FIG. 1 is a block diagram for realizing this. In the figure, reference numeral 1 is an execution thread storage memory for storing threads executed by each processor. For each processor, n thread numbers (unique numbers assigned to each thread) previously executed by the processor are stored. Remember. n can be changed according to the characteristics of the task or thread. 2 to 6 are also memories, 2 is an assignable processor set, 3 is an executable thread set, 4 is a task set, 5 is an execution thread set,
Reference numeral 6 is a memory for storing each set of execution interrupt threads. 7 is a scheduler. And the solid arrow indicates that the thread belongs to the task indicated by the arrow,
The dashed arrow indicates the reference relationship to the memory that stores the thread that the processor was executing in the past.

The memories 1 to 6 are in the shared memory 50 in the configuration of FIG. 3, and the scheduler 7 is provided in any of the processors in the configuration of FIG. When assigning a thread to a processor, the scheduler 7 refers to the past execution history of threads in the execution thread storage memory 1 and the relationship between threads and tasks in the assignable processor set 2 or the execution suspended thread set 6. Schedule.

The operation of such a configuration will be described below with reference to the operation flow of FIG. FIG. 2 is an operation flow relating to the scheduling of processors that can be assigned at a certain time. When a certain processor (this processor is designated as P) becomes empty, processing is performed according to the following procedure. A thread (this thread is S
And select). By referring to the assignable processor set 2 and the execution thread storage memory 1, it is determined whether or not the selected thread S was previously executed by the processor P. If it has not been executed, move to the next step. If it has been executed, move to. It is determined whether the suspension time of the thread S exceeds T1. If it is over, move to the next process. If not, the process returns to. Whether the thread obtained by referring to the execution thread storage memory 1 and the assignable processor set 2 is the thread previously executed by the processor P is the same by referring to the task set 4, the execution thread set 5, and the execution interrupt thread set 6. Determine if it belongs to a task. If it does not belong, the process moves to the next process. If it belongs, the process shifts to. It is determined whether the suspension time of the thread S exceeds T2. If not, the process returns to. If it is over, move to the process. The thread S is executed by the processor P.

The above T1 and T2 represent the time effective for reducing the traffic on the system bus by executing the thread S in the processor P, and change depending on the cache memory configuration and the task / thread characteristics. T1 indicates the time when one thread is executed by the same processor, and T2 is the time when one thread is executed by the processor executed by another thread in the same task.

[0015]

As described above, according to the present invention,
By reflecting the effect of the cache memory on the scheduling, it is possible to reduce the traffic on the system bus and further improve the performance of the entire system. In particular, the larger the cache memory capacity, the larger the number of processors and the larger the system bus traffic, the more remarkable the effect.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a scheduling function portion in a shared memory type multiprocessor system according to the present invention.

FIG. 2 is an operation flow for explaining the operation.

FIG. 3 is a conceptual configuration diagram showing an example of a shared memory type multiprocessor system.

[Explanation of symbols]

 1 Execution Thread Storage Memory 2 Assignable Processor Set 3 Executable Thread Set 4 Task Set 5 Execution Thread Set 6 Execution Suspended Thread Set 7 Scheduler

Claims (1)

[Claims] 1. A tightly coupled multiprocessor system comprising a plurality of processors each having a shared memory and a cache memory connected to each other via a system bus, wherein the shared memory stores and allocates execution threads. Each of a set of executable processors, a set of executable threads, a set of tasks, a set of execution threads, and a set of suspended threads of execution is stored, and the execution history of the execution threads and allocation to any one of the plurality of processors are possible. A scheduler that allocates processor threads by referencing the relationship between threads and tasks from the processor set, executable thread set, task set, execution thread set, and execution interrupt thread set is provided to reduce system bus traffic. That Tightly coupled multiprocessor system according to symptoms.