JP2002342163A - Method for controlling cache for multithread processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a control method for effectively utilizing a cache by preventing competition among a plurality of instruction flows about a cache control method for a multithread processor performing the plurality of instruction flows. SOLUTION: A storage controlling part 107 stores shared/occupied states of threads in an occupancy flag 111 and occupied thread ID in an ID register 112 for each way of a cache 110 according to designation by software, statistical information of hardware resources, etc. The storage controlling part 107 decides the sharing/occupancy of a corresponding way by using the occupancy flag 111 when a cache error occurs in cache access, and decides whether a self-thread is occupied by using the ID register 112 in the case of occupancy. As a result of the decision, a replacement destination is selected from a way of thread sharing or self-thread occupancy, and data transfer is performed a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control method for a multi-thread processor in which a plurality of instruction streams are executed. It relates to a cache control method for effective use.

[0002]

2. Description of the Related Art In recent years, a multi-thread processor that executes a plurality of instruction streams, an SMT (Simultaneous Multi Thr
ead) Architectures such as processors are attracting attention. In the multi-thread processor, when an instruction fetch cannot be performed such as when an instruction cache miss occurs, hardware resources such as functional units are effectively used by actively switching threads to be fetched. Conventionally, in a multi-thread processor, registers and instruction buffers are implemented for multiple threads, but the cache, a valuable hardware resource, is shared by multiple threads, and the cache capacity and associativity are used effectively. .

[0003]

When a cache is shared by a plurality of threads, there is a problem that cache contention is likely to occur between the plurality of threads. On the other hand, it is conceivable to prepare a plurality of independent caches and assign a different cache to each thread. However, when the number of input threads is small, there is a problem that the use efficiency of the cache decreases.

The present invention has been made in view of the above-mentioned problem, and performs switching between thread sharing / thread occupation for a part of a cache in accordance with the characteristics of a thread that has been input, thereby enabling a plurality of threads to execute. The purpose of the present invention is to prevent cache contention and to make effective use of the cache.

[0005]

In order to solve the above-mentioned problems, the present invention provides a method for controlling a cache for a multi-thread processor which executes a plurality of instruction streams. (Threads or processes, etc.), or can be assigned to be used exclusively for a specific instruction flow.

Further, the present invention controls whether or not a specific thread occupies and uses each cache way.

[0007] It is also possible to configure so that for each line having a finer granularity than the way, a control is made as to whether or not a line is occupied and used by a specific thread.

Further, by allowing the number of ways / lines to be assigned to a thread to be specified by software, the thread allocation for each way / line can be controlled more flexibly.

Further, it is also possible to collect statistical information on the use of various hardware resources of the processor and dynamically control the thread allocation for each way based on the collected statistical information.

In the above-described cache control method, when the total number of ways occupied by a thread being entered exceeds the number of ways in the cache, the entry of a new thread is stopped to realize appropriate thread entry. It is possible.

In the above cache control method, in order to share a cache among a plurality of threads in the same process having the same memory space, whether or not a specific process occupies each way / line of the cache is used. May be configured to perform the control described above.

FIG. 1 is a diagram for explaining the concept of the present invention. As shown in FIG. 1, in the multi-thread processor, the cache 2 transfers data between the register 1 and the memory 3. When data transfer of a certain thread is performed, a portion of the cache 2 that is shared by threads or a portion occupied by the thread is used, and a portion occupied by another thread is not used. The thread shared portion of the cache 2 can be accessed by all threads.

In the example shown in FIG. 1, the cache access of the thread Th0 is limited to the occupying section 2-0 or the thread sharing section 2-2 of the thread Th0 of the cache 2, and the occupying section 2-1 of the thread Th1 is accessed. Can not.

Switching between thread sharing and thread occupation may be performed in units of ways or lines in the cache 2. In the present invention, information indicating thread sharing / thread occupation and information indicating the occupying thread are held for each way or line of the cache 2.

The following is a typical example of a method of assigning a thread to a way or a line of the cache 2. 1. Assigned at the time of thread entry according to the number of entered threads. 2. The number of ways or lines occupied by the thread is specified by software, and the thread is allocated according to the number. 3. Dynamic allocation is performed using statistical information on the use of various hardware resources.

If the processing is divided into a plurality of threads in the same process having the same memory space, there is data shared between the threads, and the way or line of the cache 2 is occupied for each thread. , Way or line are considered more efficient. In order to utilize this feature, the shared data between a plurality of threads in the same process is switched by switching between process sharing and process occupation for a part of the cache 2 according to the characteristics of the process input to the processor. To prevent cache conflicts between multiple processes while effectively using

The switching between the process sharing and the process occupation is performed in a way unit or a line unit of the cache 2. Therefore, in the present invention, information indicating process sharing / process occupation and information indicating the occupying process are held for each way or line of the cache 2.

The following is a typical example of a method of allocating a process to a way or a line of the cache 2. 1. Assigned at the time of process input according to the number of input processes. 2. The number of ways or lines occupied by the process is specified by software, and threads are allocated accordingly. 3. Dynamic allocation is performed using statistical information on the use of various hardware resources.

In a multi-thread processor, if the number of input threads is too large, hardware resources such as the cache 2 compete with each other, resulting in performance degradation. Therefore, the appropriate input thread becomes important. In the present invention, when the cache 2 is occupied by a thread that has already been entered and a cache cannot be allocated to a new thread, it is possible to prevent excessive thread entry by stopping thread entry.

[0020]

Embodiments of the present invention will be described below. [First Embodiment] FIG. 2 is a diagram showing a configuration example of a multi-thread processor in the case where cache thread allocation is performed in units of ways in the first embodiment.

As shown in FIG. 2, the multi-thread processor 100 includes a register 101, a program counter 102, an instruction reading unit 103, and an instruction buffer 104.
, An instruction issuing unit 105, an instruction execution unit 106, a storage control unit 107, a cache 110, and an occupation flag 111
And an ID register 112.

In the multi-thread processor 100, the register 101, the program counter 102, and the instruction buffer 104 are mounted for a plurality of threads. Instruction reading unit 1
03, the instruction issuing unit 105, the instruction executing unit 106, and the cache 110 are hardware resources shared by a plurality of threads. The details of these functions are well-known technologies, and thus description thereof is omitted.

The storage control unit 107 controls the data transfer between the memory and the cache 110. In particular, the storage control unit 107 determines whether a part of the cache 110 is shared by a plurality of threads or occupied by a specific thread. It has a function to control the allocation of each way.

The occupation flag 111 is a flag indicating thread sharing / thread occupation for each way. The ID register 112 is a register that holds a thread ID that occupies the corresponding way.

When accessing the cache 110, only the way shared by the thread or the way occupied by the own thread can be accessed, and the way occupied by another thread cannot be accessed.

FIG. 3 shows a case where cache thread allocation is performed in line units in the first embodiment.
FIG. 3 is a diagram illustrating a configuration example of a multi-thread processor.

As shown in FIG. 3, the register 201 and the program counter 20 of the multi-thread processor 200
2. The instruction buffer 204, the instruction reading unit 203, the instruction issuing unit 205, the instruction execution unit 206, and the cache 210
This is the same as the means shown in FIG.

The storage control unit 207 controls allocation of a part of the cache 210 to be shared by a plurality of threads or occupied by a specific thread for each line.

The occupation flag 211 is a flag indicating thread sharing / thread occupation for each line. The ID register 212 is a register for holding a thread ID occupying the line.

When accessing the cache 210, only a line shared by a thread or a line occupied by the own thread can be accessed, and a line occupied by another thread cannot be accessed.

Although the configuration shown in FIG. 3 requires more occupation flags and ID registers than the configuration shown in FIG. 2, the control can be performed in finer units such as lines.
Efficient thread allocation is possible.

As an example of specifying the number of ways / lines of a cache to be assigned to a thread from software, there is a method of providing an extended instruction for specifying the number of ways / lines. As a method of inserting the extension instruction, a method of explicitly specifying the extension instruction at the source code level via a library (library) or a method of adding an extension instruction by a compiler at the time of compilation can be considered.

When performing software control, it is necessary to add a special register and an extension instruction. As a special register, for example, a special register WNR / LNR holding the number of ways / the number of lines occupied by each thread is used.
(Way / Line Number Register). In addition, as for the addition of the extension instruction, the special register WNR / LNR
However, an extended instruction for reading / writing the number of ways / lines occupied by the thread is added to the instruction set.

The extended instructions to be added are as follows. Rd_wnr% rd: The WNR corresponding to the thread that executed the instruction is read, and the number of occupied ways is written to the register rd. Wr_wnr number of ways / number of lines: specified w
At the same time as writing the number of ways to the WNR, the thread executing the instruction occupies the specified number of ways. Rd_lnr% rd, address: L of the cache line corresponding to the address of the thread that executed the instruction
Reads NR and stores the number of occupied lines in register rd
Read in. Wr_lnr number of ways / number of lines, address: LNR is the number of lines for the specified cache line
And at the same time occupy the specified number of lines of cache lines in the thread that executed the instruction.

As another example of software control,
A method of preparing the following command and specifying the number of ways is also conceivable. -Cwbind -b process_id (thr
ead_id) number of ways: the number of ways of the cache that are to be specified, and process_id (th
read_id).

When the number of ways / lines occupied by a thread is designated by software, the storage controllers 107 and 207 specifically assign ways / lines, and occupy registers 111 and 211 and an ID register 11.
Change 2,212.

As an example of controlling the number of ways / number of lines to be assigned to a thread from hardware, there is a method using statistical information.

For example, the cache miss rate of each thread is collected at regular time intervals as statistical information, and the cache miss rate is compared with a certain reference value. If the cache miss rate is smaller than the reference value, the way / line occupancy is obtained. And the way / line is occupied when the cache miss rate is larger than the reference value.

FIG. 4 shows a control flow when the cache miss rate of each thread is used as the statistical information. The storage control units 107 and 207 collect statistical information (cache miss ratio) at regular intervals (step S1), and determine whether the cache miss ratio is larger or smaller than a certain reference value (step S2).

If the cache miss rate is larger than the reference value, it is determined from the occupation flags 111 and 211 whether or not there is a shared way / line that can be assigned to the corresponding thread (step S3). If there is a / line, a way / line is assigned to the corresponding thread (step S4). The occupation flags 111 and 211 of the assigned way / line are set to the occupation state, and the ID of the corresponding thread is set in the ID registers 112 and 212 (step S5). If there is no assignable shared way / line, the way / line occupied by the corresponding thread is not assigned (step S6).

If the cache miss rate is smaller than the reference value, it is determined from the occupation flags 111 and 211 whether or not there is a way / line occupied by the corresponding thread (step S7). if there is,
The way / line occupied by the corresponding thread is released, the occupation flags 111 and 211 are set in a shared state, and the ID registers 112 and 212 are cleared (steps S8 and S8).
9). If there is no way / line already occupied,
The way / line to be occupied is not allocated, and the state is maintained (step S6).

FIG. 5 shows a control flow of the storage control units 107 and 207 at the time of cache access in the first embodiment. In FIG. 5, only the flow of the control according to the present invention will be described, and the other control will not be described because it is the same as the conventional control.

In the storage control units 107 and 207, when a cache access occurs, a cache tag, a thread I
D is checked (step S11), and a cache hit / cache miss is determined (step S12).
In the case of a cache hit, the corresponding line is accessed (step S17).

In the case of a cache miss, the occupation flag 1
According to 11 and 211, it is determined whether the line is thread sharing / thread occupation for each line of the corresponding cache tag (step S13). If the line is cache occupying, the own thread is occupied by the ID registers 112 and 212. It is determined whether or not it has been performed (step S14).

If the result of the determination is that the relevant line is shared by the thread or occupied by the own thread, a replacement destination is selected from the line shared by the thread or the line occupied by the own thread (step S15), and the cache is accessed. Update the access information. That is, data is transferred from the memory to the corresponding line selected as the replacement destination (step S17). Lines occupied by different threads are excluded from replacement candidates (step S16). [Second Embodiment] As a second embodiment, a case will be described in which the cache thread allocation method realized in the first embodiment is applied to each process.

FIG. 6 is a diagram showing an example of the configuration of a multi-thread processor when the process allocation is controlled in units of ways. In the example shown in FIG. 6, the process P0 and the process P1 are being executed on the multi-thread processor 300, and the process P0 is divided into threads Th0 to Th2. In FIG. 6, an occupation flag 311 indicates process sharing / process occupation for each corresponding way.
The ID register 312 stores the process I occupying the corresponding way.
Hold D.

When the process P0 (thread Th0 to thread Th2) accesses the cache 310, the process occupation part and the process sharing part of the cache 310 can be accessed. In this example, all the ways can be accessed.

On the other hand, when the process P1 (thread Th3) accesses the cache 310, it can access only the process sharing unit.

When a cache miss occurs, the storage control unit 307 selects a replacement destination from a line shared by the process or a line occupied by the own process under the same control as the control described in FIG. Transfer data from memory to line.

The method of controlling the number of ways / lines to be allocated to the thread uses the same method as in the first embodiment. It is also possible to specify it on the command line.

[0051]

By specifying the sharing or occupation of a thread or a process for a way or a line of a cache, a cache conflict between a plurality of threads can be reduced. Furthermore, by using hardware statistical information and instructions from software to appropriately select a cache way or line to be assigned to each spread or process, more efficient multi-thread processing can be performed.

[Brief description of the drawings]

FIG. 1 is a conceptual explanatory diagram of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a multi-thread processor in the case where cache thread allocation is performed in units of ways according to the first embodiment;

FIG. 3 is a diagram illustrating an example of a configuration of a multi-thread processor in a case where cache thread allocation is performed in line units according to the first embodiment;

FIG. 4 is a diagram illustrating a flow of control in a case where assignment of thread sharing / occupation is controlled by hardware.

FIG. 5 is a diagram showing a flow of control at the time of cache access of the storage control unit according to the first embodiment.

FIG. 6 is a diagram illustrating a configuration example of a multi-thread processor in a case where cache process allocation is performed in way units according to the second embodiment;

[Explanation of symbols]

 Reference Signs List 1 register 2 cache 3 memory 101 register 102 program counter 103 instruction reading unit 104 instruction buffer 105 instruction issuing unit 106 instruction execution unit 107 storage control unit 110 cache 111 occupation flag 112 ID register

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Claims (5)

[Claims] 1. A method for controlling a cache for a multi-thread processor that executes a plurality of instruction streams, wherein a part of the cache is shared by a plurality of instruction streams or occupied by a specific instruction stream. Cache control method for a multi-thread processor, characterized in that the cache control method has means for designating the allocation of a thread. 2. A cache control method for a multi-thread processor according to claim 1, wherein a control is performed as to whether a specific thread or a specific process occupies or uses each cache way or line. Cache control method for multi-thread processors. 3. A cache control method for a multi-thread processor according to claim 1, further comprising means for designating, from software, the number of ways or the number of lines exclusively allocated to a specific instruction stream. A cache control method for a multi-thread processor. 4. The cache control method for a multi-thread processor according to claim 1, wherein the specification for each way or each line is performed based on statistical information of hardware resource use of the multi-thread processor. A cache control method for a multi-thread processor, comprising means for controlling exclusive allocation to an instruction stream. 5. The cache control method for a multi-thread processor according to claim 1, wherein when the total number of ways occupied by a thread being entered exceeds the number of ways in said cache. A cache control method for a multi-thread processor, which has means for stopping input of a new thread.