JPH02181844A - Cache memory controlling method - Google Patents

Cache memory controlling method

Info

Publication number
JPH02181844A
JPH02181844A JP1001719A JP171989A JPH02181844A JP H02181844 A JPH02181844 A JP H02181844A JP 1001719 A JP1001719 A JP 1001719A JP 171989 A JP171989 A JP 171989A JP H02181844 A JPH02181844 A JP H02181844A
Authority
JP
Japan
Prior art keywords
cache
times
number
calculated
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1001719A
Inventor
Takashi Koizumi
Akihiro Yamada
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Priority to JP1001719A priority Critical patent/JPH02181844A/en
Publication of JPH02181844A publication Critical patent/JPH02181844A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To improve the cache hit rate of a CPU by redistributing a cache memory use area for each CPU according to distribution ratio to be calculated by the number of times of access and the number of times of cache mishit.
CONSTITUTION: The number of times of access per unit time to a cache memory 4 of each of the CPUs 1 to 3 is calculated, and by counting response signals 7 to 9, the number of times of cache hit per unit time of each CPU for the cache memory 4 is calculated. Besides, the number of times of the cache mishit is calculated. Further, the cache hit rate of each CPU 1 to 3 for the cache memory 4 is calculated, and this cache hit rate and a value set beforehand are compared with each other, and when the cache hit rates of one or more CPUs are less than the set value, the distribution ratio of the new use area of the cache memory 4 for the CPUs 1 to 3 is calculated from the number of times of the cache access and the number of times of the cache mishit. Thus, by redistributing the cache memory use area for each CPU, the cache hit rate of the CPU is improved.
COPYRIGHT: (C)1990,JPO&Japio
JP1001719A 1989-01-06 1989-01-06 Cache memory controlling method Pending JPH02181844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1001719A JPH02181844A (en) 1989-01-06 1989-01-06 Cache memory controlling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1001719A JPH02181844A (en) 1989-01-06 1989-01-06 Cache memory controlling method

Publications (1)

Publication Number Publication Date
JPH02181844A true JPH02181844A (en) 1990-07-16

Family

ID=11509374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1001719A Pending JPH02181844A (en) 1989-01-06 1989-01-06 Cache memory controlling method

Country Status (1)

Country Link
JP (1) JPH02181844A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2763714A1 (en) * 1997-05-26 1998-11-27 Bull Sa Replacement Counters machine has nonuniform memory access
JP2007206806A (en) * 2006-01-31 2007-08-16 Matsushita Electric Ind Co Ltd Cache observation system, analysis method of processor, and cache memory
JP2009059077A (en) * 2007-08-30 2009-03-19 Toshiba Corp Cache system
JPWO2007096999A1 (en) * 2006-02-24 2009-07-09 富士通株式会社 Separation device and method
JP2009223792A (en) * 2008-03-18 2009-10-01 Fuji Xerox Co Ltd Image processing apparatus
JP2013502645A (en) * 2009-08-21 2013-01-24 エンパイア テクノロジー ディベロップメント エルエルシー Allocation of processor cores with cache memory connectivity
JP2015036959A (en) * 2013-08-16 2015-02-23 富士通株式会社 Cache memory control program, processor including cache memory, and cache memory control method
JP2015222477A (en) * 2014-05-22 2015-12-10 富士通株式会社 Information processor, information processing system, control method of information processor and control program of information processor

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2763714A1 (en) * 1997-05-26 1998-11-27 Bull Sa Replacement Counters machine has nonuniform memory access
EP0881579A1 (en) * 1997-05-26 1998-12-02 Bull S.A. Replacement counters for non-uniform memory access machine
US6148378A (en) * 1997-05-26 2000-11-14 Bull S.A. Process for operating a machine with non-uniform memory access and cache coherency and a machine for implementing the process
JP2007206806A (en) * 2006-01-31 2007-08-16 Matsushita Electric Ind Co Ltd Cache observation system, analysis method of processor, and cache memory
JPWO2007096999A1 (en) * 2006-02-24 2009-07-09 富士通株式会社 Separation device and method
JP4576453B2 (en) * 2006-02-24 2010-11-10 富士通株式会社 Cache control circuit, information processing apparatus, and disconnection method
US8185699B2 (en) 2006-02-24 2012-05-22 Fujitsu Limited Cache memory controller and cache memory controlling method
JP2009059077A (en) * 2007-08-30 2009-03-19 Toshiba Corp Cache system
JP2009223792A (en) * 2008-03-18 2009-10-01 Fuji Xerox Co Ltd Image processing apparatus
JP2013502645A (en) * 2009-08-21 2013-01-24 エンパイア テクノロジー ディベロップメント エルエルシー Allocation of processor cores with cache memory connectivity
JP2015036959A (en) * 2013-08-16 2015-02-23 富士通株式会社 Cache memory control program, processor including cache memory, and cache memory control method
JP2015222477A (en) * 2014-05-22 2015-12-10 富士通株式会社 Information processor, information processing system, control method of information processor and control program of information processor

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