JPH01276261A - Interruption control device - Google Patents

Abstract

PURPOSE:To form an interruption control device with a high interruption responsiveness by causing the sequence of the coupling of a daisy chain to be variable according to a value set to an interruption prior level register. CONSTITUTION:A variable daisy chain 7 has a characteristic to be set at a prior level to be originally provided on a hardware when values on respective prior registers 2 in an initial condition, namely, after they are reset are all in a condition to be reset or when the values in respective prior registers 2 are plurally the same. By causing the daisy chain 7 to be variable according to a priority set to the prior level registers 2 to respective interruptions by means of a program by a user, a processing can be executed by surely accepting the interruptions successively in the priority according to the intention of the user program, namely, an emergency degree. Thus, the interruption control device can be realized in which an overhead at the time of accepting the interruption is canceled and which is excellent in the responsiveness.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interrupt control device for a processor that processes multiple interrupts at high speed.

BACKGROUND ART In recent years, systems using multiple microprocessors have been developed, and their scale has become larger and more complex.

Processors incorporated in application systems generally manage the entire system in many cases, and the number of tasks (hereinafter referred to as tasks) that they are responsible for is increasing. Since tasks in a processor are often activated by interrupt signals generated externally or internally, it has become necessary for the processor to manage and process a large number of interrupts.

There are various types of interrupts, such as those with a high level of urgency and those with a low level of urgency, and an interrupt control device that performs optimal and efficient processing has become necessary for the application system.

An example of a conventional interrupt control device will be described with reference to FIG. In FIG. 2, n interrupt factors 1 of BO...Bn are controlled, and a data bus 9 . An interrupt priority register 2 that can be arbitrarily set using the address bus 10 is provided, and an interrupt request signal RBO from each interrupt source is provided.
The RBn are sequentially connected by a daisy chain, accept one interrupt and its interrupt priority level from each interrupt request, and output an interrupt processing start signal 11 to the processor and a reset signal for the accepted interrupt cause. It is composed of a circuit 6.

The operation according to the conventional configuration shown in FIG.
The interrupt request signal RBm and its interrupt priority level VBm are sent to the circuit 6 for interrupt acceptance, and if the processor side is in a state where acceptance is possible, the interrupt cause Bm is immediately accepted and processed, and the interrupt request is sent to the interrupt cause Bm. It indicates that the request has been accepted and sends a reset signal to clear the cause. In this case, if the processor is already processing another interrupt factor Be, and if the interrupt priority level VBe being processed is lower than that of the previous interrupt, VBm, the processing of interrupt factor B& is interrupted; Processing for interrupt cause Bm is executed first, and after completion, processing for interrupt cause Be is restarted. Furthermore, when multiple interrupt factors Bi and Bi+1 with the same priority level occur simultaneously, the priority levels VBi and VBi+1 of both of them have the same value, but VBi with the higher priority level is processed first in the daisy chain. Even after interrupt factor Bi is processed, interrupt request RBi+1 is generated, and VBi+
If no interrupt priority level higher than 1 has occurred and no other interrupt with a priority level higher than Bi+1 has occurred due to daisy chaining, interrupt cause B
i±1 is subsequently accepted and processed. However, if two interrupt causes, BO and Bn, occur at the same time and their respective interrupt priority levels are set as VBO<VBn, the priority level on the hardware due to daisy chain takes priority, so - The processor accepts the cause BO, and then, if no other interrupt with a higher priority level than Bn has occurred, it interrupts the processing of the interrupt cause B○ that was accepted earlier, and then accepts and processes the interrupt cause Bn. Become. Generally, the value set in the interrupt priority level register by a program represents the user's level of urgency, and by the time the interrupt factor Bn given priority by the user is accepted by the processor and processing begins, As described above, unnecessary time is required and overhead is generated for interrupt acceptance, and such conventional technology may impair interrupt responsiveness.

Problems to be Solved by the Invention As is clear from the description of the prior art described above, according to the prior art, multiple interrupts occur simultaneously, and the interrupt priority level of each interrupt is determined by the hardware by daisy chaining. If the priority level is set in the opposite direction from the upper priority level, there is an inconvenience that it takes an unnecessary amount of time until the interrupt with the highest priority level on the software is accepted. An object of the present invention is to solve such problems and provide an interrupt control device with high interrupt responsiveness.

Means for Solving the Problems The present invention provides an interrupt control device having a function of rearranging the daisy chain according to the value set in the interrupt priority level register in order to preferentially control the level to be used by the interrupt priority register. be.

According to the present invention, the problem of the overhead of interrupt acceptance when multiple interrupts occur in the prior art is solved by making the order of daisy chain connection variable according to the value set in the interrupt priority level register. , it is possible to provide an interrupt control device with high interrupt responsiveness.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an interrupt control system in an embodiment of the present invention. In FIG. 1, 1 is an interrupt factor, 2 is a register for setting the priority level for interrupts, 7 is a variable daisy chain whose connection order can be changed according to the value set in the interrupt priority level register 2; 4 is a wired OR circuit for each separate request signal; 8 is a circuit for accepting interrupts; and 9 and 10 are data buses and address buses for accessing (reading and writing) the interrupt priority register 2, respectively.

Next, the operation of the interrupt control device of this embodiment will be explained below. First, when a certain interrupt Am occurs, the interrupt request signal RAm is sent to the interrupt acceptance circuit 8 through the variable daisy chain 7, and when it is accepted, the interrupt acceptance signal is sent to the signal line 11.
A signal is sent to the processor side through the reset signal line 12 to start processing, and a signal to clear the interrupt request for the interrupt cause Am is sent to the reset signal line 12. In this case, if a certain interrupt Ae is already being processed on the processor side, if the interrupt priority vector VAe is greater than or equal to VAm, the interrupt Am will be accepted after waiting for the processing of Ae to finish. If VAe is smaller than VAm, interrupt processing Ae is interrupted and processing Am is processed first. In the variable daisy chain 7, in the initial state, that is, after reset, the values in each priority register 2 are all reset, or in the case where multiple values in each priority register 2 are the same, the variable daisy chain 7 returns to its original priority level on the hardware. It has the properties that are set. In the case of this embodiment, APRO...A
If all PRn are set to the same level, the variable daisy chain 7 is connected in the order of AO...An, with AO holding the highest priority. Therefore, when a plurality of interrupts of the same level occur, each interrupt is processed in order according to the priority level by the variable daisy chain 7 as described above.

Similarly, if multiple interrupts with different priority level register values occur, the variable daisy chain changes the order of their combination according to the value of each interrupt priority level register, and then interrupts each interrupt in turn according to the set priority level. Interrupts are processed.

As described above, according to this embodiment, by making the daisy chain variable according to the priority set by the user program in the priority level register for each interrupt, the priority order according to the will of the user program, that is, the degree of urgency can be changed. It is possible to realize an interrupt control device that can reliably accept and process interrupts in order, and that has excellent responsiveness and eliminates the problem of excessive interrupt reception.

Effects of the Invention According to the present invention, means for determining each arbitrary interrupt priority level by software for a plurality of interrupt causes, and an interrupt priority level register for holding the set interrupt priority level are provided. The interrupt request generation circuits are sequentially connected by a daisy chain, and the means for determining the priority level by hardware, and the daisy chain automatically rearranges the order of connection according to the interrupt priority level set by the software. Even when multiple interrupts occur simultaneously, interrupt reception eliminates processing overload and ensures that interrupts are accepted in order according to the priority set by the user program. It is possible to provide an interrupt control device with excellent responsiveness that can accept and process interrupts.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an interrupt control method according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an interrupt control method according to a conventional technique. 1... Interrupt factor, 2... Interrupt priority level register, 3... Daisy chain gate, 4... Interrupt request signal wired OR circuit, 5 ...Interrupt priority level output switch, 6
・・・・・・Circuit for interrupt reception, 7・・・Variable daisy chain, 8・・・・・・Circuit for interrupt reception, 9
... Data bus, 10 ... Address bus, 11 ... Signal (interrupt processing start signal) for accepting interrupts to the processor, 12 ... For accepting interrupts. Reply, 13...The reception is currently at the interrupt priority level of medium or processing. Name of agent: Patent attorney Toshio Nakao and one other person 9-Deke

Claims (1)

[Claims] It has means for setting arbitrary interrupt priority levels for multiple interrupt sources, and a group of interrupt priority level registers that hold the set interrupt priority levels, and each interrupt request generation circuit is connected in sequence by a daisy chain. and means for determining the interrupt priority level, and the daisy chain operates according to the set interrupt priority level.
An interrupt control device characterized by having a function of automatically rearranging the order of connections.