JPS61260714A - Timing pulse generating circuit - Google Patents

Abstract

PURPOSE:To decrease the timing error by detecting a level of a reference clock when an input pulse is inputted and changing over a clock counted by a counter with the reference clock and its inverting clock. CONSTITUTION:A detecting circuit 3 detecting a level of the reference clock when an input pulse 1 having no synchronous relation with the reference clock is inputted, a selection circuit 4 selecting one of the reference clock and the inverting clock being the inversion of the reference clock by the output of the detection circuit, a counter 5 counting the clock outputted from the selection circuit ad a reset circuit 6 bringing the counter into the initial state when the input pulse is inputted, are provided. Further, a decode circuit 7 generating a timing pulse after a prescribed number of clocks after the input pulse is inputted by decoding the output of the counter is provided. Thus, the timing error when the input pulse is inputted until the timing pulse is outputted is kept within a half clock of the reference clock.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to timing pulse generation circuits used in digital circuits.

2. Description of the Related Art A conventional timing pulse generator outputs a desired timing pulse by decoding the output of a counter that counts a reference clock. In the following, a burst gate circuit that extracts only a horizontal synchronization signal from a decoded synchronization signal used in video signal processing, etc., and creates a burst gate pulse for extracting a burst signal of a color signal will be described.

FIG. 4 shows an example of a conventional burst gate circuit. In the figure, when a decoded synchronization signal is input from input terminal 1, D flip-flop Q8 becomes H level, and counter 5 starts counting the 25 MHz reference clock input from input terminal 2. The decode circuit 10 decodes the 114th clock and outputs a pulse, which resets Q8 and also resets the counter 5. The reason for decoding the 114th clock is
This is because it does not accept equivalent pulses or vertical synchronization pulses, but only supports horizontal synchronization signals, so if Q8 is reset at the 114th clock, it will be LO when the next water synchronization signal is input.
maintain the level. The 2o clock is decoded in the decode 5 circuit, the 12th clock is decoded in the decode C[nl] circuit, and the RS flip-flop Q? A pulse is outputted to the reset input and set input of Q9, and a pulse that becomes an H level only during the burst period is created and outputted from the output terminal 10.

Problems to be Solved by the Invention However, in the configuration described in -, there is no synchronous relationship between the horizontal synchronizing signal and the reference clock of 2.5 MHz, so the input timing of the horizontal synchronizing signal input to terminal 1 is However, as shown in the timing diagram of Figure 5, case 1
At the same timing in case 2 and case 2,
A burst gate pulse is output. Case 1 is the reference clock.

This is a case where the horizontal synchronization signal is input during the level period, and case 2 is a case where the water Y synchronization signal is input during the period when the reference clock is at Hi level. That is, the timing at which the burst gate pulse is output from the horizontal synchronization signal input has an error of at most one clock. In order to reduce this error, it is usually done by increasing the frequency of the reference clock, but this has the disadvantage that the number of counter stages increases and the decoding circuit becomes complex. Means for Solving the Problems In order to solve the above problems, the timing pulse generation circuit of the present invention includes a detection circuit that detects the level of the reference clock when an input pulse that has no synchronous relationship with the reference clock is input; A selection circuit that selects either the reference clock or an inverted clock obtained by inverting the reference O-riff based on the output of the detection circuit, a counter that counts the clock output from the selection circuit, and a counter that receives the input pulse. a reset circuit that sets the counter to an initial state when the input pulse is input; and a decode circuit that generates a timing/ζ pulse after a predetermined number of clocks after the input pulse is input by decoding the output of the counter. It is constructed by

5. Effect of the present invention With the above-described configuration, the present invention detects the level of the reference clock when an input pulse that has no synchronization relationship with the reference clock is input, and detects the level of the reference clock when an input pulse having no synchronization relationship with the reference clock is input, and selects the clock counted by the counter based on the level of the reference clock as the reference clock. By switching the reference clock with an inverted clock, the timing error from the input pulse to the timing pulse output at a constant timing can be kept within half a clock of the reference clock.

Embodiments Hereinafter, timing pulse generation circuits according to embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a burst gate circuit according to an embodiment of the present invention. In the figure, 1 is an input terminal for a decoded synchronization signal, 2 is an input terminal for a reference clock, 3 is a detection circuit, 4 is a selection circuit, 5 is a counter, 6 is a reset circuit, 7 is a decode circuit, and 8 is a burst gate pulse. , 9 is a power supply (hereinafter referred to as vDD), and 1o is a decoding circuit. When a horizontal synchronizing signal is input from the input terminal 161, -, the D flip-flop Q8 becomes Hi level and remains Hi level until a pulse is output from the decode a[9J path. D flip-flop Q1o is a detection circuit that detects the level of the reference clock when Q8 changes from the LO level to the H level. 4 is a selection circuit, Ql. With the output of Q
When the reference clock 8 is switched from the LO level to the Hi level, an inverted clock obtained by inverting the reference clock is output when the reference clock is at the Hi level, and when the reference clock is at the LO level, the reference clock is output. θ is a reset circuit, which generates a pulse to reset the counter 5 for one reference clock period after Q8 switches from LO level to Hi level, and after the reset pulse, counter 5 starts counting. Decoding 8 circuits 10 are 11
The second clock is decoded and a pulse is output to reset Q8. Q8 is reset, counter 5 is also reset, and selection circuit 4 also stops outputting. 7 is a decoding circuit, decoding 5 circuit, decoding C circuit, R871\-
- Consists of flip-flop Q9. The 18th clock is decoded in the decode 5 circuit, and the 10th clock is decoded in the decode C circuit.
input to the set input. As a result, in Q9,
A burst gate pulse that is at Hi level only during the burst period is generated and output from the output terminal 8. Figure 2 is a timing diagram when the reference clock is at Hi level when the water/F-sync signal is input from input terminal 1. In the third section, the horizontal synchronization signal is input from input terminal 1. FIG. 12 is a timing diagram when the reference clock is at Lo level when S'I'l.

As described above, according to this embodiment, the level of the reference clock when the horizontal synchronization signal is input is detected, and the clock supplied to the counter is switched between the reference clock and its inverted clock according to the detected level. As a result, the timing error in switching the burst gate pulse from the water synchronization signal can be kept within half a clock of the reference clock, so it is possible to reduce the timing error without increasing the frequency of the reference clock.

Effects of the Invention As described above, the timing pulse generation circuit of the present invention includes a detection circuit that detects the reference clock level when an input pulse having no synchronous relationship with the reference clock is input, and an output of the detection circuit to detect the reference clock level. a selection circuit for selecting either a clock or an inverted clock obtained by inverting the reference clock; a counter for counting the clock output from the selection circuit; and setting the counter to an initial state when the input pulse is input. By providing a reset circuit and a decoding circuit that generates a timing pulse a predetermined number of clocks after the input pulse is input by decoding the output of the counter, the timing pulse is generated after the input pulse is input. An excellent effect can be obtained in that the timing error at the point where the clock is output can be reduced to within half a clock of the reference clock without increasing the frequency of the reference clock.

[Brief explanation of drawings]

9'''-/ FIG. 1 is a timing pulse generation circuit according to an embodiment of the present invention, FIGS. 2 and 3 are timing diagrams of the embodiment of FIG. 1, and FIG. 4 is a conventional timing pulse generation circuit. , Fig. 5 is a timing diagram of the conventional example shown in Fig. 4. 1... Input terminal, 2... Input terminal, 3...
・Detection circuit, 4... Selection circuit, 5... Counter,
6...Reset circuit, 7...Decode circuit,
8...Output terminal, 9...Power supply, 10...8 decoding circuits. Name of agent: Patent attorney Toshio Nakao and 1 other person - 〇

Claims (1)

[Claims] A detection circuit detects the level of the reference clock when an input pulse that has no synchronization relationship with the reference clock is input, and one of the reference clock and an inverted clock obtained by inverting the reference clock is selected based on the output of the detection circuit. a selection circuit that counts clocks output from the selection circuit; a reset circuit that initializes the counter when the input pulse is input; and a selection circuit that decodes the output of the counter. 1. A timing pulse generation circuit comprising a decoding circuit that generates a timing pulse a predetermined number of clocks after an input pulse is input.