JPH01106674A - Synchronizing signal regenerating circuit - Google Patents

Abstract

PURPOSE:To obtain a regenerating synchronizing signal where a dislocation from a synchronizing signal is almost eliminated and a noise is removed by generating the window signal of a prescribed width synchronizing to the leading edge or trailing edge of the synchronizing signal and detecting the leading edge and trailing edge of the synchronizing signal only when the window signal exists. CONSTITUTION:When the synchronizing signal separated from the video signal of a television camera, etc., is inputted, a trailing detecting circuit DPC and a leading detecting circuit UPC detect the leading and trailing edges. The leading or trailing window signal of the prescribed width is generated by a window signal generating circuit UWC or DWC whenever the tie passes from plural known leading edges to trailing edges (or to the contrary) to be contained in the synchronizing signal synchronizing to the detecting outputs. Since, at such a time, the circuits DPC and UPC are operated only when the window signal exists and a set/reset pulse is outputted, the reproducing signal can be obtained in which the noise is removed and the dislocation is generated only by one clock.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a synchronization signal reproducing circuit for reproducing a synchronization signal contained in a video @ signal of a television etc. The present invention relates to a synchronization signal reproducing circuit that removes noise and reproduces a synchronization signal.

<Prior Art> A synchronization separation circuit that separates a synchronization signal contained in a video signal and reduces the influence of noise contained therein was put into practical use by the applicant on September 14, 1986. An application for new patent registration (8>r name of invention S: synchronous signal separation circuit) has been filed.

In this application, this noise is detected by focusing on the relationship between the pulse width of the separated synchronization signal and the width of change in noise. In other words, since the pulse width of this separated sync signal is known in advance, when there is a change in the level of the separated sync signal, a period signal having a pulse width close to that of this separated sync signal is output in synchronization with this separated sync signal. If the level of the separated sync signal changes while the period signal exists, it is assumed that there is noise and the output does not change, and the level of the separated sync signal changes while the period signal exists. If not, it is assumed that there is no noise, and a correct synchronization signal corresponding to the separated synchronization signal is output after a predetermined time delay.

<Problems to be Solved by the Invention> However, such a conventional synchronization signal reproducing circuit obtains a synchronization signal from which noise has been removed after a predetermined delay from the synchronization lfi signal input from a television camera, etc. There is a problem in that when an image processing device or the like is operated using the detected synchronization signal, a shift occurs in the image.

<Means for Solving the Problems> In order to solve the above problems, the present invention focuses on the following characteristics of the synchronization signal.

FIG. 5 shows the waveform of the synchronization signal separated from the Eiya signal. The waveform (b) follows the waveform (a).

This synchronization signal <SYN>(<SYN> means inversion of SYN) is applied during the first field period as shown in FIG.
Second field period, equivalent pulse period, vertical synchronization signal W
There are three types of periods from the falling edge to the rising edge of the pulse included in these periods: ■, ■, and ■. ,
It can be seen that there are five types: ■ and ■.

Therefore, based on these findings, the present invention first detects these falling or rising edges, and after a time corresponding to each pulse width has elapsed after detecting these falling edges or rising edges, the pulse width is adjusted to an appropriate width. A synchronization signal with reduced noise by generating a wind signal, detecting the rise and fall of the corresponding synchronization signal in the presence of this wind signal, and determining that the fall or rise in the absence of the wind signal is noise. It is designed to reproduce.

Specifically, the present invention provides a falling edge detection means for receiving a separated synchronizing signal included in a video signal and inputting a falling window signal to detect the falling edge of the synchronizing signal; and a rising edge detection means for detecting the rising edge of the synchronizing signal by inputting the rising window signal separately, and for detecting a plurality of known rising edges included in the synchronizing signal in synchronization with the output of the falling detecting means. A rising window generating means generates a rising window signal of a predetermined width every time the time from falling to rising edge passes, and a plurality of known rising edges included in the synchronizing signal are synchronized with the output of the rising edge detecting means. A falling window generating means generates a falling window signal of a predetermined width every time a period of time elapses, and the falling window signal is set to a predetermined level by the output of the falling detecting means and reset by the output of the rising detecting means to become a synchronizing signal. and set/reset means for outputting a corresponding reproduction synchronization signal.

<Function> A synchronizing signal is input and each fall (or rise) is detected by a fall (or rise) detection means,
The same is true in synchronization with the output of these detection means! A rising (or falling) window generating means generates a rising (or falling) window signal of a predetermined width every time a plurality of known times from falling to rising (or vice versa) included in the I signal elapse. When this happens, the rising (or falling) detection means is operated only when this rising (or falling) window signal is present, and at other times it is masked to remove the noise that mixes between the regular synchronizing signals. , operate the set/reset means using the output of the rising/falling detection means to set M.
To reproduce a silent synchronous signal without time delay.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 7 is a block diagram showing one embodiment of the present invention.

DFFI is a D-type flip-flop, and its data end receives a synchronization signal <SYN> separated from a video signal transmitted from a television camera, etc., and its clock end C receives a system clock SGK. ing. D
The data at the output end Q of the 70-tube flip-flop DFF+ is applied to the data end of the D-type flip-flop DFF2, and the system clock SGK is applied to the clock end C.

The DPC is a falling detection circuit, and is composed of a three-way non-do gate, and its first negative input terminal receives data from the output terminal Q of the D-type flip-flop OFF+, and its positive input terminal receives data from the output terminal Q of the D-type flip-flop 70-tube. The data at the output terminal Q of DFF2 is sent to the second negative input terminal by the falling detection circuit DPG.
A control window signal <WINDOW2> for controlling lJ l is input, respectively. - The UPC is a rising edge detection circuit, and is composed of a three-power Nant gate, whose first negative input terminal receives data from the output terminal Q of the D-type flip 70 tube DFF2, and its positive input terminal receives the data from the output terminal Q of the D-type flip 70 tube. Data at the output terminal Q of the knob OFF+ is input to the second negative input terminal, and a control window signal <WINDOWI> for controlling the rising edge detection circuit UPC is input, respectively.

The output Qd of the falling detection circuit DPC is input to the rising window generation circuit UWC. The wind generation path UWC is
For example, it is composed of an N-pit counter CT and a decoder DCR that decodes its output. The clear input terminal CLR of the counter CT receives the output of the falling detection circuit DPC, the clock terminal C receives the reference clock CK created by dividing the system clock, and the ENP input terminal receives the output from the decoder DCR. The decoded outputs Wa> are respectively input. The N-bit output of the counter CT is input to the decoder DCR, where it is decoded, and decoded outputs are sent to each output terminal.
Output.

These decode outputs kuWo〉, kuW,〉, kuW2〉,
<Wa> is input to the NOR gate G, and a window signal <WINl> is obtained at its output terminal.

G2 is an AND gate, the window signal <WINl> is inputted to its negative input terminal, and the data of the output terminal Q of the set/reset flip 70 tube 5RFI is inputted to its positive input terminal.

G3 is a NOR gate, the data of the output terminal of the AND gate G2 is inputted to its positive input terminal, the reset signal <Re5et> is inputted to its negative input terminal, and the rising wind signal <WINDOWl> is inputted to its output terminal. obtain.

Further, the clear terminal <CLR> of the set/reset flip-flop 5RF1 receives the output of the rising edge detection circuit UPC, and the preset terminal <Pre> thereof receives the output of the falling detection circuit DP.
The outputs of C are respectively applied, and the output obtained at the output terminal Q controls the passage of the rising wind signal <WINDOWl>.

On the other hand, the output Qu of the rising edge detection circuit LJPC is input to the falling window generation circuit DWC. The internal configuration of this falling window generation circuit DWC is the rising window generation circuit U.
Like the WC, it is composed of a counter and a decoder, and its output terminal outputs decoded outputs <Wo->, <W! ->, <W2 ′>
, W3'>, <wn->, and <W5'> are output.

These decode outputs Wo ′, W+ ′, W2-1W
s-1<Wa'>, KuW'> are input to the NOR gate Q4, and a window signal <VIN2> is obtained at its output terminal.

G5 is an AND gate, the window signal <WIN2> is inputted to its negative input terminal, and the data of the output terminal Q of the set/reset flip-flop 5RF2 is inputted to its positive input terminal.

G6 is a NOR gate, and its positive input terminal receives the data at the output terminal of the AND gate G, its negative input terminal receives the reset signal <Re5et>, and its output terminal receives the falling window signal WINDOW2. > get.

In addition, the output of the falling detection circuit DPC is connected to the clear terminal <CLR> of the set/reset flip 70 knob 5RF2.
The preset end <Pre> has a rising edge detection circuit LIP.
The outputs of C are respectively applied and the outputs obtained at the output terminals Q control the passage of the falling window signal <WINDOW2> and obtain the reproduction synchronization signal <R8YN>.

Next, the operation of the circuit shown in FIG. 1 constructed as above will be explained using the waveform diagrams shown in FIGS. 2, 3, and 4. Figure 2 is a waveform diagram explaining the operation of the rising window generating circuit UWC, Figure 3 is a waveform diagram explaining the operation when noise is not included, and Figure 4 is a waveform diagram explaining the operation when noise is included. be.

In the following explanation, other periods ■～■ in FIG.
However, since the same operation is performed, a case will be described in which the falling period of the synchronizing signal <SYN>, particularly the period ■, is detected and the synchronizing signal <SYN> is reproduced.

First, FIG. 3, which shows an operation in which the synchronization signal <SYN> does not include noise, will be described.

A synchronizing signal <SYN> (Fig. 3 (O)) separated from an image signal transmitted from a television camera, etc. is input to the data end of the D-type flip 70-tube DFF+, and the system clock 5GK (Fig. 3 (O)) is input. b)) This synchronizing signal <SYN> is shifted to the D-type flip-flop D.
These D-type flip-flops DF are input to FF2.
The outputs of FI and DFF2 are input to the falling edge detection circuit DPC, so when there is a falling edge of the synchronization signal <SYN>, the falling edge detection circuit DPC detects this falling edge and outputs Qd (third
(C)) is output to the rising window generating circuit UWC, and the set/reset flip 70 knob S'RF2 is cleared to set its output Q to a low level (FIG. 3 (E)).

The rising window generating circuit UWC detects when the output Qd becomes low level, and at the time shown in FIG. 2(A), more precisely, as shown in FIGS. SYN > 1 system clock SCK later)
After a period of time corresponding to the period ■ shown in Figure 5 has elapsed, the second
A decoded output WO> having a predetermined time width Δt shown in FIG. 2B is output to the Nantes gate G1. At the same time, Figure 2 (
C) As shown in (f), the decode outputs <Wl> and <W2> corresponding to the periods ■ and ■ are not output. In addition to this, decoding output <WO
If a rising edge is not detected during any of the periods from <W2> to <W2>, a signal that becomes low level after a certain period of time after the rising edge of the decoded output <W2> is output (see FIG. 2).
to). The <ENP> input of counter 0 is decoded and the W3> is at a low level to stop its counting. As described above, the window signal <WINI> obtained by ORing the decoded outputs <WO> to W2> is outputted to the output terminal of the NOR gate G1, as shown in FIG. 2(d).

On the other hand, the set/reset flip 70 SRF is preset by the fall of the output Qd of the fall detection circuit DPC, and outputs a high level output to its output Q. Therefore, the window signal <W I N 1> is the AND gate G2
A rising wind signal <WINDOWl> having the same waveform as that shown in FIG. 2 (H) or FIG. 3 (D) is obtained at the output of the NOR gate G3. This wind signal <
Since WINDOWl> makes it possible to detect the rise of the synchronization signal <SYN> during its low level period (Δt) or the rising edge detection circuit UPC, it corresponds to the period ■ to ■ after the fall of the synchronization signal <SYN>. The rise detection circuit UPC detects the rise of the synchronization signal <SYN> that matches the passage of time.
is detected as the output Qu, clears the set/reset flip-flop SRF, holds its output at low level, turns off the rising edge detection circuit UPC via AND gate G2 and NOR gate G3, and outputs the set/reset flip-flop. 5RF2 is preset and the level of its output terminal Q is set to high level (Fig. 3 (e)) to generate a reproduction synchronization signal <R8YN> corresponding to the synchronization signal <S'YN>.
Reproduce.

The synchronization signal <R3YN> reproduced as above is
As can be seen from a comparison of FIGS. 3(b) and 3(e), there is a difference of only one system clock, and this slight difference does not substantially cause image deviation.

Note that the reset signal <Re5et> sets the rising window signal <VINDOWl> and the falling window signal <WINDOW2> to a low level when the power is turned on to ensure stability of operation.

Next, the operation when noise is mixed into the synchronization signal <SYN> will be explained using FIG.

In this case, as shown in Figure 4 (b), the synchronization signal < SY
Noise NZ is mixed into N ->. However, this noise NZ is caused by the rise detection circuit because the rising wind signal <WINDOWI> is not located within the predetermined time width Δt of the low level corresponding to the period ■ to ■ as shown in FIG. 4(d). The rising edge is not detected by UPC, so the set/reset flip 70 knob 5RF2 is not preset and does not affect the playback synchronization signal <R8YN> (
Figure 4 (e)).

In the case of the rising period ■ to ■, the same operation as in the case of the falling period is performed.

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the falling detection circuit or the rising detection circuit is masked except for a predetermined period after detecting a rising edge or falling edge. Therefore, even if noise enters the period other than this, it will not affect the playback synchronization signal, and it will be reset or set almost simultaneously with the fall or rise of the synchronization signal.
Since the synchronization signal is set or hit at the rising or falling edge of the synchronization signal to reproduce the synchronization signal, there is almost no difference between the synchronization signal and the reproduced synchronization signal.

As a result, according to the present invention, a reproduction synchronization signal without image shift and from which the influence of noise is removed can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of one embodiment of the present invention, Fig. 2 is a waveform diagram explaining the operation of the rising window generation circuit in Fig. 1, and Fig. 3 shows that noise is not included in the synchronization signal. FIG. 4 is a waveform diagram explaining the operation of the circuit shown in FIG. 1 when the synchronization signal includes noise. FIG. 5 is a waveform diagram of the synchronization signal. FIG. 2 is a waveform diagram illustrating the characteristics of OFF+, DFF2...D type flip 70 knobs, D
PC...Falling detection circuit, UPC...Rising detection circuit, DWC...Falling window generation circuit, UWC...
・Rising window generation circuit, SRF+, 5RF2...
・Set/reset flip 70 knob, CT...Counter, DCR...Decoder, <SYN>...Synchronization signal. <R8YN>...Reproduction synchronization signal, <WINDOWl>
・・・Rising wind signal, ・WINDOW2＞・・
・Falling wind signal. Figure 2

Claims (1)

[Claims] a fall detection means for detecting a fall of the synchronization signal by inputting a synchronization signal included in the video signal and a falling window signal; and a rising edge detection means for detecting the rising edge of the synchronizing signal when a rising window signal is input thereto; a rising window generating means for generating the rising window signal of a predetermined width every time a period of time elapses; Falling window generating means generates the falling window signal of a predetermined width every time time elapses, and the falling window signal is set to a predetermined level by the output of the falling detecting means and reset by the output of the rising detecting means to achieve the synchronization. 1. A synchronization signal reproducing circuit comprising set/reset means for outputting a reproduction synchronization signal corresponding to the signal.