JPH0584717B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a video signal processing device, and in particular to a disk on which a video signal including a line-sequential color difference signal in which two types of color difference signals appear sequentially every horizontal scanning period is recorded. The present invention relates to an apparatus for processing line-sequential color difference signals included in a video signal reproduced from a recording medium.

<Description of Prior Art> Generally, when synchronizing line sequential signals, the type of the line sequential signals must be determined for each horizontal scanning period (H), and when recording or transmitting, the type must be determined. The signal format is such that it can be distinguished in some way. For example, when recording two types of signals with line adaptation, DC component (CD) offset and frequency offset are performed with a 2H cycle, and a flag signal is added with a 2H cycle. However, when determining the type of line sequential signal that has been subjected to these processes using a reproduction system, it is not possible to accurately determine the type due to effects such as dropout and transmission distortion.

The following is an example of a device that reproduces a still image by continuously reproducing a video signal containing a line-sequential color difference signal recorded for one field on a circular recording track on a magnetic sheet and having a DC offset of 2H period as an identification signal. Let me explain.

FIG. 1 is a block diagram showing the main structure of a conventional reproducing apparatus of this type. Also, Figure 2 is Figure 1 a~
g is a waveform diagram showing waveforms at various parts.

In FIG. 1, _t1 is a terminal to which a line-sequential color difference signal obtained from a reproduced video signal is supplied, and _t2 is a terminal to which a horizontal synchronization signal obtained from a reproduced video signal is supplied. Further, 1 is a sample and hold circuit, 2 is an amplifier that amplifies the output of the sample and hold circuit 1, 3 is a comparator that compares the output of the amplifier with a predetermined level, and 4 is a comparator 3.
The horizontal synchronization signal (Fig. 2 d) is used as the data input.
6 is a 1H (63.556 μsec) delay line, and 7 is a second flip-flop triggered by the horizontal synchronizing signal d.
Monomulti, SW that forms the signal as shown in Figure b
When the output signal of DFF4 is high level, SW1's E is connected to A and SW2's F is connected to C. When it is low level, SW1's E is connected to B and SW2's F is connected to C, respectively, and the lines are synchronized. The color difference signals
It will be supplied at t ₃ and t ₄ .

Now, the line-sequential color difference signal consists of red (R)-luminance (Y) and blue (B)-luminance (Y) signals, and R-Y has a higher center level than B-Y and is recorded with a line offset. Suppose that At this time, if R-Y is being reproduced at a certain H level, the signal sampled and held at the falling edge of the output signal b of the monomulti 7 is at a high level during that period. Therefore, the next H
The output signal e of the DFF4 becomes high level. That is, if the output signal of the 1H delay line 6 is R-Y, E of SW1 is connected to A, and the synchronized R-Y is output from the terminal _t3 . Similarly, the synchronized B-Y is output from the terminal _t4 .

However, when obtaining a line simultaneous color difference signal from a line sequential color difference signal with the above configuration, if there is some kind of flaw in the line sequential color difference signal at the sampling timing, such as S/N deterioration due to dropout, it is difficult to obtain a sample with the correct DC offset. You will not be able to get hold results. Therefore, there is a drawback that switching errors occur between SW1 and SW2, and switching between RY and BY becomes reversed. For example, the second
Due to S/N deterioration such as dropout shown by arrow A in the figure, the period shown by B becomes reversed. This becomes very noticeable on the playback screen. For example, if the screen is all blue, a red line will appear on the screen. Particularly in the above-mentioned still image reproducing apparatus, there is a high possibility that S/N deterioration due to dropout or the like will occur in the same H, so that a noticeable line will always appear in the same part.

<Object of the Invention> The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a video signal processing device capable of line-synchronizing line-sequential signals without error even when the S/N ratio is very poor. It is an object.

<Description by Example> The present invention will be described below using an example in which the present invention is applied to the above-mentioned still image reproduction device. FIG. 3 is a timing chart for explaining necessary synchronization control signals prior to explaining this embodiment.

In FIG. 5, a is a reproduced horizontal synchronizing signal, and b is a signal PG synchronized with the rotation of the magnetic sheet, one pulse being obtained in one field. c is PG,
b is waveform-shaped using a horizontal synchronization signal. d is a timing signal formed from the horizontal synchronizing signal a and inverted every H. e is a discrimination signal obtained by reading an identification signal superimposed on a directly reproduced line sequential signal to discriminate the type of line sequential signal. In the diagram
F1 to F4 each represent a field number,
1/2H at the boundary point between F1 field and F2 field
Skew correction is performed, and the RY signal is continuously reproduced over 2H. The phases of the timing signal d and the discrimination signal e become opposite to each other at time t2'. This state is the end of F3 field,
That is, it continues until time t4'. From this point on, the timing signal d and the discrimination signal e become in phase again, and one cycle ends at time t5. That is, in this example, the timing signal d for self-running switching and the discrimination signal for direct readout switching are in opposite phase between times t2' and t4', that is, for two field periods. Therefore, in order to match the phase of the timing signal d with the discrimination signal e, PG,
If we create a timing signal that is inverted every two frames as shown by b and invert the phase of the timing signal d during the period when this timing signal is at a high level, we can obtain a switching signal that is completely in phase with the discrimination signal 1 shown in g. I can get a signal.

This timing signal f and the switching control signal g
FIG. 4 shows a block diagram showing an example of a circuit configuration for obtaining the following.

A line-sequential color difference signal is inputted from a terminal 11 and guided to a sample and hold circuit 12 . Here, the above-mentioned line sequential identification signal is sampled using a signal delayed by a predetermined timing in the mono multivibrator 13 from the reproduced horizontal synchronization signal inputted from the terminal 15, and the level difference is detected in the comparator circuit 14, and the switching is performed. A signal e for use is formed. The horizontal synchronizing signal a inputted from the terminal 15 is further inputted to the inverting circuit 17 through the monomulti 16, where a timing signal d which is inverted every 1H is generated. A signal c synchronized with PG and D is inputted from the terminal 8 and is led to the OR circuit 19 and serves as a reset input for the counter 25. The output of the OR circuit 19 becomes the input of the inverting circuit 20, where a signal is inverted every field, which is further inverted by the OR circuit 20.
1 to an inverting circuit 22. Here, a timing signal that is inverted every two fields is created, and both the timing signal d and the timing signal are input to the exclusive OR circuit 23, and the output thereof becomes the actual line switching control signal g. This line switching control signal g is also led to an exclusive OR circuit 27, and its output is sent to an AND circuit 26.
It is supplied together with the horizontal synchronizing signal a, and the AND circuit 26
The output is the clock input of the counter 25. After counting a predetermined number of clocks supplied from the AND circuit 26, the counter 25 supplies a carry-out signal to the control circuit 24 and the other input terminal of the OR circuit 21. The Q output of the inverting circuit 20 is also input to the control circuit 24 as another input, and based on these two inputs,
The output signal of the control circuit 24 is supplied to the other input terminal of the OR circuit 19.

FIGS. 5 and 6 are timing charts for explaining the operation waveforms of this block diagram, respectively.

Figure 5 C' shows the trailing edge of Figure 3 signal C, with ia and
ib is an output waveform of the inverting circuit 20 representing two types of phases. ₁ and ₂ are the output waveforms of the inversion circuit 22 representing two more types of phases in ia, and ₃ and ₄ are the output waveforms of ib.
It is that in . Now, assuming that ₁ shown in FIG. 5, that is, FIG. 6 ₁ is the output waveform of the inverting circuit 22,
f ₂ , ₃ and ₄ all have a different phase relationship from the correct phase inversion timing signal.

Now, if there is a phase difference between the direct readout discrimination signal e and the switching control signal g output from the exclusive OR circuit 23, the exclusive OR circuit 27 outputs a high level signal for the period of the phase difference. A certain output signal appears. Therefore, a horizontal synchronization signal is obtained as an output signal of the period AND circuit 26, and is counted by the horizontal synchronization period counter 25. When the count reaches a certain fixed number, that is, when it is determined that the phases are different, a carry-out output is obtained from the counter 25, and the output of the inverting circuit 22 is also inverted with this carry-out output. In FIG. 5, j2 _{and 2} ' represent the correction operation when the combination of the outputs of the two inversion circuits 20 and 22 is ia- ₂ , and _j2 means the internal count value of the counter 25. . The counter value increases from time t ₁ due to the phase difference, and a carry-out output is produced at time t ₆ (not shown). At the same time, ₂ ' changes from high level to D-level, and at time _t2 ', it is inverted to high level again as ia falls. After that, the phase becomes normal ₁ .

Next, the phase correction for the combination of ib- ₃ and ib- ₄ will be described. Figure 6 shows this.ia
₋₁ indicates a normal phase as described above.
₃ ′, j ₃ ′, and ib ₃ ′, the solid lines are the original operating waveforms,
The broken lines are the internal value of the operational inverting circuit counter 24 of ₃ (inverting circuit 22) of this embodiment and the operational waveform of similar i (inverting circuit 20). The same applies to ₄ ′, j ₄ and ib ₄ .

To explain from the former point of view, since the phase is the same from time t ₁ to t ₂ ', the counter 25 does not count anything other than an error such as a dropout, and operates from time t ₂ ' to t ₇ . Then, ₃ ' is inverted to high level due to the carry out output at _t7 .
Next, at time t ₃ ′, ib ₃ ′ is reversed to low level, so
₃ ' becomes low level, a phase difference occurs at this point, the counter 25 starts operating, and a carry-out output is generated at time _t8 . At this time, if ib ₃ ' is at low level, if it is controlled to be at high level,
Since ₃ ' is simultaneously at a high level at this time, the phase becomes normal from time _t4 '.

Considering the latter in the same way, the counter 25 is activated due to the difference in phase from time _t1 .
At time _t6 , ₄ ' becomes D-level as a carry-out output. Then, the counter 25 is activated again from t ₂ ' and becomes high level at time t ₇ . At this time
Since ib ₄ ' is inverted at the same time as the carry-out output of the counter 25 and ib ₄ ' is inverted to low level, ib ₄ ' is inverted at time t ₃ '. Through this series of controls, the phase becomes normal after time t ₃ '.

FIG. 7 is a flowchart showing an algorithm for the operation of the control circuit 25. As shown in FIG.

The starting condition is that the motor rotation is stable. k is the number of carry-outs of the counter 25. Check whether there is a carry out in the first field, and check this again in the next field. If there is no carry out in both fields (if the phase is correct from the beginning; ₁ )
If there is no carry-out in the second field (case ₂ ), there is no need to correct the phase of the inverting circuit 20 and the operation continues as it is.
On the other hand, if there is a carry-out output in the second field, it is likely to be determined whether it is the Nth field (N=2 in the example), and the output signal of the inverting circuit 10 is This phase inversion control is performed depending on whether the level is high or low. Now, the phase discontinuity point of the switching-like control signal and PG
Let's consider a case where the timings of the two times do not match ideally. Although this is not so much of a problem in the case of self-recording and playback, the following problems arise when compatibility with other devices is achieved. In other words, there are differences in the characteristics of the detectors that detect the rotation of the magnetic sheet, timing deviations due to errors in their mounting positions, and the fact that the rotation servo is not activated by the PG pin embedded at a small radius point on the magnetic sheet. The control signal phase near the phase discontinuity point may be caused by deviation of the PG on the recording track existing at a large radius position due to It is inverted with respect to the phase of

FIG. 8 explains the malfunction of the switching control signal caused by this PG timing shift. For each alphabet, the solid line is the current operating waveform and the broken line is the waveform when there is no shift in PG, as in FIG. According to this, it can be seen that the phase of the switching signal g during this period from time t ₂ ' to t ₁₀ is inverted with respect to the original phase, and a switching error occurs when line synchronization is performed.

FIG. 9 is a block diagram showing the configuration of the main parts of the device that reflects this idea, and FIG. 10 is its operating waveform diagram. 4 in Figures 9 and 10.
The same numbers and symbols as in the figures and FIG. 5 indicate blocks and operating waveforms having similar functions.

Similar to FIG. 4, the discrimination signal output from the level comparison circuit 14 is
It is also supplied to Retriggerable Kino Multi 29, which has an unstable period of time slightly longer than 1H.
When the switching signal does not invert for a period longer than the horizontal synchronization period, that is, when a phase discontinuity point comes, the output becomes low level from then on. This signal is supplied to the A terminal of the switch circuit 30. Also
Signal C based on PG is sent from terminal 8 to counter 25
In addition, it is also supplied to the B terminal of the switch circuit 30. The output of the switch circuit 30 is input to the inverting circuit 20 through the OR circuit 19, and this Q output is also supplied to the OR circuit 21, the control circuit 24, and the switch circuit 31. The output of the switch circuit 31 is input to the monomulti 32 which has an unstable period of (2 fields - 3H), and the output k of this mono multi 32 is supplied to the mono multi 33, from which 6H
A gate signal l for the period is generated. Here 3H is now
The specific value raised is not limited to 3H, but any value that exceeds the absolute value of PG variation is sufficient. The gate signal l controls the switch circuit 30, and when the gate signal l is low level, it is on the B side, and when it is high level, it is on the A side.
The connection of the switch circuit 30 is switched to the side. The control circuit 34 is the control circuit 24 in FIG.
The function is almost the same, but here, after detecting that i and f are in the correct phase, the switch circuit 31 is turned on at the next falling edge of i, and the monomultis 32 and 33 are activated.

FIG. 12C shows pulses obtained from the horizontal synchronizing signal and PG, and the dashed line is the timing when there is no deviation. The phase with i is normalized in field F1, and at the next pulse C (time _t11 ), the monomulti 32 enters an unstable period, and after the (2V-3H) period at time _t12 , the next Monomulti 23 enters the bH period unstable period. During this time, the switch 20 is switched to the A side, so the discontinuous phase point t ₄ ' of the switching signal
At this point, the output m of the retriggerable monomulti 29 falls, and at the same time, i is inverted, and the monomulti 32 enters the unstable period again. After that, the phase switching of the inverting circuits 20 and 22 is controlled at the discontinuity point seen from the superimposed identification signal, so a reliable switching control signal g for line synchronization can be obtained despite the PG generation deviation. .

However, at the phase discontinuity point of the line-sequential switching control signal, that is, at the connection point between the start point and end point of one circular track, it is impossible to detect the discrimination signal due to the lack of horizontal synchronization signal caused by uneven rotation. Furthermore, since these points are the start and end of the recording gate signal, gate switching noise caused by this is superimposed, resulting in a reduction in S/N. Therefore, even if you try to detect the phase discontinuity point of the switching signal by directly detecting the superimposed discrimination signal in this vicinity, for example at ±3H, it may not be detected at all, or multiple points may be detected. . When such a phenomenon occurs, the phase of the free-running switching signal is either not inverted at all, or even if it is reversed, it is reversed again, making it impossible to obtain a normal line-sequential switching signal.

Therefore, a device as an embodiment of the present invention that also solves these problems will be described below.

FIG. 11 is a block diagram showing the main structure of an apparatus according to an embodiment of the present invention. Components with the same numbers as those in FIG. 9 have similar functions. The control circuit 35 is substantially the same as the control circuit 34, but by directly detecting whether or not a discontinuous point exists from the discrimination signal, the retriggerable monomulti 2
The output of 9 is also input to the control circuit 35. The rest of the configuration is the same as that in FIG. 9, so the explanation will be omitted.

FIG. 12 is a flowchart showing an operation algorithm of the control circuit 35 of FIG. 11.

Similarly to the case shown in FIG. 8, in this embodiment, when the output i of the single-carrier inverting circuit 20Q and the output f of the inverting circuit 22Q reach the normal phase, from that point on, the next falling edge of i, for example, in FIG. From t ₁₁ (at this point, the phase of the switching control signal is discontinuous), the switch circuit 31 is turned on and the monomulti 32 is brought into an unstable state, and when that period (2V-3H) ends, it is turned on again for the next switching. A point of control signal phase discontinuity comes. The control circuit 35 detects the output of the retriggerable monomulti 29 during the ±3H period before and after the pulses C and PG obtained from the above, and counts the number of falling edges, that is, the number of discontinuous points. If this number n is not 1, it is determined that there was no accurate discontinuity point during this period of ±3H due to low S/N or some other reason, and after that there is no discontinuity point. The pulse C is used without detecting continuous points. If n=1, it can be determined that it is a valid discontinuous point that is synchronized with the timing of the recording track during recording.
Thereafter, the phase inversion of the switching control signal is controlled in accordance with this.

According to the above-described configuration, when a line-synchronized control signal is formed using PG, the generation phase of the PG fluctuates, and the S/N of the line-sequential signal near the phase discontinuity point deteriorates. Since the phase of the control signal described above can be reliably inverted even in such a case, it has become possible to always perform good line synchronization.

It is more preferable to perform this operation again when the rotation of the magnetic sheet is disturbed by the magnetic field, or when a long-term dropout occurs in the line-sequential signal, and it is easy to configure it in this way. It can be realized.

<Description of Effects> As explained above, according to the present invention, a video signal processing device can be obtained that can line-synchronize line-sequential color difference signals without malfunction even when the S/N is poor. It is.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the main part configuration of a conventional playback device, Fig. 2 is a waveform diagram showing waveforms of each part in Fig. 1, and Fig. 3 is a timing chart for explaining the synchronization control signal of the embodiment. 4 is a block diagram showing an example of a circuit configuration for obtaining the control signal shown in FIG. 3, FIGS. 5 and 6 are timing charts showing waveforms of various parts in FIG. 4, and FIG. A flowchart showing the operation algorithm of the control circuit in Fig. 4, Fig. 8 a diagram for explaining the influence of PG deviation, and Fig. 9 showing the main part configuration of the device that solved the problem shown in Fig. 8. Block diagram, Figure 10 is Figure 9
a timing chart showing the operation of the device shown in the figure;
FIG. 11 is a block diagram showing the main structure of an apparatus as an embodiment of the present invention, and FIG. 12 is a flowchart showing an operation algorithm of the control circuit in the apparatus shown in FIG. 11 is a terminal to which a line sequential signal is input, 12 is a sample and hold circuit, 13 is a mono multivibrator, 14 is a comparison circuit, 16 is a mono multivibrator, 17, 20, and 22 are each inverting circuits, 25
is a counter, 28 is a control signal output circuit, 3
2 and 33 are mono multivibrators, 34,
35 is a control circuit.

Claims (1)

[Claims] 1. Two types of color difference signals are included in a video signal reproduced from a disk-shaped recording medium on which a video signal including a line-sequential color difference signal that appears sequentially in each horizontal scanning period is recorded. A device for processing a line-sequential color difference signal, which inputs a line-sequential color difference signal included in a video signal reproduced from the disc-shaped recording medium, synchronizes the input line-sequential color difference signal, and processes the two types of line-sequential color difference signals. a synchronizing means for simultaneously outputting the color difference signals; and inputting a first signal that is inverted every horizontal scanning period and a second signal that is inverted at the rotation period of the disc-shaped recording medium, and control signal forming means for forming a control signal for controlling the synchronization operation in the synchronization means using the signal and the second signal; inputting a line sequential color difference signal, and determining the types of two types of color difference signals that appear sequentially in each horizontal scanning period in the input line sequential color difference signal;
a discriminating means for outputting a discriminating signal according to the discriminating result; and during a part of the period determined by the timing at which the second signal is inverted, whether the discriminating signal output from the discriminating means or the second signal is determined. A video signal processing device comprising: phase setting means for setting the phase of the control signal formed by the control signal forming means according to one of the two.