JPS61225922A - Synchronizing signal separation circuit - Google Patents

Abstract

PURPOSE:To obtain an accurate frame synchronizing signal by clearing a frame counter, an synchronization step-out frame counter and a latch circuit synchronously with a frame synchronizing signal. CONSTITUTION:The signal FSPS is latched by a D flip-flop circuit 33 in the timing of the frame synchronizing signal SYNC generated at first after the synchronization step-out signal FSPS is generated and a latch signal LP is outputted from the circuit 33. When the signal LP is generated, the signal SYNC generated at first is outputted from an AND circuit 30, the frame counter 27 is cleared and a window pulse WD is generated. The signal SYNC is generated synchronously with the pulse WD in this case and outputted from the AND circuit 30. Then the signal SYNC in this case is regarded as the normal signal SYNC and the mode is restored to a normal operation state. Thus, the frame synchronizing signal with high reliability is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronization signal separation circuit suitable for use in, for example, an optical compact disc player.

[Technical Background of the Invention] As is well known, in recent years, in the fields of audio equipment, image equipment, etc., information signals have been converted into digital data in order to achieve recording and reproduction with as high density and high fidelity as possible. A digital recording and reproducing system has been developed in which the information signal is converted and recorded on a recording medium such as a disk, and the information signal is read out from the recording medium using a pickup, a head, or the like.

Among these, optical compact disc players, video disc players, and the like, which use discs as recording media, are generally well known as playback systems that read information signals from recording media.

By the way, for example, in an optical compact disc player, data is recorded on the disc using 588 periods (channel bits) of a reference clock signal as 17 frames, and a frame synchronization pattern of 24 channel bits is placed at the beginning of each frame. is provided. and,
When a disc is reproduced, a frame synchronization pattern is detected from a reproduction signal to generate a frame synchronization signal, and based on the frame synchronization signal, for example, the rotational speed of the disc motor is controlled, demodulation reproduction processing, etc. are performed.

FIG. 7 shows a conventional synchronization signal separation circuit for separating a frame synchronization signal from a disc playback signal. That is, numeral 11 in the figure is an input terminal, to which digital data EFMI obtained by level slicing a reproduction signal output from a pickup (not shown) is supplied. In addition, 12 in the figure is an input terminal, which is a system clock generated within the compact disc player (corresponding to the frequency of the channel bits constituting the digital data EF old) P
K is supplied.

The digital data EFHI and system clock PK are then supplied to the frame synchronization pattern detection circuit 13, where a frame synchronization pattern is detected from the digital data EFHI in synchronization with the system clock PK, and a frame synchronization signal 5VNC is generated.

On the other hand, the system clock PK is supplied to the subframe counter 14 and frame counter 15 and counted. When the frame counter 15 counts the system clock PK for about one frame (about 588 channel bits), the gate signal generating circuit 16 mechanically outputs a wind pulse -0 of a predetermined width.

This wind pulse -0 is supplied to an AND circuit 18 via an OR circuit 17. Also, this AND circuit 18
is supplied with the frame synchronization signal 5VNC. Therefore, if the generation timing of the wind pulse WD and the generation timing of the frame synchronization signal 5YNC match, the above-mentioned frame synchronization signal 5YNC is output from the acid circuit 18, and the frame synchronization signal at this time is the regular frame synchronization signal. It is used for various types of control and processing of compact disc players.

Therefore, counting the system clock PK, 1°
When the generation timing of the wind pulse WD mechanically obtained in one frame cycle and the generation timing of the frame synchronization signal 5YNC obtained from the frame synchronization pattern detection circuit 13 match, this frame synchronization signal is It is considered to be data.

Further, the frame synchronization signal 5VNC outputted from the AND circuit 18 is supplied to the frame counter 15 to clear its count value. Therefore, the frame counter 15 counts the system clock PK again, and the wind pulse -0 is repeatedly generated.

On the other hand, each time the frame counter 15 finishes counting one frame, the out-of-synchronization frame counter 1
A pulse signal is generated at 9. This out-of-synchronization frame counter 19 counts the pulse signal, and receives the frame synchronization signal 5YN from the AND circuit 18.
When C is generated, the count value is cleared thereby, so that the count value does not exceed 1 while the frame synchronization signal 5YNC is being generated normally.

Here, if the frame synchronization signal 5VNC cannot be obtained, for example, when the power is turned on or when a burst occurs, etc.
Since the out-of-sync frame counter 19 is no longer cleared, the count value of the out-of-sync frame counter 19 increases.

Then, when the count value of the out-of-synchronization frame counter 19 exceeds a predetermined value, the out-of-synchronization frame counter 19 outputs an out-of-synchronization signal FSPS.
occurs. This out-of-synchronization signal FSPS is supplied to an AND circuit 21 via an OR circuit 20.

Note that this AND circuit 21 receives a frame synchronization signal 5Y output from the frame synchronization pattern detection circuit 13.
NC is supplied.

Here, the subframe counter 14 counts the system clock PK for one frame, so that the gate signal generation circuit 22 generates a subwind pulse 5BWD having a width wider than the wind pulse -D, for example. become. This subframe counter 14 is cleared by the output of the AND circuit 21.

And the above subwind pulse! JJD is supplied to the OR circuit 17 via the AND circuit 23. Note that the AND circuit 23 receives the out-of-synchronization signal FSP.
S is supplied.

Therefore, when the frame synchronization signal 5YNC is generated for the first time after the synchronization loss signal FSPS is generated, the subframe counter 14 is cleared, and the next frame synchronization signal 5YNC coincides with the generation timing of the subwind pulse 5BWD. When the out-of-synchronization frame counter 19 is cleared, the out-of-synchronization signal FSPS
generation is stopped and the original state is restored.

The above operations can be summarized as shown in the flowchart shown in FIG. That is, when the system clock PK is supplied, the subframe counter 14 and the frame counter 15 start counting operations in step S1. Then, in step S2, it is determined whether the gate signal generating circuit 16 generates the wind pulse -0. If the wind pulse -〇 is not generated (No>, the determination operation continues as it is, and if it is generated (YES)
), out-of-synchronization frame counter 19 in step S3.
is +1.

Next, in step S4, it is determined whether the wind pulse -0 and the frame synchronization signal 5YNC are generated at the same time. If they occur at the same time, that is, if they match (YES), the subframe counter 14. The frame counter 15 and the out-of-synchronization frame counter 19 are cleared, and the process returns to step S2.

If they do not match (No>), it is determined in step S6 whether the count value of the out-of-synchronization frame counter 19 is greater than or equal to a predetermined number n or less than n.If it is less than the above n, then ( No> Returned to step S2,
If it is greater than or equal to n (YES), the out-of-synchronization signal FSPS is generated from the out-of-synchronization frame counter 19 in step S7.

Thereafter, in step S8, it is determined whether or not the subwind pulse 5BWD is generated from the gate signal generation circuit 22. If the subwind pulse 5BWD is not generated <No>, the determination operation continues as it is, and if it is generated (YES), it is determined in step S9 whether the subwind pulse 5BWD and the frame synchronization signal 5YNC are generated at the same time. It is determined whether or not. If they do not occur at the same time, that is, if they do not match (N
o>, the discrimination operation continues, and if they match (Y
ES), the process is returned to step S5, and the normal operation is resumed thereafter.

That is, if the above-mentioned means is used, when the frame synchronization signal 5YNe is no longer generated and then is generated again, and when it occurs twice or more and coincides with the generation timing of the wind pulse -0, the frame synchronization signal 5YNe is Sync signal 5YN
Since C is regarded as regular data, an extremely reliable frame synchronization signal can be obtained.

[Problems in the background art] However, in the conventional synchronization signal separation circuit as described above, the frame counter 1 that generates the wind pulse -D
5 and the gate signal generation circuit 16, and the subframe counter 14 and the gate signal generation circuit 22 that generate the subwind pulse 5BWD, the configuration becomes complicated and unsuitable for miniaturization. ), there is a problem that it will be economically disadvantageous.

[Object of the Invention] The present invention has been made in consideration of the above circumstances, and an object thereof is to provide an extremely good synchronization signal separation circuit that has a simple configuration and can contribute to the generation of accurate frame synchronization signals. .

[Summary of the Invention] That is, the synchronization signal separation circuit according to the present invention inputs data in which frames are configured with a predetermined cycle of a reference clock signal and each frame includes a synchronization pattern, and extracts the synchronization pattern from the data. a frame synchronization pattern detection circuit that detects and generates a frame synchronization signal; a frame counter that counts the reference clock signal; a gate signal generation circuit that generates a wind pulse every predetermined count value of the frame counter; a first control circuit that clears the frame counter in a state in which a wind pulse is generated from the gate signal generation circuit and the frame synchronization signal is generated; and a first control circuit that counts the wind pulse output from the gate signal generation circuit; an out-of-sync frame counter that generates an out-of-sync signal when the value reaches a predetermined value; and clearing the out-of-sync frame counter when a wind pulse is generated from the gate signal generation circuit and the frame synchronization signal is generated. and a latch that latches the out-of-sync signal at the timing when the frame-sync signal is first generated from the frame-sync pattern detection circuit in a state where the out-of-sync signal is generated from the out-of-sync frame counter. circuit, and a third control circuit that clears the frame counter in a state where a latch output is generated from the latch circuit and the frame synchronization signal is generated, and the latch signal is output from the latch circuit. In the state, when the generation timings of the frame synchronization signal and the wind pulse do not match, the frame counter is cleared in synchronization with the frame synchronization signal, and when the generation timings of the frame synchronization signal and the wind pulse match, the frame counter is cleared. By clearing the frame counter, the out-of-synchronization frame counter, and the latch circuit in synchronization with the synchronization signal, it is possible to generate a frame synchronization signal accurately with a simple configuration.

[Embodiments of the Invention] Before explaining one embodiment of the invention, the basic configuration of the invention will be explained below. In FIG. 4, 24 is an input terminal to which the digital data EFHI is supplied. Further, numeral 25 in the figure is an input terminal to which the system clock PK is supplied.

The digital data EFHI and system clock PK are then supplied to a frame synchronization pattern detection circuit 26, and a frame synchronization pattern is detected from the digital data EFHI in synchronization with the system clock PK, as shown in FIG. 5(a). A frame synchronization signal 5YNC is generated.

On the other hand, the system clock PK is supplied to the frame counter 27 and counted. When the frame counter 27 counts the system clock PK for about one frame, the gate signal generating circuit 28 mechanically outputs a wind pulse 10 as shown in FIG. 5(b).

This wind pulse -0 is supplied to an AND circuit 30 via an OR circuit 29. Further, the frame synchronization signal S"/He is supplied to the AND circuit 30. Therefore, if the timing of the occurrence of the wind pulse -0 and the timing of the generation of the frame synchronization signal 5YNC match, the AND circuit 30 is supplied with the frame synchronization signal S"/He. As shown in FIG. 5(d), the frame synchronization signal 5VNC is outputted from the circuit 30. Then,
The frame synchronization signal S'/He outputted from the AND circuit 30 at this time is regarded as the regular frame synchronization signal 5VNC.

Further, the frame synchronization signal 5YNC output from the AND circuit 30 is supplied to the frame counter 17 to clear its count value. Therefore, the frame counter 27 counts the system clock PK again, and the wind pulse -D is generated repeatedly.

On the other hand, the above-mentioned wind pulse -0 is supplied to the out-of-synchronization frame counter 31 and also to the AND circuit 32. Note that the AND circuit 32 is supplied with the frame synchronization signal 5YNC.

Here, the period-shifted frame counter 31 counts the number of occurrences of the wind pulse WD, and receives the frame synchronization signal 5Y from the AND circuit 32.
When NC is generated, the count value is cleared thereby, so that the count value does not exceed 1 while the frame synchronization signal 5YNC is normally generated.

Here, if the frame synchronization signal 5YNe cannot be obtained continuously as shown by the X mark in FIG. Because it will no longer be
The count value of the out-of-synchronization frame counter 31 increases.

Then, when the count value reaches a predetermined value (2 in this embodiment) or more, the out-of-synchronization frame counter 31 generates an out-of-synchronization signal FSPS as shown in FIG. 5(C). This out-of-synchronization signal FSPS is output by the OR circuit 29
The signal is supplied to the AND circuit 30 via.

Therefore, when the frame synchronization signal 5YNC is first generated after the out-of-synchronization signal FSPS is generated (time T1), the frame synchronization signal 5YNC is
Since the frame counter 27 is cleared, the wind pulse WD is generated at time T2 after approximately one frame has elapsed.

At this time, if the frame synchronization signal 5YNC generated next to time T1 is not synchronized with the wind pulse -0 generated at time T2, the frame counter 21 is cleared and the wind pulse date occurs again at time T3. will be done. When the frame synchronization signal 5YNC is generated at the timing of the wind pulse WD generated at time T3, the out-of-synchronization frame counter 31 is cleared and the generation of the out-of-synchronization signal FSPS is stopped. be.

The above operations can be summarized as shown in the flowchart shown in FIG. That is, when the system clock PK is supplied, the 7 frame counter 27 starts counting operation in step S1. Then, in step S2, it is determined whether the gate signal generating circuit 28 generates the wind pulse -0. If the wind pulse -0 is not generated (NO), the determination operation continues for 14H; if it is generated (YES), the out-of-synchronization frame counter 31 is incremented by 1 in step S3.

Next, in step S4, it is determined whether the wind pulse WD and the frame synchronization signal 5YNC are generated at the same time. If they occur at the same time, that is, if they match (YES), the frame counter 27 and the out-of-synchronization frame counter 31 are cleared in step S5, and the process returns to step S2.

If they do not match (No>), it is determined in step S6 whether the count value of the out-of-synchronization frame counter 31 is greater than or equal to a predetermined number n or less than n.If it is less than the above n, then ( NO) Return to step S2,
If it is greater than or equal to n (YES), the out-of-synchronization signal FSPS is generated from the out-of-synchronization frame counter 31 in step S7.

Thereafter, in step S8, it is determined whether or not the frame synchronization signal 5YNC has been generated. Frame synchronization signal 5VN
If C is not generated (No>), the determination operation continues as is, and if it is generated (YES), the 7 frame counter 21 is cleared in step S9.

Then, in step 810, it is determined whether the wind pulse WD and the frame synchronization signal 5VNC are generated at the same time. If they do not occur at the same time, that is, if they do not match <No>, the process returns to step S8; if they match (YES), the process returns to step S5.

Therefore, according to the above basic configuration, the same operation as the conventional one can be realized with a simpler configuration than the conventional one, and it is suitable for miniaturization and IC.

By the way, with the means having the above-mentioned basic configuration, when the frame synchronization signal 5VNC is not continuously detected and the synchronization loss signal FSPS is generated, the frame synchronization signal 5VNC is not detected continuously.
The operation of clearing the 7 frame counter 27 and generating the wind pulse WD every time YNC occurs is repeated, and when the generation timing of the wind pulse -0 and the generation timing of the frame synchronization signal 5VNC match, the out-of-synchronization frame counter 31 is cleared. I'm trying to clear it and return to normal.

However, if the frame synchronization signal 5VNC is not detected continuously, this means that, for example, the rotation servo system of the disk motor is in a very unstable state, so the frame synchronization signal 5YN generated at this time is
C is extremely unreliable. If the frame counter 21 is cleared using this unreliable frame synchronization signal 5YNC, the frame counter 21 may be cleared more than necessary. An inconvenience arises in that the number increases.

Therefore, one embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, the same parts as in FIG. 4 are indicated by the same symbols, and only the different parts will be explained here. That is, the out-of-sync signal FSPS output from the out-of-sync frame counter 31
is supplied to the input end of the 091779777077 circuit (hereinafter referred to as DFF circuit) 33.

Further, the latch signal LP generated from the output DWtQ of this DFF circuit 33 is supplied to the OR circuit 29.

Furthermore, the frame synchronization signal 5VNC1 output from the frame synchronization pattern detection circuit 26 and the frame synchronization signal 5YNC output from the AND circuit 32 are supplied to the clock input terminal CK and clear terminal CL of the DFF circuit 33, respectively. It is done like this.

The operation of the above configuration will be described below with reference to the timing diagram shown in FIG.

First, in the normal state shown before time T4 in FIG.
The second signal output from the frame synchronization pattern detection circuit 26
Since the frame synchronization signal 5YNe as shown in FIG. As shown in FIG. 2(e), a frame synchronization signal 5VNC is output, and the frame synchronization signal 5VNC at this time is regarded as a regular frame synchronization signal 5VNC.

Assume that after time T4, the frame synchronization signal 5VNC is not detected continuously, as indicated by the X mark in FIG. 2(a). Then, the out-of-sync frame counter 3
1 counts the wind pulses -〇, and when the count value exceeds a predetermined number (in this case 2),
As shown in , the out-of-synchronization signal FSPS is generated.

Here, the frame synchronization signal 5 is generated first (at time T5) after the synchronization loss signal FSPS is generated.
At the timing of YNC, the desynchronization signal FSPS is latched in the DFF circuit 33, and the second signal is output from the DFF circuit 33.
As shown in Figure (d), a latch signal LP is output.

Then, when the latch signal LP is generated, first (
The frame synchronization signal 5YNC generated at time T6) is output from the AND circuit 30, and the frame synchronization signal 5YNC is output from the frame counter 21.
will be cleared. Therefore, the wind pulse -D is generated at time T7, and in synchronization with the wind pulse -0 at this time, the frame synchronization signal 5YN
When C is generated, the frame synchronization signal 5YNC is outputted from the AND circuit 30.

Then, the frame synchronization signal 5YNC at this time is regarded as a regular frame synchronization signal 5YNC, and the normal operating state is returned thereafter.

Therefore, according to the configuration of the above embodiment, after the frame synchronization signal 5VNC is not detected continuously and the out-of-synchronization signal FSPS is generated, the frame synchronization signal 5YNe that is generated first is ignored, and the frame synchronization signal 5YNe that is generated first is ignored. Since the frame counter 27 is cleared by the frame synchronization signal 5YNC that is generated next, the wind pulse is generated based on the unreliable frame synchronization signal 5VNC that is generated first after the out-of-synchronization signal FSPS is generated. - It is not necessary to generate 〇, and data can be reproduced accurately and reliably.

FIG. 3 shows a modification of the above embodiment. That is, this uses an n-bit shift register 34 instead of the DFF circuit 33.

In this way, after the frame synchronization signal 5YNC is not detected continuously and the out-of-synchronization signal FSPS is generated, n frame synchronization signals 5VNe are ignored, and the frame synchronization signal 5VNC generated thereafter is 7 frame counter 27 can be cleared, and a more reliable frame synchronization signal 5YNC can be obtained.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effect of the invention] Therefore, as detailed above, according to the invention,
It is possible to provide an extremely good synchronization signal separation circuit that has a simple configuration and can contribute to the generation of accurate frame synchronization signals.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the synchronization signal separation circuit according to the present invention, FIG. M2 is a timing diagram for explaining the operation of the embodiment, and FIG. 3 shows a modification of the embodiment. 4 is a block diagram showing the basic configuration of the present invention; FIGS. 5 and 6 are timing diagrams and flow charts for explaining the operation of the basic configuration; FIGS. 7 and 8 1A and 1B are a block diagram showing a conventional synchronizing signal separation circuit and a flowchart for explaining its operation, respectively. 11, 12...Input terminal, 13...Frame synchronization pattern detection circuit, 14...Subframe counter, 1
5... Frame counter, 16... Gate signal generation circuit, 17-... OR circuit, 18... AND circuit, 1
9... Out of synchronization frame counter, 20... OR circuit, 21... AND circuit, 22-... gate signal generation circuit, 23... AND circuit, 24.25... input terminal, 26... ...Frame synchronization pattern detection circuit, 27
... Frame counter, 28... Gate signal generation circuit, 29... OR circuit, 30... AND circuit, 31
...Out-of-synchronization frame counter, 32...AND circuit, 33...DFF circuit, 34...shift register. Applicant's representative Patent attorney Takehiko Suzue Drawing IF (no change in content) Figure 1 Figure 6 Figure 8I! i

Claims (1)

[Claims] a frame synchronization pattern detection circuit configured to input data in which a frame is constituted by a predetermined period of a reference clock signal and each frame includes a synchronization pattern, detect the synchronization pattern from the data and generate a frame synchronization signal; A frame counter that counts a reference clock signal, a gate signal generation circuit that generates a window pulse every predetermined count value of the frame counter, and a window pulse generated by the gate signal generation circuit and the frame synchronization signal generated. a first control circuit that clears the frame counter in a state in which the frame counter is set; and an out-of-synchronization circuit that counts wind pulses output from the gate signal generation circuit and generates an out-of-synchronization signal when the count value reaches a predetermined value a frame counter; a second control circuit that clears the out-of-synchronization frame counter in a state in which a window pulse is generated from the gate signal generation circuit and the frame synchronization signal is generated; and an out-of-synchronization signal from the out-of-synchronization frame counter; a latch circuit that latches the out-of-synchronization signal at the timing when the frame synchronization signal is first generated from the frame synchronization pattern detection circuit in a state in which a latch output is generated from the latch circuit; a third control circuit that clears the frame counter in a state in which the frame synchronization signal and the wind pulse are generated, and in a state in which the latch signal is output from the latch circuit, the generation timings of the frame synchronization signal and the wind pulse do not match. When the frame counter is cleared in synchronization with the frame synchronization signal, and when the generation timing of the frame synchronization signal and the window pulse coincide, the frame counter, the out-of-synchronization frame counter, and the latch circuit are synchronized with the frame synchronization signal. A synchronous signal separation circuit characterized in that it clears the synchronous signal.