JPH04255171A - Reference signal generating circuit - Google Patents

Abstract

PURPOSE:To prevent any hunting when a vertical synchronizing signal is missing and to prevent large discontinuity from being caused in a reference signal even when discontinuity is caused in the vertical synchronizing signal when the reference signal synchronously with the vertical synchronizing signal is generated. CONSTITUTION:A frame period data is set to a counter 4 counting a clock signal and the counter is controlled by a vertical synchronizing signal to obtain a reference signal of a frame period synchronously with the vertical synchronizing signal from the counter 4. When a shift register 9 detects missing of the vertical synchronizing signal, the reference signal of the frame period is obtained from the counter 4. When a shift register 13 detects discontinuity of the vertical synchronizing signal, a period data setting means 7 sets a period data slightly different from the frame period to the counter 4 to obtain the reference signal of the period from the counter 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference signal generating circuit that can be used in a servo circuit in a video tape recorder or the like.

0002

2. Description of the Related Art A reference signal generating circuit disclosed in Japanese Patent Application Laid-Open No. 2-177681 is provided with a compensation function when a vertical synchronizing signal is lost, and the outline thereof is as follows. The reference signal generation circuit includes a reference counter that counts clock signals, and is configured to output a pulse every time a predetermined number of clocks are counted, thereby oscillating a reference signal with a predetermined period. The oscillation period of this reference signal generation circuit is set to a period slightly longer than the field period, and if a regular vertical synchronization signal is detected, a reference signal is output in response to this vertical synchronization signal, and vertical synchronization is performed. If a signal is lost singly, an oscillation output set to a cycle slightly longer than the field cycle is output as a compensation signal. Further, when the vertical synchronization signal is continuously lost, the oscillation period of the reference signal generation circuit is set to the field period, and the oscillation period output is outputted as a compensation signal.

[0003] In such a configuration, when the vertical synchronization signal is singly lost, the period of the compensation signal is slightly longer than the normal period, so when the vertical synchronization signal is singly lost, the compensation signal is output from the reference signal generation circuit. Hunting will occur in the reference signal (see FIG. 6).

On the other hand, the reference counter constituting the reference signal generation circuit is configured to be controlled (preset to a predetermined value) by one of two vertical synchronization signals that appear in one frame, and is configured to oscillate at the frame period. There is also a way to do this. In this case, the oscillation period of the reference signal created by the reference signal creation circuit matches the frame period, so if the vertical synchronization signal is lost once, if this oscillation signal is output as a compensation signal, Hunting as described above does not occur.

However, since this method is a system in which presetting is performed at a frame period, it is necessary to set a large detection window width for the vertical synchronizing signal for presetting. That is,
If the compensation signal is output when the vertical synchronization signal is missing, and the vertical synchronization signal appears normally after that,
It is necessary to bring into a synchronized state so that a signal synchronized with this vertical synchronization signal is used as a reference signal, but for this purpose it is necessary to set the detection window width to one field or more. However, with such a configuration, as shown in FIG. 7, if the vertical synchronization signal becomes discontinuous, the continuity of the reference signal will be greatly disrupted.

[0006]

[Problems to be Solved by the Invention] Therefore, it is an object of the present invention to prevent hunting of the reference signal from occurring even when a drop occurs in the vertical synchronizing signal in a weak electric field state, and to prevent the vertical synchronizing signal from becoming discontinuous. This is to prevent large discontinuities from occurring in the reference signal even when

[0007]

[Means for Solving the Problem] By having a reference counter that counts clock signals and controlling the counting operation of the reference counter using a vertical synchronization signal within a predetermined detection window,
In a reference signal generation circuit configured to obtain a reference signal synchronized with a vertical synchronization signal from a reference counter, cycle data setting sets the cycle of the reference signal output from the reference counter to a frame cycle or a cycle slightly different from this frame cycle. and a discontinuity detecting means for detecting a discontinuity in the vertical synchronization signal that is present but not within a detection window.

In a normal state, the period data setting means sets the frame period data for the reference counter, and when the loss detection means detects a loss of the vertical synchronization signal, the reference signal of the frame period is obtained from the reference counter.

When the discontinuity detecting means detects discontinuity in the vertical synchronizing signal, the period data setting means sets period data for the reference counter that is slightly different from the frame period, and the period data that is slightly different from the frame period is determined by the reference counter. The configuration is such that a reference signal with a period of

0010

[Operation] In the normal state, frame period data is set for the reference counter, and since the reference counter is controlled by the vertical synchronization signal, a reference signal with a frame period synchronized with the vertical synchronization signal is obtained as its output. It will be done. In addition, if the vertical synchronization signal is simply lost, since the frame period data is set for the reference counter, the reference signal of the frame period can also be obtained as its output. Even if the vertical synchronization signal is missing consecutively, the frame period data is set for the reference counter, so the frame period reference signal can be obtained as its output.

[0011] When the vertical synchronization signal becomes discontinuous,
Period data slightly different from the frame period is set for the reference counter, and a reference signal having a period slightly different from the frame period can be obtained. Since the period of the reference signal output from the reference counter is a signal with a period slightly different from the frame period, even if the detection window of the vertical synchronization signal created based on the count value of this reference counter is narrow, this A vertical synchronization signal can be placed within the detection window. That is, it is possible to pull into a synchronized state.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of a reference signal generation circuit according to the present invention. The composite synchronization signal is input to a vertical synchronization signal separation circuit 1, where the vertical synchronization signal is separated. The separated vertical synchronization signal is input to a vertical synchronization signal counter 2 that counts the number of vertical synchronization signals, and is also applied to a reference counter 4 via an AND gate 3. The reference counter 4 counts the clock signal and counts the clock signal to a predetermined value (for example, 100
) is outputted every time a pulse is counted to return to the initial value 0, but when the above-mentioned vertical synchronization signal is applied, it is controlled to be preset to a predetermined value (for example, 50). Such a preset occurs only for one of the two vertical synchronization signals that occur during one frame period. That is, the decoder 5 outputs its output S during the period when the reference counter 4 is counting a predetermined value (for example, 45 to 55).
1 becomes a high level, and this high level signal is applied to the AND gate 3 through the AND gate 6. Therefore,
The reference counter 4 is preset to a predetermined value by the vertical synchronization signal generated during the period when this high level signal exists. Therefore, the decoder 5 serves as a detection window setting means for the vertical synchronization signal. In this example, the detection window is plus or minus 5 percent of the frame period. The period from 0 to 50 counted by the reference counter 4 corresponds to the period of the vertical synchronization signal, and is 0.
The period from 1 to 100 corresponds to the frame period.

In this way, the pulses output from the reference counter 4 are synchronized with the vertical synchronizing signal, and thus the reference counter 4 can obtain a reference signal with a frame period synchronized with the vertical synchronizing signal.

The predetermined value 100 is set by the period data setting means 7, and the period data setting means 7 sets the predetermined value, for example, 102 (a value slightly different from 100 corresponding to the frame period). can also be set, but this will be discussed later.

The vertical synchronization signal counter 2 counts the number of vertical synchronization signals generated in each frame period. A comparator 8 determines whether or not this count value is 2. If it is 2, the output of the comparator 8 becomes high level, and this output is applied to a 4-bit shift register 9. This register 9 detects that the vertical synchronization signal is continuously missing by a predetermined value 8. The reference signal output from the reference counter 4 is used as a clock input, and the high level output of the comparator 8 is used as a clock input. Entered as data input.

In a normal state (a state in which a vertical synchronizing signal is normally generated), the contents of the 4-bit shift register 9 are all "1", and all of its outputs are at a high level. Therefore, the flip-flop circuit 11 is in the set state due to the high level output of the gate 10. Therefore, the output of the flip-flop circuit 11 is at a high level, and since this is applied to the AND gate 6, the detection window set by the decoder 5 is in an open state.

[0017] When eight vertical synchronization signals are lost in succession,
The contents of the shift register 9 are all 0, all of its outputs are low level, and the output of the gate 12 is high level. This high level output resets the flip-flop circuit 11 so that its output becomes low level, and the AND gate 6 is closed, thereby closing the detection window.

On the other hand, the state of the 4-bit shift register 13 in the normal state is as follows. This register 1
3 detects a state in which the vertical synchronizing signal exists but is not within the detection window (discontinuous state). In the normal state (the state where the vertical synchronization signal is within the detection window), AND gate 3
Since the preset signal output from the decoder 5 is applied to the decoder 5, the decoder 5 is reset by this signal, so that the output S2 of the decoder 5 becomes a low level (0). Output S2 is sent to shift register 1 via AND gate 16.
3 is applied as data. Therefore, this data 0 is sequentially taken into the shift register 13 by the reference signal (clock signal to the shift register 13) outputted from the reference counter 4, and the contents thereof are all zero. Therefore, the output of the AND gate 14 is at a low level, and depending on the low level output state of the AND gate 14, the periodic data setting means 7 sets a predetermined value of 100 (
A value corresponding to the frame period) is set in the reference counter 4.

If no vertical synchronization signal occurs within the detection window, the output S2 of the decoder 5 becomes high level. This high level output S2 is applied to the shift register 13 via the AND gate 16 and taken into the shift register 13 as data 1.

Now, when the vertical synchronization signal becomes discontinuous over four frames, the contents of the shift register 13 become all 1, and at this time, the output of the AND gate 14 is inverted from low level to high level, and this In response to this, the periodic data setting means 7 sets the predetermined value 102 to the reference counter 4.

Next, the operation will be explained with reference to the operation waveform diagrams shown in FIGS. 2 to 5. The state shown in FIG. 2 is a normal state (a state in which a vertical synchronization signal is generated within the detection window), and at this time, the reference counter 4 is set to a predetermined value of 50 every time a vertical synchronization signal occurs within the detection window. It is preset and outputs a pulse (reference signal) every time a predetermined value of 100 is counted. Further, the contents of the shift register 9 are all 1's, and the contents of the shift register 13 are all 0's.

[0022] If the vertical synchronization signal is lost once, the reference counter 4 will not be preset, but the cycle of the reference signal obtained from the reference counter remains the same as the frame cycle. That is, in response to a single drop in the vertical synchronization signal, part of the contents of the shift register 9 becomes 0.
Therefore, part of the contents of the shift register 13 becomes 1, but the states of the flip-flop circuit 11 and the AND gate 14 do not change in response. Therefore, the detection window remains open, and the periodic data setting means 7 continues to set the predetermined value 100.

FIG. 3 shows a case where eight vertical synchronization signals are lost in succession. At this time, the contents of the shift register 9 are all 0, the flip-flop circuit 11 is reset by the output of the gate 12 and its output becomes low level, the AND gate 6 is closed, and the detection window is closed. Considering the state of the shift register 13 at this time, since the clock signal applied to the shift register 13 is slightly delayed by the delay circuit 17 with respect to the clock signal applied to the shift register 9, all contents of the shift register 13 are It will never be 1. That is, since the detection window is closed immediately before the clock signal is applied to the shift register 13, the AND gate 16 is closed, and therefore the data taken into the shift register 13 at this time is not 1 but 0. Therefore, the periodic data setting means 7
continues to set the predetermined value 100 as usual. In this manner, after it is detected that eight consecutive vertical synchronization signals are missing, the reference counter 4 determines that the frame period reference signal is in a free-running state (not synchronized with the vertical synchronization signal). It will be output in .

FIG. 4 shows an operational waveform diagram when eight vertical synchronization signals are generated in succession in such a free run state. When eight vertical synchronization signals are generated in succession, the contents of the shift register 9 all become 1, and the output of the flip-flop circuit 11 changes to high level. That is, the detection window is opened. The change of the output of the flip-flop circuit 11 to high level is detected by the rise detection circuit 15, and in response, the shift register 1
3 is preset to a predetermined value of 7. That is, the content is 1
It becomes 110. In this state, if the next vertical synchronization signal is not within the detection window, the shift register 13
is fetched, and the contents of the shift register 13 become all 1s. Therefore, the output of the AND gate 14 becomes high level, the period data setting means 7 sets the predetermined value 102 for the counter 4, and the counter 4 enters a synchronous pull-in state in which it outputs a reference signal at a 102% frame period. Become.

In this synchronization pull-in state, the period of the vertical synchronization signal and the period of the reference signal are slightly different, so even if they are initially out of synchronization, the detection set based on the count value of the reference counter 4 It is possible to drive the vertical sync signal within the window.

When the vertical synchronizing signal enters the detection window, the least significant bit of the shift register 13 becomes 0, and the output of the AND gate 12 becomes low level. Then, the periodic data setting means 7 sets the predetermined value 100 to the counter 4, and the normal state is restored.

FIG. 5 is an operational waveform diagram in a state where the vertical synchronizing signal exists but is not within the detection window (discontinuous state). When such a discontinuous state continues for four frames, the contents of the shift register 13 become all 1, and the periodic data setting means 7 sets the predetermined value 102 for the counter 4, and the counter 4 outputs the reference signal at a 102% frame period. It becomes a synchronous pull-in state where it outputs. In this state,
The detection window is open, and if the vertical synchronization signal enters the detection window, the cycle data setting means 7 sets the predetermined value 100 to the counter 4, as in the case described above, and the normal state is restored.

[0028]

According to the present invention, when a vertical synchronization signal is lost, a reference signal having the same frame period as in the normal state can be obtained from the reference counter, and hunting does not occur.

Furthermore, when the vertical synchronization signal becomes discontinuous, a reference signal with a period close to the frame period can be obtained, and large discontinuities do not occur in the reference signal. In this state, the period of the vertical synchronization signal and the period of the reference signal are slightly different, so even if the synchronization is initially out of order, the vertical synchronization signal can be brought into the detection window.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a block diagram of a reference signal generation circuit according to the present invention.

[Figure 2] Operating waveform diagram in normal state

[Figure 3] Operation waveform diagram when vertical synchronization signal is missing

[Figure 4] Operation waveform diagram when re-inputting the vertical synchronization signal

[Figure 5] Operation waveform diagram when vertical synchronization signal is discontinuous

[Figure 6] Operation waveform diagram when the vertical synchronization signal is missing in the conventional circuit

[Figure 7] Operation waveform diagram when the vertical synchronization signal is discontinuous in the conventional circuit

[Explanation of symbols]

4 Reference counter 5 Decoder 7 for setting detection window Periodic data setting means 9 Shift register 13 serving as means for detecting missing vertical synchronizing signal Shift register serving as means for detecting discontinuity of vertical synchronizing signal

Claims (1)

[Claims] 1. A reference counter that counts clock signals, and by controlling the counting operation of the reference counter using a vertical synchronization signal within a predetermined detection window, the reference counter is synchronized with the vertical synchronization signal. a reference signal generating circuit configured to obtain a reference signal with a reference signal output from the reference counter, the reference signal generating circuit comprising: a period data setting means for setting the period of the reference signal outputted from the reference counter to a frame period or a period slightly different from the frame period; and a discontinuity detection means for detecting a discontinuity in the vertical synchronization signal that is present but not within the detection window, and in a normal state. ,
When the cycle data setting means sets frame cycle data for the reference counter and the dropout detection means detects a dropout of the vertical synchronization signal, a reference signal of the frame cycle is obtained from the reference counter and the frame cycle data is set for the reference counter. When the continuity detection means detects discontinuity in the vertical synchronization signal, the period data setting means sets period data for the reference counter that is slightly different from the frame period, and the period data that is slightly different from the frame period is determined by the reference counter. 1. A reference signal generation circuit characterized in that the circuit is configured to obtain a reference signal with a period of .