JP4729189B2 - Horizontal sync separator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a horizontal sync separator, and more specifically, in an apparatus for converting an analog video signal into a digital video signal, a horizontal sync that accurately separates horizontal sync by removing noise from a separated sync component signal including noise. The present invention relates to a sync separator.
[0002]
[Prior art]
Conventionally, there is a method using a monostable multivibrator as a method often used in an analog circuit as a method of masking a noise component other than a horizontal synchronizing signal or an equivalent pulse from a synchronizing component signal separated from a composite video signal. This is a method in which a monostable multivibrator is activated simultaneously with detection of a synchronous component signal, and detection is masked for a certain time after detection. By this method, an equalization pulse arranged at a period of 1 / 2H in a period of 1-3 lines and a period of 7-9 lines in a vertical blanking period or a signal arranged at a period of 1 / 2H in a vertical synchronization pulse period Can be eliminated.
[0003]
In addition, a method of removing a high-frequency noise component or subcarrier component included in the composite video signal by a high cut filter is used.
[0004]
In addition, when the synchronization signal is separated from the composite video signal, a slice technique is used to fix the DC level of the composite video signal. For fixing the DC level, a spier value clamp, a pedestal clamp, or the like of the synchronized portion of the composite video signal is used.
[0005]
[Problems to be solved by the invention]
However, when the S / N ratio of the video signal is deteriorated due to a weak electric field or the like, noise (noise) due to the influence of noise is output as a pulse to a synchronized separation output that is level-discriminated. Since this noise pulse is generated at random, if this drives a monostable multivibrator, the true synchronization signal may be masked depending on the timing of the noise. Alternatively, in the case of a signal with a poor S / N ratio, the operation of level discrimination itself becomes unstable, and the synchronization signal may not be detected. When the sync signal is lost, the mask of the monostable multivibrator due to the detection of the sync signal is not effective. For this reason, there is a problem that it becomes defenseless against noise, and it becomes impossible to detect a more accurate synchronization signal due to masking by noise.
[0006]
FIG. 1 is a diagram for explaining the operation of the above-described conventional example. In this figure, the upper part shows the synchronous component signal separated by level discrimination in positive polarity. An arrow part is a part of a horizontal synchronizing signal, and noise is included between them. In the center, the horizontal sync signal cannot be extracted by the level discrimination circuit. The middle waveform shows the case where the mask signal is driven by the first synchronization signal in this figure. When the mask signal is driven, the output is set to a high level, and is set to a low level after a predetermined period. The high level period is a mask period, and the low level period is a mask release period.
[0007]
In the case of the specifications as described above, it is understood that the mask generation is performed as shown in the middle stage with respect to the upper stage signal, and the mask-controlled signal, that is, the signal output without being masked, is shown in the lower stage. The In this case, a noise component is output in part of the signal output without masking instead of the horizontal synchronization signal. Therefore, the signal interval is not uniform.
[0008]
The present invention has been made in view of such problems, and the object of the present invention is to input a television signal or a video signal and to effectively remove a noise component from a synchronous separation output obtained by level discrimination of the signal. It is an object of the present invention to provide a device that outputs only a horizontal synchronization component having periodicity, that is, a horizontal synchronization separation device.
[0009]
[Means for Solving the Problems]
In order to achieve such an object, the present invention provides a horizontal sync separator, wherein the video signal is A / D converted at a slice level for separating sync components. The first gate means for inputting the separated synchronization component signal obtained by slicing the gate, and the control output for periodically masking the gate of the gate means so that only the specific separated synchronization component signal is outputted from the gate means Mask control means for outputting signals, and signals on the input side and output side of the gate means; The mask control means And a mask period correcting means for generating period correction data of the control output signal by inputting data relating to the period from the above.
[0010]
The invention according to claim 2 is the horizontal sync separator according to claim 1, wherein the video signal that has been A / D converted at the slice level for separating the sync components is sliced and output. Filter means comprising a combination of a first slicing means, an integrating means for integrating one level of the input signal as + α, and the other level as -α, and a second slicing means for slicing the output of the integrating means. And a filter means connected to one or a series for inputting the output of the first slice means, wherein the first gate means inputs the output of the first filter means. .
[0011]
The invention according to claim 3 is the horizontal sync separator according to claim 1 or 2, wherein the mask control means includes a counter for inputting and counting a clock signal having a predetermined frequency, The mask period correction means inputs the value of the counter, Input side of the gate means The counter value is controlled to be changed based on the counter value when the signal is received.
[0012]
The invention according to claim 4 Claim 3 The horizontal synchronization separation apparatus according to claim 1, wherein the mask period correction means includes: Filter means Second gate means for masking the output from the first gate means or the second gate means for a predetermined period of time started by a signal output from the first gate means or the second gate means. The output is controlled to be masked, a correction value is generated according to the output value of the counter when receiving the signal output from the second gate means, and the mask control means is used using this correction value The value of the counter is changed.
[0013]
The invention according to claim 5 is the horizontal synchronization separation device according to claim 3 or 4, further comprising a fixed frequency oscillator, wherein the clock signal of the predetermined frequency is derived from the fixed frequency oscillator. It is output.
[0014]
The invention according to claim 6 is the horizontal sync separator according to claim 3 or 4, wherein the clock signal having the predetermined frequency is phase-locked to the color burst signal of the video signal. It is supplied from a PLL circuit.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
FIG. 2 shows a block diagram of a part of a video processing apparatus to which the present invention is applied, and is a diagram showing an embodiment of a horizontal sync separator. In this figure, a portion denoted by reference numeral 210 is a portion corresponding to the main part of the present invention, and is a noise mask portion. This portion includes a gate 211 that gates a synchronous component signal obtained by level discrimination, a mask control unit 212 that controls the gate 211, and a mask cycle correction unit 213 that corrects the mask cycle of the mask control unit.
[0017]
The input composite video signal (composite television signal or video signal) is fixed to a DC level by a clamp circuit (not shown), and converted into a digital signal by the A / D converter 201 including a synchronous component. The digitally converted input signal is passed through a digital filter to remove high frequency noise and color subcarrier components. The slice circuit 202 performs normal level discrimination and obtains a so-called synchronization signal component signal at its output. When a signal having no noise component and having a specified value is input, the composite synchronization signal itself is obtained at the output of the slice circuit.
[0018]
In this embodiment, as an input condition, a signal from a signal source with poor quality or a signal containing a lot of noise components is allowed. Therefore, in preparation for this, the integration circuit 203 operates as a time constant circuit (a four-terminal circuit having a resistor between the input and output and a capacitor between the ground output terminals) which is an analog circuit for the synchronous component signal obtained by separation. Is entered. The integration circuit 203 removes most of noise components included in the input signal and included in the separated synchronization component signal. The integrating circuit 203 integrates this signal with the period of the synchronization signal component being 1, and the period of not being −1. This integrator is not intended to detect the vertical sync signal, but to remove the narrow pulse noise included in the composite sync signal. Do not enlarge.
The lower limit of integration is 0.
[0019]
The output of this integration circuit is subjected to level discrimination by the second slice circuit 204. Here, the slice level is set to the midpoint between a predetermined upper limit value and lower limit value of the integration circuit. In the slicing unit 204, fine noise included in the output of the slicing unit 202 is removed.
[0020]
FIG. 3 is a diagram illustrating the operations of the integration circuit 203 and the slice unit 204 described above. An input signal 31 represents an input signal of the A / D conversion unit, and a slice output 32 represents an output of the slice unit 202. In order to remove a narrow portion included in the slice output 32, the slice output is integrated as shown in the lower part thereof. The slice output integration signal 33 integrates the input signal as described above within the lower limit value and the upper limit value as described above. The slice circuit slices at the midpoint level of the upper limit value and the lower limit value, and outputs the slice output 32 shown at the lowest level. Thus, by fixing the slice level, the signal delay amount of the output of the slice circuit including the integration circuit can be kept almost constant, and can be kept constant when there is no noise component.
[0021]
The integrating circuit 203 and the slicing unit 204 constitute a filter, and a plurality of these filters can be provided to form a series, which works effectively depending on the allowable input signal quality range.
[0022]
However, although not shown in the figure, noise components may be included even at this stage, and the noise mask unit 210 is provided to extract only the horizontal synchronization signal from these noise components.
[0023]
FIG. 4 is a timing chart for explaining the basic operation of the noise mask unit. The basic operation of the mask signal when the vertical synchronization signal portion of the separation synchronization signal is input is shown. The noise mask unit shown in FIG. 2 forms a feedback circuit. First, the operation in a steady state will be described. (1) When the output signal of the slicing unit 204 is passed without being masked, a period of not masking is provided around the time after one horizontal synchronization period from that time, that is, a mask window is opened.
(2) When there is no output signal in the slice unit 204 during the period when the mask window is opened, a period for opening the mask window is provided again before and after the next one horizontal synchronization period. (3) When the output signal of the slice unit 204 is passed while the mask window is opened, the opened mask window is closed after the passage.
[0024]
The conventional mask signal has been masked for a certain period after detection, but the present invention is characterized in that the mask period and the mask release period are made periodic. This is because the conventional method of prohibiting detection of the synchronization signal for a certain time after the detection of the synchronization signal is particularly vulnerable when the synchronization signal is lost, and particularly when this synchronization signal is lost. The method avoids the vulnerability.
[0025]
In the noise mask unit 210 shown in FIG. 2, the gate 211 is controlled according to the count value of the mask counter 12 in the mask control unit 212 to mask the output signal of the slice unit 204 over a predetermined period, and is repeated periodically. Let the horizontal sync signal pass. The output value of the mask counter 12 is sent to the gate controller 11 to generate a mask window for controlling the gate 211.
[0026]
The mask window represents a signal for closing the gate 211 and masking so that noise does not pass through the gate. Opening the mask window indicates that the output signal of the slice unit 204 input to the gate is opened. It is to pass through.
[0027]
This mask counter counts the clock signal from the fixed frequency oscillator 214 in the embodiment shown in FIG.
[0028]
This fixed frequency oscillator 214 will be described as generating a 13.5 MHz clock when the input video signal is in the NTSC format. In this case, the period of one line is 858 clocks, and the mask counter 12 is configured to return to 0 in the 858 count cycle.
[0029]
When the value of the mask counter is within a preset range, the gate control unit 11 operates to open the mask window in the range of 858−128 = 730 to 857 and 0 to 128, for example. Specifically, when controlling as described above, the mask window is opened when the mask counter is 730, and the mask window is closed when the mask counter is 128. Further, when the output of the gate 211 is input, the gate controller 11 operates to close the mask window with the next control clock. When the mask window is closed by the output of the gate 211, it remains closed until the start timing of the next mask window, that is, the timing when the mask counter becomes 730 next. This operation is to prevent a plurality of pulses from being output from the gate 211 when the mask window is opened.
[0030]
The above operation is the basic operation of the mask control unit. However, in this state, it is confirmed that the horizontal sync signal is received during the mask window is open and the noise component is received during the closed window. It is also assumed that 858 times the clock period for driving the mask counter does not completely coincide with the horizontal synchronization period of the input signal. Further, when the synchronization signal is out of the mask window in the initial state, the synchronization signal cannot be detected forever.
[0031]
Assuming the above case, when such a signal is input, the mask period correction unit detects an error between the signal and the center of the mask window, that is, the zero value of the mask counter. The mask counter of the mask controller is directed so that the position of the mask window is directed to the position of such a signal, which may be a horizontal sync signal, by feeding back to the mask counter. Control to manipulate the value of. In this way, if the signal is a random noise component, it will not be affected much, but if it is a horizontal sync signal that is a periodic signal, such operation will continue for a certain number of times. Therefore, it is possible to operate so that the timing of the horizontal synchronizing signal gradually enters within the period during which the mask window is opened.
[0032]
A specific operation of the mask cycle correction unit will be described below.
[0033]
The mask cycle control unit 213 shown in FIG. 2 includes a gate 21 that inputs the output of the slice unit 204, a feedback (FB) inhibition control unit 22 that inputs the output of the gate 21 and the output of the gate 211 described above, and The mask window error detection unit inputs the output of the gate 21 and the output of the mask counter. When the above-mentioned signal is input, the feedback (FB) prohibition control unit 22 counts the clock signal from the fixed frequency oscillator 212 and masks the gate 21 for a predetermined FB prohibition period, that is, closes it, and outputs a signal. To do. The FB prohibition period is, for example, a period of 730 (= 858−128) clocks.
[0034]
When the FB prohibition period is set as described above, the gate 21 is opened at least after the FB prohibition period. When a signal is output from the slice unit 204 in the opened state, the signal passes through the gate 21 and is sent to the mask window error detection unit. When receiving the signal from the gate 21, the mask window error detecting unit inputs the data value from the mask counter 12 inputted at that time and checks whether it is 429 or less or 429 or more. If the value input at this time is 64, it is 129 or less, so 64/8 = 8. If the value input at this time is 794, since it is 429 or more, it is calculated as 794-858 = −64, and −64 / 8≈−8.
[0035]
Here, the numerical value 1/8 is a coefficient that determines the amount of feedback. The coefficient value of the feedback amount is set to 1/8 when the signal that has passed through the gate 21 is noise. This is a numerical value for reducing the influence. On the other hand, the signal that has passed through the gate 21 is a horizontal synchronization signal. In some cases, it is assumed that the signal is periodic and will be input the next time the gate 21 is opened by the FB prohibition control unit, and the signal is put in the period when the mask window is opened after at least 8 inputs. It is based on the assumption that it can be included. This numerical value is determined in consideration of the randomness of the noise component and the periodicity of the horizontal synchronization signal. Increasing the denominator of the count value makes it more resistant to noise. On the other hand, if the operation fails, the time until the next horizontal synchronization signal is captured becomes longer.
[0036]
FIG. 5 shows the operation of the mask period correction unit described above, where there is no noise, and when there is a phase difference between the center timing of the period during which the mask window is opened and the output of the slice unit 204. Fig. 6 illustrates how the phase difference is reduced. When there is a signal that is output without being masked at a certain first time point, and a signal deviated from the unmasking period of the period extending around the time point after one horizontal synchronization period generated thereby,
6 and 7 show a case where the mask counter 12 is controlled by the mask cycle control unit 213. FIG. 5 shows the former case, where the value that should be 0 is 64, that is, the signal is later than 0 at the center of the mask window. Control the mask counter to delay the start and delay its value by 8. FIG. 6 shows the latter case, where the one that should be zero is 794, that is, the signal has advanced 64 from zero at the center of the mask window, so the mask window starts. The mask counter is controlled so that the value is advanced by eight.
[0037]
FIG. 8 shows an example of the operation of the present embodiment, taking as an example a signal including a case where the level discrimination of the input signal includes a lot of noise components and the horizontal discrimination component level discrimination fails. FIG.
[0038]
In the figure, an input signal 801 as a noise mask unit, 802 indicating the count state of the mask counter, and a gate signal 803 output from the FB prohibition control unit are shown.
[0039]
First, in the example of the leftmost part (1), the input signal is in the period when the mask window of the mask counter 0 points within ± 128 clocks (indicated by the dotted square frame) is open and passes through the gate 211. This is a case where a horizontal synchronizing signal is used. Here, it is assumed that the FB prohibition signal is at a low level and the gate 21 is opened. Therefore, the input signal of (1) is sent to the mask window error detection unit, and when there is a deviation from the zero point of the mask counter, the error is fed back to the mask counter value by the method described above. . At the same time, an FB prohibition signal (high level signal) is sent to the gate 21 by the FB prohibition control, and the gate 21 is closed for the period t.
The example of (2) is a noise signal. During the period when the FB prohibition signal is at the high level, the interference signal (2) is not fed back by the feedback prohibition signal, and is not output from the gate 211 by the mask window.
The example of {circle over (3)} is a noise signal generated after the immediately preceding synchronization signal has been left without being level discriminated. At this time, the prohibition period of the feedback prohibition signal has expired, but it is a period masked by the mask window and is not output from the gate 211. However, since the prohibition period of the feedback prohibition signal expires and the gate 21 is open, feedback control to the mask counter is performed by the input signal (actually a noise signal). However, the feedback coefficient is 1/8, and the timing of the next horizontal synchronization signal does not deviate from the range in which the mask window is opened.
The example of (4) is a signal during a period in which feedback is prohibited by the noise signal shown in (3), and feedback control is not performed. However, the mask window is open and is output from the gate 211 as a horizontal synchronizing signal. Therefore, the signal is sent to the FB prohibition control circuit, and the FB prohibition control unit resets the FB prohibition time at time t.
In the signal (1) after (4), since the inhibition period of the feedback inhibition signal expires and the gate 21 is open, feedback control to the mask counter is performed by the input signal. At the same time, the mask window is open and is output from the gate 211 as a horizontal synchronizing signal.
[0040]
The above description is based on the embodiment of the present invention in which the input signal is the NTSC color television signal and the frequency of the fixed frequency oscillator is 13.5 MHz. However, similar color television other than the NTSC system, such as the PAL system, is used. Is also applicable. Further, instead of the fixed frequency oscillator, it is possible to use a color burst signal of an input signal or a clock signal from an XVCO (voltage controlled crystal oscillator) generated by being locked to a horizontal synchronizing signal. The mask control period, mask window period setting, and period setting for FB prohibition control as described above are not so strict, and since the mask period correction unit is provided, the range of generated frequencies is It will be appreciated that the output of the XVCO (voltage controlled crystal oscillator) described above, which is limited to some extent, can also be used.
[0041]
Further, although the coefficient value of the feedback amount is set to 1/8 in the mask window error correction unit, the present invention is not particularly limited to this numerical value, and the other numerical values described in the embodiment are also the same. . As for the coefficient value of the feedback amount, for example, the coefficient value is increased during the period in which the mask window is open, that is, the period during which the gate 211 is open, and is reduced in other cases. It can be strengthened. The same thing can be realized by reducing the period during which the mask window is opened.
[0042]
In the present invention, since the masking is periodically executed and the mask period correction unit is provided, it is possible to reduce the period during which the mask window is opened.
[0043]
In the above-described embodiment, the noise is reduced together with the filter unit and the mask unit. However, the filter unit removes high-frequency components from noise that cannot be eliminated by the mask unit, particularly noise near the horizontal synchronization signal. On the other hand, it can be said that the mask part aims to remove a wide-range, that is, low-frequency component noise, especially random noise, which cannot be removed by the filter part and is far from the synchronization signal.
[0044]
The output of the gate 211 of the noise mask unit 210 is sent to the horizontal coordinate generation unit, and a signal for correcting the phase of the horizontal coordinate generation unit, that is, a signal that has a predetermined phase relationship with the input signal phase. , And is usually used. There are various correction methods in this case, depending on how to grasp the signal source of the input signal, whether it is a stable signal source or a signal source that fluctuates like a VTR.
[0045]
【The invention's effect】
As described above, according to the present invention, a random signal having no correlation with the horizontal synchronizing signal such as noise can be removed by a periodically generated mask window. In addition, if a phase difference occurs between the periodically generated mask window and the actual horizontal synchronization signal, the mask that generates the mask window so that the phase difference gradually approaches in the mask period correction unit Since the counter is controlled, the mask window can be generated so as to extract a horizontal synchronizing signal having periodicity while reducing the influence of random noise.
[0046]
Even in the mask period correction unit, even if the phase of the mask window is corrected by noise components, the correction operation is limited to once in about one horizontal operation period. The influence which disturbs the synchronous relationship of the horizontal synchronizing signal of a window can be suppressed small.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a masking operation of a conventional example.
FIG. 2 is a block diagram of a part of a video processing apparatus to which the present invention is applied, and is a diagram illustrating an embodiment of a horizontal sync separator.
FIG. 3 is a diagram for explaining operations of an integration circuit 203 and a slicing unit 204;
FIG. 4 is a timing chart for explaining the basic operation of the noise mask unit.
FIG. 5 shows the operation of the period correction unit, and shows how the phase is gradually reduced when there is a phase difference between the center timing of the period when the mask window is opened and the output of the slice unit 204; FIG.
6 is a diagram showing a case where a mask counter 12 is controlled by a mask cycle control unit 213. FIG.
7 is a diagram showing a case where a mask counter 12 is controlled by a mask cycle control unit 213. FIG.
FIG. 8 shows an example of the operation of the present embodiment, taking as an example a signal that includes a lot of noise components in the signal obtained by level discrimination of the input signal and that includes a case where the level discrimination of the horizontal synchronization component fails FIG.
[Explanation of symbols]
11 Gate controller
12 Mask counter
13 Correction control unit
21 Gate
22 FB prohibition control unit
23 Mask window error detector
201 A / D converter
202 Slice
203 Integration circuit
204 Slice part
210 Noise mask
211 gate
212 Mask control unit
213 Mask period correction unit
214 Fixed Frequency Oscillator

Claims (6)

First gate means for inputting a separated synchronous component signal obtained by slicing a video signal that has been A / D converted at a slice level for separating synchronous components;
A mask control means for outputting a control output signal for periodically masking the gate of the gate means so that only a specific separation synchronization component signal is outputted from the gate means;
A mask period correcting means for inputting the signals on the input side and the output side of the gate means and data relating to the period from the mask control means, and generating period correction data of the control output signal. Horizontal sync separator.   First slice means for slicing and outputting a video signal that has been A / D converted at a slice level for separating synchronous components, and integrating one level of the input signal as + α and the other level as -α Filter means combining an integrating means and a second slicing means for slicing the output of the integrating means, further comprising a filter means connected to one or a series for inputting the output of the first slicing means. 2. The horizontal sync separator according to claim 1, wherein said first gate means inputs an output of said filter means. The mask control means includes a counter that receives and counts a clock signal having a predetermined frequency, and the mask cycle correction means inputs a value of the counter and receives a signal on the input side of the gate means The horizontal sync separator according to claim 1, wherein the counter value is controlled to be changed based on the counter value. The mask period correcting means includes a second gate means for masking the output from the filter means, and is set to a predetermined constant started by a signal output from the first gate means or the second gate means. Control to mask the output of the second gate for a period of time, and generate a correction value according to the output value of the counter when receiving the signal output from the second gate means, 4. The horizontal sync separator according to claim 3, wherein the counter value of the mask control means is changed using a correction value.   5. The horizontal sync separator according to claim 3, further comprising a fixed frequency oscillator, wherein the clock signal having the predetermined frequency is output from the fixed frequency oscillator.   5. The horizontal sync separator according to claim 3, wherein the clock signal having the predetermined frequency is supplied from a PLL circuit phase-locked to a color burst signal of the video signal.

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