JP3106470B2 - PLL circuit - Google Patents

Description

The present invention is used to generate a sampling clock for sampling a video signal supplied to, for example, a multi-scan type video printer every horizontal scanning period. And a suitable PLL circuit.

[Summary of the Invention]

The present invention relates to, for example, a PLL circuit that generates a sampling clock signal for sampling a video signal input to a multi-scan type video printer for each horizontal scanning period.
Detection generated based on the 3/4 horizontal cycle removal signal synchronized with the horizontal synchronization signal for removing the horizontal synchronization signal and the horizontal synchronization signal for detecting the vertical synchronization signal in the video signal A horizontal frequency detection circuit for generating a signal is provided.
Using the 3/4 horizontal synchronization removal signal, remove the horizontal synchronization signal of 1/2 horizontal cycle and compare the horizontal synchronization signal of this phase comparison circuit with the feedback signal of this PLL circuit in this vertical synchronization signal period. By not being done inside,
This is to obtain a stable sampling clock signal.

[Conventional technology]

Generally, multi-scan type video printers require 1
For example, a PLL circuit as shown in FIG. 5 is used to obtain this sampling clock signal for the purpose of always keeping the number of samples in the horizontal period constant. That is, in FIG. 5, (1) indicates a composite synchronization signal input terminal to which a composite synchronization signal separated from a video signal to be printed is supplied, and a composite synchronization signal supplied to the composite synchronization signal input terminal (1). Is supplied to one input terminal of a phase comparison circuit (2), and an error signal obtained at the output side of the phase comparison circuit (2) is supplied to a low-pass filter (3). ) Is supplied to the control terminal of the voltage-controlled variable frequency oscillator (4), and the starting signal obtained at the output side of the voltage-controlled variable frequency oscillator (4) is passed through a predetermined frequency divider (5). The voltage is supplied to the other input terminal of the phase comparison circuit (2) and the sampling clock signal output terminal (6) is derived from the output side of the voltage controlled variable frequency oscillator (4).

According to such a PLL circuit as shown in FIG. 5, it is possible to obtain a sampling clock signal in which the number of samples in one horizontal period is always constant.

[Problems to be solved by the invention]

In such a PLL circuit as shown in FIG. 5, a stable sampling clock signal can be obtained if the horizontal synchronization signal supplied to the composite synchronization signal input terminal (1) is stable.

However, as in a multi-scan type video printer, various composite synchronizing signals, such as a vertical synchronizing signal as shown in FIG. When a signal or the like is supplied and the composite synchronizing signal is supplied directly to the PLL circuit, there is a disadvantage that the sampling clock signal from the PLL circuit is very unstable and unstable. In this case, if the frequency of the sampling clock signal is fixed or the horizontal synchronization signal is constant, the PL
Although the variable width of the voltage-controlled variable frequency oscillator (4) of the L circuit is narrow, the circuit constant can be stabilized, but the variable width of the voltage-controlled variable frequency oscillator used in a multi-scan type video printer is relatively large. Widely, the frequency of the horizontal synchronizing signal is not constant, so that it is very weak against disturbance.

Therefore, as shown in FIG. 6, a horizontal synchronizing signal is obtained by using another PLL circuit (10), and this horizontal synchronizing signal is supplied to one input terminal of the phase comparator circuit (2) of the PLL circuit. Can be considered. That is, a composite synchronizing signal separated from a video signal to be printed supplied to the composite synchronizing signal input terminal (1) is supplied to one input terminal of a phase comparison circuit (7) constituting another PLL circuit (10). An error signal obtained at the output side of the phase comparison circuit (7) is supplied to a control terminal of a voltage-controlled variable frequency oscillator (9) whose free oscillation frequency is a horizontal frequency via a low-pass filter (8). An oscillation signal synchronized with the horizontal synchronization signal of the controllable variable frequency oscillator (9) is supplied to the other input terminal of the phase comparison circuit (7), and the oscillation signal synchronized with the horizontal synchronization signal is obtained as a sampling clock signal. The voltage signal is supplied to one input terminal of a phase comparison circuit (2) of a PLL circuit, and an error signal obtained at the output side of the phase comparison circuit (2) is supplied to a voltage-controlled variable frequency oscillator via a low-pass filter (3). The oscillation signal supplied to the control terminal of (4) and obtained at the output side of the voltage-controlled variable frequency oscillator (4) is supplied to the other input of the phase comparison circuit (2) via a predetermined frequency divider (5). A sampling clock signal output terminal (6) is derived from the output side of the voltage controlled variable frequency oscillator (4) while being supplied to the terminal.

When a horizontal synchronizing signal is obtained by using another PLL circuit (10) as shown in FIG. 6, various composite synchronizing signals are supplied to a multi-scan type video printer. Similarly, the oscillation signal oscillated by the voltage control type variable frequency oscillator (9), that is, the horizontal synchronizing signal is disturbed to generate jitter, and the horizontal synchronizing signal is supplied to the phase comparison circuit (2). (6) There is a disadvantage that the sampling clock signal becomes unstable.

In view of the above, an object of the present invention is to always obtain a stable sampling clock signal.

[Means for solving the problem]

The PLL circuit of the present invention is, for example, a PLL circuit for generating a sampling clock signal for sampling an input video signal every one horizontal scanning period as shown in FIG. Synchronized with this horizontal sync signal to remove the horizontal sync signal of 2 horizontal cycles
The phase comparison circuit is provided with a horizontal frequency detection circuit (11) for generating a removal signal having a 3/4 horizontal period and a detection signal generated based on the horizontal synchronization signal for detecting a vertical synchronization signal in the video signal. Using the 3/4 horizontal synchronizing elimination signal, the horizontal synchronizing signal of the half horizontal cycle is eliminated from the composite synchronizing signal supplied to the circuit (2), and the horizontal synchronizing signal of the phase comparing circuit (2) and the horizontal synchronizing signal are eliminated. The comparison operation with the feedback signal of the PLL circuit is not performed during this vertical synchronization signal period.

[Action]

According to the present invention, the horizontal synchronizing signal of the half horizontal cycle is removed from the horizontal synchronizing signal of the composite synchronizing signal, and the comparison operation between the horizontal synchronizing signal and the feedback signal of the PLL circuit is performed in the vertical synchronizing signal period. When the comparison operation is not performed, the voltage-controlled variable frequency oscillator (4) maintains the previous state, so that a stable sampling clock signal can always be obtained.

〔Example〕

Hereinafter, an embodiment of the PLL circuit of the present invention will be described with reference to FIG. In FIG. 1 and FIG.
The same reference numerals are given to portions corresponding to the drawings, and the detailed description thereof will be omitted.

In this embodiment, the second synchronizing signal input terminal (1) separates the second synchronizing signal input terminal (1) from the video signal to be printed.
A composite synchronizing signal (shown in the negative direction in FIG. 2) as shown in FIG.
1) and are supplied to a half horizontal pulse elimination circuit (12) and a vertical synchronization signal detection circuit (13) for eliminating a horizontal synchronization signal having a 1/2 horizontal cycle such as an equalization pulse. The horizontal frequency detecting circuit (11) detects the frequency of the horizontal synchronizing signal of the composite synchronizing signal, that is, the horizontal period H, and synchronizes with the horizontal synchronizing signal as shown in FIGS.
A pulse of 4H width and a pulse of 3 / 4H width are formed. This half horizontal pulse elimination circuit (12) is a horizontal frequency detection circuit (1
Using the 3 / 4H width pulse from 1) as the gate signal, remove the 1/2 horizontal synchronization pulse such as the equalization pulse of the composite synchronization signal as shown in FIG. 2A as shown in FIG. 2C. It was done. The horizontal synchronizing signal from which the half horizontal synchronizing pulse is removed as shown in FIG. 2C obtained at the output side of the half horizontal pulse removing circuit (12) is supplied to one input terminal of the phase comparator (2). I will do it. The vertical synchronizing signal detecting circuit (13) outputs a composite synchronizing signal as shown in FIG. Or a low-level signal “0”, and the state is maintained until the next determination. The second synchronization signal obtained at the output side of the vertical synchronization signal detection circuit (13) The vertical synchronizing signal as shown in FIG. E is supplied to a control terminal for controlling the operation / non-operation of the phase comparing circuit (2) via the inhibit signal forming circuit (14), and the phase comparing circuit ( 2) is disabled, and the comparison operation is not performed.

The error signal obtained at the output side of the phase comparison circuit (2) is converted into a low-pass filter (3) by a voltage-controlled variable frequency oscillator (4) having a free oscillation frequency of N times the horizontal frequency corresponding to the sampling number N. The output signal of the voltage controlled variable frequency oscillator (4) is supplied to the other input terminal of the phase comparison circuit (2) via a 1 / N frequency divider (5). An output signal of the oscillator (4) is supplied to a sampling clock signal output terminal (6).

Since the present embodiment is configured as described above, of the horizontal synchronizing signal of the composite synchronizing signal supplied to the composite synchronizing signal input terminal (1), the half horizontal pulse is removed by the half horizontal pulse removing circuit (12). The supplied horizontal synchronizing signal is supplied to one input terminal of the phase comparator circuit (2), and the horizontal synchronizing signal is oscillated via a 1 / N divider (5) from a voltage-controlled variable frequency oscillator (4). The signal is compared with a signal by a phase comparator circuit (2) to obtain an error signal, and the phase comparator circuit (2) is disabled during the vertical synchronizing signal period. 4) maintains the previous state, so that a stable sampling clock signal can always be obtained without being affected by a cut pulse or an equalization pulse of 1/2 horizontal synchronization of the vertical synchronization signal. Also, in this example, since the horizontal synchronization number is detected by the horizontal frequency detection circuit (11) and a 1 / 4H width pulse and a 3 / 4H width pulse are formed, various composite synchronization signals are input to the composite synchronization signal input terminal. A stable sampling clock signal can be obtained even when supplied to (1), and when this embodiment is used for a multi-scan type video printer, a print with improved image quality can be obtained.

FIG. 3 shows another embodiment of the present invention. In FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 3, a composite synchronizing signal as shown in FIG. 4A supplied to this composite synchronizing signal input terminal (1) is supplied to one input terminal of a phase comparison circuit (2) and a horizontal frequency detecting circuit ( 11) and the vertical synchronization signal detection circuit (13). This horizontal frequency detection circuit (11)
Generates a pulse of 1 / 4H width as shown in FIG. 2D and supplies it to a vertical synchronizing signal detecting circuit (13). The horizontal frequency detecting circuit (11) generates a pulse of this horizontal frequency. The pulse of the frequency is supplied to the line number counting circuit (15). The vertical synchronizing signal detecting circuit (13) detects a vertical synchronizing signal at the rising edge of a 1 / 4H width pulse signal from the horizontal frequency detecting circuit (11) to obtain a vertical synchronizing signal as shown in FIG. 4B. The vertical synchronizing signal is supplied to an inhibit signal forming circuit (14) and the vertical synchronizing signal is supplied to a line number counting circuit (15). This line count circuit (15) is a horizontal frequency detection circuit (11)
A signal which counts horizontal frequency pulses and becomes a low level "0" during nH for the number of lines where the equalization pulse is eliminated from the beginning of the vertical synchronizing signal as shown in FIG. The inhibit signal forming circuit (1
4) and the pH before the equalization pulse before the next vertical synchronization signal is present, eg, mH until 3 horizontal periods before
The high-level "1" signal is supplied to the inhibit signal forming circuit (14), and the inhibit signal forming circuit (14)
As shown in FIG. 4C, an inhibit signal which includes a vertical synchronizing signal on the output side thereof and disables the period in which the equalizing pulse before and after the vertical synchronizing signal exists is obtained. The inhibit signal obtained at the output side of the inhibit signal forming circuit (14) is supplied to a control terminal for controlling the operation / non-operation of the phase comparison circuit (2). Other configurations are the same as those in FIG.

In the example shown in FIG. 3, the phase comparison circuit (2) is deactivated during the period in which the equalizing pulse including the vertical synchronizing signal exists, and the oscillation state of the voltage controlled variable frequency oscillator (4) is changed during this period. It can be easily understood that the same effect as that of the example shown in FIG. 1 can be obtained because the cause of the disturbance is removed so that the state is maintained.

It goes without saying that the present invention is not limited to the above-described embodiment, and can take various other configurations without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, there is an advantage that a stable sampling clock signal can always be obtained even when various composite synchronization signals are supplied.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the PLL circuit of the present invention, and FIG.
FIG. 3 is a diagram for explaining FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. 4 is a diagram for explaining FIG. 3, FIG. 5 and FIG. It is a block diagram which shows the example of the conventional PLL circuit, respectively. (1) is a composite synchronization signal input terminal, (2) is a phase comparison circuit, (3) is a low-pass filter, (4) is a voltage controlled variable frequency oscillator, (5) is a frequency divider, and (6) is A sampling clock signal output terminal, (11) is a horizontal frequency detection circuit, (12) is a half horizontal pulse removal circuit, (13) is a vertical synchronization signal detection circuit, and (14) is an inhibit signal formation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/937 H04N 1/23-1/31

Claims (1)

(57) [Claims] 1. A PL for generating a sampling clock signal for sampling an input video signal every one horizontal period.
In the L circuit, one of the horizontal synchronization signals in the video signal
A 3/4 horizontal cycle removal signal synchronized with the horizontal synchronization signal for removing a / 2 horizontal cycle horizontal synchronization signal and the horizontal synchronization signal for detecting a vertical synchronization signal in the video signal. A horizontal frequency detection circuit for generating a detection signal to be generated is provided, and a horizontal synchronization signal having a 1/2 horizontal cycle is removed from the composite synchronization signal supplied to the phase comparison circuit using the 3/4 horizontal cycle removal signal. A PLL circuit, wherein a comparison operation between the horizontal synchronization signal of the phase comparison circuit and a feedback signal of the PLL circuit is not performed within the vertical synchronization signal period.