JP2982524B2 - Clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit used to generate a clock synchronized with a reproduced video signal having a time axis fluctuation with respect to a standard format of a video signal.

[0002]

2. Description of the Related Art In recent years, a digital signal processing has been adopted in a time base collector for correcting a time axis fluctuation of a video signal with respect to a standard format of a reproduced video signal of the video signal, and the reproduced video signal is converted into the time axis. A circuit that performs A / D conversion via a clock synchronized with the fluctuation, writes data to the memory using a clock synchronized with the time axis fluctuation, reads data from the memory using a clock synchronized with the standard format, and performs DA conversion. It has become to. FIG. 9 is a block diagram of a clock generation circuit conventionally used to generate a clock synchronized with a time axis fluctuation of a reproduction signal.

In FIG. 9, in the conventional example, a horizontal synchronization detection circuit 22, a phase comparison circuit 23, an edge generation circuit 24, a frequency division counter 25, and an LPF (corresponding to a composite synchronization input terminal 56 and a clock output terminal 57). Low-pass filter)
26, and a VCO (voltage controlled oscillator) 27. A composite synchronizing signal 101 of a video signal input from a composite synchronizing input terminal 56 is input to the horizontal synchronizing detection circuit 22. 10
2 is detected and output. On the other hand, the clock 109 oscillated and output from the VCO 27 is input to the frequency division counter 25, and is divided by the time length of the horizontal line period of the video signal. The output 130 of the frequency division counter 25 is the edge generation circuit 2
4 is converted into a pulse signal 127 synchronized with the rising edge of the output 130 of the frequency division counter 25 and output.

The output 102 of the horizontal synchronization detection circuit 23 and the pulse signal 127 output from the edge generation circuit 24 are input to the phase comparison circuit 23, and the pulse signal 127 rises from the rising edge of the output 102 of the horizontal synchronization detection circuit 23. The pulse signal 12 which becomes "1" level in the period up to the edge and "0" level in other periods
8 is output. The pulse signal 128 output from the phase comparison circuit 23 is input to the LPF 26, converted into a low frequency band voltage 129 of the pulse signal 128 and output, and input to the VCO 27 as a frequency control voltage. In the VCO 27, the oscillation frequency is controlled by the voltage 129, and the output is output as the clock 109 via the clock output terminal 57.

In the conventional clock generation circuit,
The phases of the horizontal synchronizing signal 102 and the pulse signal 127 obtained by dividing the clock 109 output from the VCO 27 into one line are compared, and V so as to match the phase relationship between the two signals.
The oscillation frequency of the CO is controlled. Thus, a clock 109 synchronized with the horizontal synchronizing signal 102 of the input composite synchronizing signal 101 is generated and output.

[0006]

In the above-described conventional clock generation circuit, the synchronization signal 102 of the input reproduced video signal and the clock 10 output from the VCO 27 are used.
The phase of the pulse signal 127 corresponding to the frequency-divided signal 9 is compared, and the frequency of the clock 109 output from the VCO 27 is controlled and adjusted according to the result of the phase comparison. Therefore, the frequency of the clock 109 follows the fluctuation of the time axis of the reproduced video signal, but the phase of the clock 109 has no relation to the horizontal line period of the reproduced video signal.
For this purpose, in the time base collector, the reproduced video signal is A / D-converted by the clock 109 generated in the conventional example, written into the memory, and fixed to a horizontal line cycle synchronized with the standard format of the video signal. Is read from the memory by a reference clock having a phase relationship of
A time-axis variation of up to one clock corresponding to the phase relationship between the horizontal axis and the horizontal line cycle remains uncorrected. Accordingly, when the chroma signal of the video signal is A / D-converted via the clock signal 109, written to the memory, read out via the reference clock, and replaced with a burst signal generated from the reference clock, the video signal of the reference format is used. Has a fixed relationship between the horizontal line cycle and the position and phase of the burst, but has the disadvantage that the color of the video changes because the phase of the read chroma signal remains variable.

Further, in the conventional example, even when the skew occurs (the horizontal synchronization timing becomes longer by one line at the VTR head switching point), the horizontal synchronization signal 102 is used as it is. , VCO2
7 has an effect on the skew during frequency control, and VC
There is a drawback in that accurate frequency control of O27 cannot be performed, thereby hindering improvement in image quality in video equipment.

[0008]

According to the present invention, there is provided a clock generating circuit for generating a clock synchronized with a reproduced video signal of a video signal recording / reproducing apparatus. In response to the input of the value, a horizontal synchronization is performed by removing an excess equivalent pulse (hereinafter abbreviated as H / 2) appearing within one horizontal period included in the vertical retrace period in the composite synchronization signal of the reproduced video signal. A skew and a noise included in the horizontal synchronizing signal in response to an H / 2 killer circuit for outputting a signal and a predetermined reference clock, the horizontal synchronizing signal and the count value, and In this case, a predetermined skew detection signal is output, and when there is no skew or noise, a predetermined clock start signal is output, and If the horizontal synchronization signal is not detected, a skew cancel circuit that outputs a clock start signal at a predetermined skew, a first analog delay circuit that delays the clock start signal for a predetermined time and outputs the clock start signal, and a second analog delay In response to the skew clock start signal, the count value, and the output of the first analog delay circuit, when there is no skew, the output signal of the first analog delay circuit is output as it is, In the case of skew, a control circuit that outputs the skew-time clock start signal as it is,
An output signal of the first analog delay circuit or a clock start signal at the time of skew output from the control circuit, and an output signal of the first analog delay circuit or the clock start signal at the time of skew corresponding to the input of the count value. A distribution circuit that divides a signal into first and second signals at a predetermined timing and outputs the divided signal, and receives a first signal output from the distribution circuit and a predetermined control signal, and oscillates a first clock. A first ringing oscillator for outputting, a second ringing oscillator for oscillating and outputting a second clock in response to the second signal output from the distribution circuit and the control signal, and the first and second ringing oscillators; The first and second signals are output at a predetermined timing in response to the clock and the input of the first and second signals output from the distribution circuit. A scramble circuit that scrambles a second clock and outputs a line-locked clock, and counts the line-locked clock in response to the input of the line-locked clock and the output of the second analog delay circuit; A horizontal counter that outputs the count value corresponding to the horizontal coordinate of the reproduced video signal; and, in response to the input of the skew detection signal and the count value, divides the frequency of the line lock clock through the count value. A frequency dividing circuit that divides and outputs the frequency-divided signal; and a frequency-divided output of the frequency dividing circuit and a horizontal synchronizing signal output from the second analog delay circuit. And a feedback control circuit that outputs the control signal for controlling the oscillation frequency.

The feedback control circuit includes a phase comparator for comparing a frequency-divided output of the frequency divider with a phase of a horizontal synchronization signal output from the second analog delay circuit, and an output from the phase comparator. And a filter circuit for extracting and outputting a low-frequency component of the phase difference signal to be output.
May be formed as a control signal for controlling the oscillation frequency of the ringing oscillator.

The skew cancel circuit includes a first and a second for counting and outputting the reference clock.
And a window generation circuit that receives a count value corresponding to the horizontal coordinate of the reproduced video signal and a count output value of the first counter, and generates an allowable range of skew of the synchronization signal of the reproduced video signal. An edge detection circuit that receives a horizontal synchronization signal and an output of the window generation circuit and detects an edge position of the horizontal synchronization signal, a count output value of the first and second counters,
A control signal generating circuit that receives the edge position output value of the edge detection circuit and the horizontal synchronization signal and outputs the clock start signal, the skew-time clock start signal, and the skew detection signal may be provided.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a reference clock input terminal 51, a composite sync input terminal 5
2, corresponding to the line lock clock output terminal 53,
H / 2 killer circuit 1, skew cancel circuit 2,
Analog delay circuits 3 and 10, control circuit 4, distribution circuit 5, ringing oscillator A6 and ringing oscillator B7, scramble circuit 8, horizontal counter 9, frequency divider circuit 11, feedback control circuit 12,
And is provided. FIG. 3 is a block diagram showing an internal configuration of one embodiment of the feedback control circuit 12, and FIG. 4 is a block diagram showing an internal configuration of one embodiment of the skew cancel circuit 2. The skew canceling circuit 2 is formed by the phase comparing circuit 15 and the filter circuit 16, and includes a counter A1.
7, a counter B18, and a window generation circuit 19
And an edge detection circuit 20 and a control signal generation circuit 21. 5A and 5B.
And (c), FIGS. 6 (a), (b) and (c), FIG.
(A), (b), (c), (d) and (e), and FIGS. 8 (a), (b), (c), (d), (e),
(F) and (g) are timing diagrams of respective signals showing the operation of the present embodiment.

The operation of this embodiment will be described below with reference to FIGS. 1, 3, 4, 5, 6, 7, and 8.

In this embodiment, in a horizontal counter 9 for counting the horizontal position coordinates of an input video signal, a line lock clock 109 output from a scramble circuit 8 described later and an analog delay circuit 3 described later The line lock clock 109 is counted in response to the input of the output 113, and the count output 1
10 is output. The horizontal counter 9 is reset at the timing of the rising of the second clock of the line lock clock 109 after the falling of the output 113 of the analog delay circuit 3 described above. FIG. 5 is a timing chart of resetting in the horizontal counter 9.
(A), (b) and (c). Here, the horizontal position coordinates WH of the video signal immediately before the reset are performed.
(WHMAX is a natural number of 2 or more).

The composite sync signal 101 of the video signal supplied to the composite sync input terminal 52 and the horizontal counter 9
The count output 110 is supplied to the H / 2 killer circuit 1 and the H / 2 pulse and the copy guard signal included during the horizontal synchronization of the composite synchronization signal 101 are deleted, and only the horizontal synchronization signal 102 is extracted. Is output.
For example, assuming that the count value of the count output 110 of the horizontal counter 9 is WH, WH ≧ WC (WC is a natural number of 2 or more, and the falling edge of the composite synchronization signal 101 input during the period of WHMAX / 2 <WC <WHMAX) The pulse is output as valid, and in other cases, the pulse of the code synchronization signal 101 is ignored.

The horizontal synchronizing signal 102 output from the H / 2 killer circuit 1 and the count output 110 of the horizontal counter 9
And the reference clock 117 input from the reference clock input terminal 51 is input to the skew cancel circuit 2. The skew cancel circuit 2 detects the skew and noise of the horizontal synchronization signal 102 output from the H / 2 killer circuit 1, and outputs a skew detection signal 112 and outputs a skew detection signal 112 at the time of skew or noise. When there is no skew or no noise, the clock start signal 111 is output and input to the analog delay circuits 3 and 10. And
If the horizontal synchronization signal 102 cannot be detected within a predetermined period, the skew-time clock start signal 10
3 is output and input to the control circuit 4. Note that the reference clock 117 is a clock synchronized with the standard format of the video signal.

Next, the operation of the skew cancel circuit 2 will be described with reference to FIGS. 4, 6 (a), (b) and (c) and FIGS. 7 (a), (b), (c), (d) and (E)
This will be described with reference to FIG. 4, in the skew cancel circuit 2, the count output 110 of the horizontal counter 9 and the reference clock 117 are supplied to a counter A17. In the counter A17, the count value of the count output 110 is WH, and WH = HMAX (HMAX is It is reset at the rising edge of the reference clock 117 when WHMAX / 2 <HMAX <WHMAX (natural number), the reference clock 117 is counted, and the count output 123 is output. The count output 123 of the counter A17 and the count output 110 of the horizontal counter 9 are supplied to the window generation circuit 19, and the count value of the count output 123 of the counter A17 is obtained from WH = W1 (W1 is a natural number and WHMAX / 2 <W1 <HMAX). , WF = W2 (W2 is a natural number and W2 <WHMAX /
A signal 124 indicating a period up to 2) (hereinafter, this period is referred to as a window period) is output. FIG. 6 (a),
The above window periods are clearly shown in the timing diagrams of (b) and (c).

The output 124 of the window generation circuit 19 and H
The horizontal sync signal 102 output from the / 2 killer circuit 1 is
The signal is supplied to the edge detection circuit 20, and it is determined whether the rising edge and the falling edge of the horizontal synchronization signal 102 are within the window period indicated by the signal 124, and the determination output is output. The judgment output 125 of the edge detection circuit 20 and the reference clock 117 are supplied to the counter B18, where the H / H
The falling edge of the horizontal synchronizing signal 102 output from the 2-killer circuit 1
4, the horizontal synchronizing signal 1
02 is reset at the timing of the fall of 02,
The reference clock 117 is counted from 0 to a predetermined integer value larger than EN (EN is a natural number), and the count output 126 is output. After the counter B18 counts up to a predetermined integer value larger than the natural number EN, its output value is held until reset by the condition.

A count output 126 of the counter B18;
The output 125 of the edge detection circuit 20, the count output 123 of the counter A17, and the count output 110 of the horizontal counter 9 are all supplied to the control signal generation circuit 21, and the count output 126 of the counter B18 and the output of the edge detection circuit 20 are output. In response to the input of 125, a clock start signal 111, a skew detection signal 112, and a skew-time clock start signal 103 are output as described below (see FIG. 7). Horizontal synchronization signal 10 output from H / 2 killer circuit 1
If the falling edge of the clock signal 2 falls within the window period of the output 124 of the window generation circuit 19, the clock start signal 111 and the skew detection signal 112 fall at the falling timing of the horizontal synchronization signal 102. In the same case as above, and when the horizontal synchronizing signal 102 does not rise within a period until the count value WE = EN of the count output 126 of the counter B18,
The count value WH of the count output 110 of the horizontal counter 9
= WA (WA is a natural number of 2 or more, and WA <WHMAX /
At the timing of 2), the clock start signal 11
1 (see FIG. 7A). In the same case as above, when the horizontal synchronizing signal 102 rises during the period up to the count value WE = EN of the count output 126 of the counter B18, it is determined that the horizontal synchronizing signal 102 is noise, and the horizontal synchronizing signal 10
The clock start signal 111 and the skew detection signal 112 rise at the timing of the rising edge of 2 (see FIG. 7B). When the rising edge of the horizontal synchronization signal 102 exists within the window period, it is determined that the horizontal synchronization signal 102 is noise or skew, and the clock start signal 111 and the skew detection signal 112 rise at the rising timing of the horizontal synchronization signal 102. (See FIG. 7C). If the rising edge of the horizontal synchronization signal 102 does not exist within the window period, it is determined that the horizontal synchronization signal 102 is skewed. At the end of the window period, the skew detection signal 112 rises (see FIG. 7D). The count value W of the count output 123 of the counter A17
If the horizontal synchronizing signal 102 does not fall before F = W3 (W3 is a natural number and W3> W2), the skew-time clock start signal 10 at the timing of WF = W3
3 and rises at the count value WH = WA of the count output 110 of the horizontal counter 9 (FIG. 7 (e)).
See).

Next, the operation of the analog delay circuit 3 and the control circuit 4 will be described with reference to FIGS. 8 (a), (b), (c), (d),
This will be described with reference to (e), (f) and (g). Of the signals output from the skew cancel circuit 2, the clock start signal 111 is supplied to the analog delay circuit 3, and only the falling edge of the clock start signal 111 is output as the signal 113 after being delayed by a predetermined time. . Here, the delay time in the analog delay circuit 3 is a period longer than the value of EN counted by the reference clock 117. In the above case, that is, when the falling edge of the horizontal synchronization signal 102 output from the H / 2 killer circuit 1 is within the window period of the output 124 of the window generation circuit 19, and during the period until WE = EN. When the horizontal synchronizing signal 102 rises, the clock start signal 111 output from the control signal generation circuit 21 once falls at the timing of the falling of the horizontal synchronizing signal 102. The horizontal synchronization signal 1
The clock start signal 111 rises again at the timing of the rise of 02 (see FIG. 7). In the analog delay circuit 3 with respect to the horizontal synchronization signal 102 at this time, only the falling edge of the clock start signal 111 is determined by the operation of the control signal generation circuit 21 as noise. In order to delay for a longer time than the pulse width of the clock start signal 111, the pulse of the clock start signal 111 determined to be noise is erased.

The output 113 of the analog delay circuit 3, the count output 110 of the horizontal counter 9, and the skew-time clock start signal 103 among the outputs of the skew cancel circuit 2 are supplied to the control circuit 4, and are output when there is no skew. Is output from the analog delay circuit 3 as it is as the output 104 of the control circuit 4, and when the skew occurs, that is, at the time of the count output WF = W3 of the counter A17 in the skew cancel circuit 2, the H / 2 killer circuit 1 outputs When the output horizontal synchronizing signal 102 is at “H” level, the skew clock start signal 103 output from the skew cancel circuit 2 is output as a signal 104 and input to the distribution circuit 5.

The output 104 of the control circuit 4 and the horizontal counter 9
Is supplied to the distribution circuit 5, and WH = WDIV
(Where WDIV is a natural number and WDIV <WA).
06 is output in a time-division manner. FIG. 8 is a timing chart showing the operation of the distribution circuit 5. Distribution circuit 5
Output 105 and output 11 of feedback control circuit 12
4 (described later) is supplied to a ringing oscillator A6. In ringing oscillator A6, distribution circuit 5
The clock 107 output at the rising timing of the output 105 is stopped, and the output of the clock 107 starts at the falling timing of the output 105. In this case, in the ringing oscillator A6, the output 114 (described later) of the feedback control circuit 12 is temporarily latched and held at the rising timing of the output 105 of the distribution circuit 5, and the level is captured at the next rising timing. Rarely, output 11
The clock 107 having a frequency corresponding to the level 4 is output.

The output 106 of the distribution circuit 5 and the output 114 (described later) of the feedback control circuit 12 are supplied to a ringing oscillator B7. In the ringing oscillator B7, the clock 108 output at the rising timing of the output 106 of the distribution circuit 5 is stopped,
The output of the clock 108 starts at the falling timing of the output 106. In this case, in the ringing oscillator B7, the output 114 (described later) of the feedback control circuit 12 is temporarily latched and held at the rising timing of the output 106 of the distribution circuit 5, and the level is captured at the next rising timing. In rare cases, the clock 108 having a frequency corresponding to the level of the output 114 (described later) is output. FIG. 8 shows an operation timing chart of the ringing oscillator A6 and the ringing oscillator B7.

The clock 107 output from the ringing oscillator A6, the clock 107 output from the ringing oscillator B7, and the outputs 105 and 106 of the distribution circuit 5 are supplied to the scramble circuit 8. In the scramble circuit 8, during the period from the falling edge of the output 105 of the distribution circuit 5 to the falling edge of the output 106 of the distribution circuit 5, the clock 107 output from the ringing oscillator A6 is output as the clock 109, In the period from the falling edge of the output 106 of the distribution circuit 5 to the falling edge of the output 105 of the distribution circuit 5, the ringing oscillator B
7 is output as the line lock clock 109. FIG. 8 shows an operation timing chart of the scramble circuit 8 in this case.

The clock start signal 111 of the output of the skew cancel circuit 2 is the analog delay circuit 1
0, and only after the falling edge of the clock start signal 111 is delayed by a predetermined time, the signal 116
Is output to the feedback control circuit 12. Here, the delay time in the analog delay circuit 10 is determined by the count output EN of the reference clock 117 (FIG. 7).
(See (a))). As in the case of the analog delay circuit 3, in the analog delay circuit 10,
When the skew cancellation circuit 2 determines that the horizontal synchronization signal 102 output from the H / 2 killer circuit 1 is noise having a short pulse width, the horizontal synchronization signal 1
At the timing of the falling edge of the clock signal 02, the clock start signal 111 output from the control signal generation circuit 21 (see FIG. 4) once falls, but is determined to be noise of the horizontal synchronizing signal 102, , The clock start signal 111 rises again (see FIG. 7). In response to the clock start signal 111 at this time, the analog delay circuit 10
Since only the falling edge of 11 is delayed for a time longer than the pulse width of the clock start signal 111, the pulse of the clock start signal 111 determined to be noise is erased.

The counter output 110 of the horizontal counter 9 and the skew detection signal 112 output from the skew cancel circuit 2 are supplied to the frequency dividing circuit 11. When the skew detection signal 112 is at the “L” level (when there is no skew), the frequency divider 11 generates a frequency-divided output 115 obtained by frequency-dividing the line-locked clock by the counter output 110 of the horizontal counter 9. Is output.
When the skew detection signal 112 is at "H" level (during skew), the output of the frequency-divided output 115 of the line lock clock is stopped.

The output 116 of the analog delay circuit 10 and the frequency-divided output 115 of the frequency divider 11 are supplied to the feedback control circuit 12, and as shown in FIG. Dividing circuit 11
Is output to the phase control circuit 15 and the phases of both outputs are compared. Output 12 of phase comparison circuit 15
2 is input to the filter circuit 16, converted into a signal 114 of a low frequency voltage level, and output. The line lock clock 109 output from the scramble circuit 8 is output via the line lock clock output terminal 53.

In this embodiment, the output 1 of the control circuit 4
04 is alternately distributed to two ringing oscillators A6 and B7 in the distribution circuit 5 for each horizontal line of the video signal, and the start and stop timings of the respective ringing oscillators are controlled. It is possible to control the phase of the start point of each horizontal line to be the same as the phase of the reproduced video signal having a time axis fluctuation. For this purpose, the ringing oscillator must be stopped once. However, since the same ringing oscillator is used alternately for stopping and starting the oscillation once every two lines, a continuous clock is generated. When the skew of the composite synchronizing signal 101 of the video signal is detected by the skew cancel circuit 2, the frequency division output 115 output from the frequency division circuit 11 is stopped. At the same time, at the time of skew, since the pulse of the output 116 of the analog delay circuit 10 is also eliminated, the output 122 of the phase comparison circuit 15 in the feedback control circuit 12 is output in a state where the phase difference is zero. Therefore, the feedback control circuit 1
With the output 114 of 2, the output frequency of the ringing oscillator becomes ± 0. Therefore, at the time of skew, the frequency of the ringing oscillator is maintained at the same frequency as that of the previous line, so that the influence of skew is completely eliminated in controlling the frequency of the ringing oscillator.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, in the present embodiment, a reference clock input terminal 51, a composite sync input terminal 52, a line lock clock input terminal 53, a vertical synchronization signal input terminal 54, and a servo feedback signal output terminal 55
In response to this, the H / 2 killer circuit 1, the skew cancel circuit 2, the analog delay circuits 3 and 10, the control circuit 4, the distribution circuit 5, the ringing oscillator A6 and the ringing oscillator B7, and the scramble circuit 8
, A horizontal counter 9, a frequency dividing circuit 11, a feedback control circuit 12, an averaging circuit 13, and a servo control signal generating circuit 14. FIG. 2 is a block diagram showing the internal configuration of one embodiment of the feedback control circuit 12, as in the first embodiment. FIG. 3 is a block diagram showing the internal configuration of one embodiment of the skew cancel circuit 2. The feedback control circuit 12 is formed by a phase comparison circuit 15 and a filter circuit 16, and the skew cancellation circuit 2 includes a counter A17 and a counter B
18, the window generation circuit 19, and the edge detection circuit 2
0 and the control signal generation circuit 21. Note that, similarly to the first embodiment, FIG.
(B) and (c), FIGS. 6 (a), (b) and (c), FIGS. 7 (a), (b), (c), (d) and (e), and FIG. 8 (a) , (B), (c),
(D), (e), (f), and (g) are timing diagrams of respective signals showing the operation of the present embodiment.

The operation of this embodiment will be described below with reference to FIGS. 2, 3, 4, 5, 6, 7, and 8.

The difference between this embodiment and the first embodiment is that an averaging circuit 13 and a servo control signal generation circuit 14 are newly added to the configuration of the first embodiment. . The operation of the circuit components other than the added averaging circuit 13 and servo control signal generation circuit 14 is exactly the same as in the case of the above-described first embodiment. In FIG. 2, the maximum count value 118 of the count output 110 of the horizontal counter 9 and the vertical synchronizing signal 119 input through the vertical synchronizing signal input terminal 54 are supplied to the averaging circuit 13.
In the averaging circuit 13, the average value of the maximum count value 118 supplied for each line is calculated for one field period. This calculation of the average value is reset at the start of the field detected from the vertical synchronization signal 119. Count average value 120 output from averaging circuit 13
Is supplied to the servo control signal generating circuit 14, which calculates the difference from the cloak number of one predetermined line defined by the standard format of the video signal, and outputs the result as the servo control signal 121 via the servo feedback signal output terminal 55. Is done.

In this embodiment, the scramble circuit 8
The horizontal lock 9 is counted by the horizontal counter 9, and the average circuit 13 calculates the average value of the number of clocks per line (the maximum count value of the count output 110) in one field, and calculates the average. By taking the difference between the output count average value 120 and the number of clocks per line defined by the standard format of the video, it is possible to determine whether the line lock clock synchronized with the reproduced video signal is faster or slower than the standard format. Detected and output. The servo system of the VTR (video tape recorder) can be effectively controlled with reference to the servo control signal 121 of the difference output.

[0033]

As described above, the present invention provides an H / 2 killer circuit for removing H / 2 of a synchronization signal of a video signal,
A skew cancel circuit for removing the skew of the synchronization signal, two analog delay circuits for delaying the extracted horizontal synchronization signal for a predetermined time, and a control circuit for generating two signals for controlling the stop and start of the oscillator based on the horizontal synchronization A distribution circuit that distributes two signals output from the control circuit for each line, two ringing oscillators that stop and start once for two lines to adjust the phase of the oscillation output, A scramble circuit that scrambles two clocks output from the ringing oscillator and outputs a line lock clock, a horizontal counter that outputs a count value corresponding to the horizontal coordinate of the video signal, and divides the line lock clock Frequency divider circuit, and the oscillations of the two ringing oscillators By providing at least a feedback control circuit for generating and outputting a control signal for the wave number, there are the following effects as a clock generating circuit.

The phase of the line-locked clock in the video signal can be matched with the horizontal line cycle of the reproduced video signal with relevance, and the time axis can be completely corrected from the starting point of each line. There is an effect that can be.

Further, since the phases of the chroma signals can be completely matched in accordance with the fixed relationship between the horizontal line cycle of the standard format video signal, the burst position and the phase, the color reproduction of the video signal can be accurately performed. This has the effect of being realized.

Further, when the skew of the composite synchronizing signal of the video signal is detected by the skew cancel circuit, the ringing oscillator A and the ringing oscillator B are output via the output of the phase comparison circuit included in the feedback control circuit. Since the oscillation frequency is kept at ± 0, the effect of skew is eliminated in controlling the frequency of the ringing oscillator.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a feedback control circuit in the first and second embodiments.

FIG. 4 is a block diagram showing a skew cancellation circuit in the first and second embodiments.

FIG. 5 is a timing chart showing the operation of the first and second embodiments.

FIG. 6 is a timing chart showing the operation of the first and second embodiments.

FIG. 7 is a timing chart showing the operation of the first and second embodiments.

FIG. 8 is a timing chart showing the operation of the first and second embodiments.

FIG. 9 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 H / 2 killer circuit 2 Skew cancellation circuit 3, 10 Analog delay circuit 4 Control circuit 5 Distribution circuit 6 Ringing oscillator A 7 Ringing oscillator B 8 Scramble circuit 9 Horizontal counter 11 Divider circuit 12 Feedback control circuit 13 Average circuit 14 Servo control Signal generation circuit 15 Phase comparison circuit 16 Filter circuit 17 Counter A 18 Counter B 19 Window generation circuit 20 Edge detection circuit 21 Control signal generation circuit 22 Horizontal synchronization detection circuit 23 Phase comparison circuit 24 Edge generation circuit 25 Divider circuit 26 LPF 27 VCO

Claims (3)

(57) [Claims] 1. A clock generating circuit for generating a clock synchronized with a reproduced video signal of a video signal recording / reproducing apparatus, wherein said reproduced video signal is input in response to input of a composite synchronizing signal of said video signal and a predetermined count value. An H / 2 killer circuit for removing a redundant equivalent pulse (hereinafter abbreviated as H / 2) appearing within one horizontal period included in a vertical retrace period in the composite synchronization signal and outputting a horizontal synchronization signal; In response to the input of the reference clock, the horizontal synchronization signal and the count value, a skew and noise included in the horizontal synchronization signal are detected, and a predetermined skew detection signal is output at the time of skew or in the case of noise. , When there is no skew or noise, outputs a predetermined clock start signal, and when the horizontal synchronization signal is not detected for a predetermined period, A skew cancel circuit that outputs a constant skew clock start signal, a first analog delay circuit and a second analog delay circuit that delay the clock start signal for a predetermined time and output the skew clock start signal, In response to the count value and the output of the first analog delay circuit,
When there is no skew, the control circuit outputs the output signal of the first analog delay circuit as it is, and when there is skew, the control circuit outputs the skew-time clock start signal as it is; In response to the output signal or skew clock start signal of the first analog delay circuit and the input of the count value, the output signal of the first analog delay circuit or the skew clock start signal is output at a predetermined timing. A distribution circuit that divides and outputs the first and second signals, and a first circuit that oscillates and outputs a first clock in response to the first signal output from the distribution circuit and a predetermined control signal.
A second ringing oscillator that oscillates and outputs a second clock in response to a second signal output from the distribution circuit and the control signal, the first and second clocks, A scramble circuit for scrambling the first and second clocks at a predetermined timing in response to the input of the first and second signals output from the distribution circuit and outputting a line-locked clock; A line lock corresponding to an input of a clock and an output of the second analog delay circuit;
A horizontal counter for counting clocks and outputting the count value corresponding to the horizontal coordinate of the reproduced video signal; and responding to the input of the skew detection signal and the count value, A frequency dividing circuit that divides and outputs a clock frequency; and a frequency division output of the frequency dividing circuit and a horizontal synchronization signal output from the second analog delay circuit.
A clock control circuit for outputting the control signal for controlling the oscillation frequency of the first and second ringing oscillators. 2. The phase control circuit according to claim 1, wherein said feedback control circuit compares a divided output of said frequency dividing circuit with a phase of a horizontal synchronizing signal outputted from said second analog delay circuit. And a filter circuit for extracting and outputting a low-frequency component of the phase difference signal to be output. The output of the filter circuit is formed as a control signal for controlling the oscillation frequency of the first and second ringing oscillators. The clock generation circuit according to claim 1. 3. A first and a second counter, wherein the skew cancel circuit counts and outputs the reference clock, a count value corresponding to a horizontal coordinate of the reproduced video signal, and a count of the first counter. A window generation circuit for inputting an output value and generating an allowable range of skew of a synchronization signal of a reproduced video signal, and an input of a horizontal synchronization signal and an output of the window generation circuit to detect an edge position of the horizontal synchronization signal An edge detection circuit,
The count output values of the first and second counters, the edge position output value of the edge detection circuit, and the horizontal synchronization signal are input to output the clock start signal, the skew clock start signal, and the skew detection signal. 2. The clock generation circuit according to claim 1, comprising a control signal generation circuit.