JP2982512B2 - Clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit and, more particularly, to a clock generation circuit of a signal processing device in a video signal recording / reproducing device.

[0002]

2. Description of the Related Art A signal processing apparatus in a conventional video signal recording / reproducing apparatus needs to generate a clock synchronized with a reproduced video signal having a time axis fluctuation with respect to a standard format of the video signal. Circuit is used. As a specific example, there is, for example, a time axis correction device (time base collector).

[0003] A time base collector for correcting the time axis fluctuation of the reproduced video signal with respect to the standard format converts the reproduced video signal into an analog signal with a clock synchronized with the time axis fluctuation.
A circuit that performs D-conversion and writes to the memory with a clock synchronized with the time axis fluctuation and a circuit that reads from the memory with a clock synchronized with the standard format and performs D / A conversion are adopted, and the circuit is synchronized with the time axis fluctuation of the reproduced signal. To generate a clock, a clock generation circuit is used.

FIG. 11 is a block diagram of a clock generation circuit showing an example of such a conventional art. As shown in FIG. 11, a conventional clock generation circuit includes a horizontal synchronization detection circuit 22 that receives a composite synchronization signal CSYNC from a composite synchronization input terminal 27 to detect a horizontal synchronization signal HD, and a horizontal synchronization signal H
D and a phase comparison circuit 23 for comparing the phases of the pulse signal HD2, and a low-pass filter (LPF) 26 which receives an output DH of the phase comparison circuit 23 and outputs a voltage value VDH.
A voltage control oscillator (hereinafter referred to as VCO) 27 which oscillates based on the voltage value VDH and outputs a clock CLK to a clock output terminal 29, a frequency dividing counter 25 which receives the clock CLK of the VCO 27 and divides the frequency, Based on the output DCK of the frequency division counter 25, the pulse signal HD
2 for generating an edge signal.

First, when the composite synchronization signal CSYNC of the video signal input to the composite synchronization input terminal 28 is supplied to the horizontal synchronization detection circuit 22, the horizontal synchronization detection circuit 22 detects the horizontal synchronization signal HD.

On the other hand, the clock CL output from the VCO 27
K is supplied to the frequency division counter 25, and is divided during the period of the horizontal line of the video signal. The output D of the frequency dividing counter 25
CK is supplied to the edge generation circuit 24 and the frequency dividing counter 2
5 is converted into a pulse signal HD2 synchronized with the rising edge of the output DCK.

Next, the horizontal synchronization signal HD detected by the horizontal synchronization detection circuit 22 and the pulse output HD of the edge generation circuit 24 are output.
2 is compared by the phase comparison circuit 23, and outputs a pulse signal DH which is "1" during the period from the rising edge of HD to the rising edge of HD2, and "0" during the other periods.
The output DH of the phase comparison circuit 23 is supplied to the LPF 26, and the pulse signal DH is converted into a voltage value VDH in a low frequency band. When the output VDH of the LPF 26 is supplied to the VCO 27, the VCO 27 generates a clock signal CLK having a frequency corresponding to VDH, and supplies the clock signal CLK to the frequency division counter 25 and the clock output terminal 29.

As described above, the conventional clock generation circuit includes:
The horizontal synchronization signal HD is compared with a pulse signal HD2 obtained by dividing the clock generated by the VCO 27 into one line,
Since the VCO 27 is controlled so that HD and HD2 become the same, a clock synchronized with the horizontal synchronizing signal HD of the input composite synchronizing signal CSYNC can be generated.

[0009]

The conventional clock generation circuit described above compares the horizontal synchronizing signal of the input reproduced video signal with the frequency-divided signal of the clock generated by the VCO, and according to the result, the VCO In order to control the frequency of the generated clock, the frequency of the clock follows the time axis fluctuation of the reproduced video signal, but the phase of the clock is not related to the horizontal line period of the reproduced video signal. For this reason, in the above-described clock generation circuit of the time base collector, when the reproduced video signal is A / D converted by the generated clock and written into the memory, the horizontal line cycle synchronized with the standard format of the video signal has a fixed phase relationship. Read from memory with reference clock
In the case of the A-conversion, there is a disadvantage that it is not possible to correct a time-axis variation of up to one clock corresponding to a phase relationship between a clock and a horizontal line cycle.

The above-mentioned clock generating circuit converts the chroma signal of the video signal from analog to digital with the generated clock and writes it to the memory, and reads out the reference clock and replaces it with a burst signal generated from the reference clock. In this case, since the video signal of the standard format has a fixed relationship between the horizontal line synchronization and the position and phase of the burst, there is a defect that the phase of the read chroma signal remains and the color of the video changes.

Further, the clock generation circuit described above has a VT
Even at the time of skew when the horizontal synchronization timing becomes longer by one line at the time of switching the R head, the horizontal synchronization signal is used as it is, so that the skew effect is exerted on the VCO frequency control, so that accurate frequency control can be realized. There is a disadvantage that there is no.

As described above, the conventional clock generation circuit has the above-mentioned disadvantages, and thus greatly affects the image quality of a reproduced image, which is disadvantageous in improving the image quality of video equipment.

An object of the present invention is to provide a clock generating circuit capable of obtaining a clock synchronized with a horizontal line of such a reproduced image.

[0014]

SUMMARY OF THE INVENTION A clock generation circuit according to the present invention, when generating a clock synchronized with a reproduced video signal in a video signal recording / reproducing apparatus, inputs a composite synchronous signal of the reproduced video signal and outputs the reproduced video signal. An H / 2 killer circuit for removing a half H included in the equivalent pulse of the synchronization signal, a skew cancellation circuit for inputting a reference clock and removing a skew of the synchronization signal, and a part of an output of the skew cancellation circuit. First and second analog delay sections for delaying, a control circuit for controlling a phase of a clock, a ringing oscillator for generating a clock by an output of the control circuit, and the reproduced video signal based on a clock generated by the ringing oscillator A horizontal counter for counting the horizontal coordinates of the And a frequency divider performs frequency division of the click,
A clock synchronized with the reproduced video signal is output from a line lock clock output terminal.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a clock generation circuit showing one embodiment of the present invention. As shown in FIG. 1, this embodiment is a circuit for generating a clock CKL synchronized with a reproduced video signal in a video signal recording / reproducing apparatus. In this clock generation circuit, an H / 2 killer circuit 1 for removing a half H included in an equivalent pulse of a composite synchronizing signal CSYNC of a reproduced video signal from a composite sync input terminal 10
And the reference clock FCK from the reference clock input terminal 9.
And a skew cancel circuit 2 which receives the output HP of the H / 2 killer circuit 1 and removes the skew of the synchronization signal, a first analog delay section 3 and a second analog delay section 4
And a control circuit 5 for controlling the phase of the clock.
Further, this clock generation circuit outputs the output ST of the control circuit 5.
/ SP, a ringing oscillator 6 for generating a clock CKL, a horizontal counter 7 for counting the horizontal coordinates of the reproduced video signal by the clock CKL, and a frequency division (FH) of the clock by the output WH of the horizontal counter 7. A clock CKL synchronized with the reproduced video signal is output from a line lock clock output terminal 11.

FIG. 2 is a block diagram of the skew cancel circuit shown in FIG. As shown in FIG. 2, the skew cancel circuit 2 receives a reference clock FCK from a reference clock input terminal 9, counts and outputs count results WF and WE, and first and second counters 12 and 13, A window generation circuit 14 for generating a window based on the count output WF and the count output WH of the horizontal counter 7 described above, and an output WDW of the window generation circuit 14 and an output HP of the H / 2 killer circuit 1 are input. Edge detection circuit 1 that performs edge detection
5 and a control signal generating circuit 16 for generating a control signal to the control circuit 5 and the like based on these outputs.

FIG. 3 is a block diagram of the ring oscillator shown in FIG. As shown in FIG. 3, the ring oscillator 6 receives the output HSD of the second analog delay unit 4 and the output FH of the frequency divider 8 and compares the phases with each other.
A filter circuit 18 for filtering the output PH of the phase comparator 17, and an output VH of the filter circuit 18.
And a switch 20 for controlling the ringing circuit 19 by controlling the opening and closing by the ST / SP signal from the control circuit 5 to generate the clock CKL. In short, the ringing oscillator 6 oscillates and outputs the clock CKL by comparing the phases of HSP and FH.

FIG. 4 is a timing chart of signals for explaining the operation of the horizontal counter shown in FIG. As shown in FIG. 4, the horizontal counter 7 receives and counts the line lock clock CKL generated by the ringing oscillator 6, and outputs a count value WH. The horizontal counter 7
Is set at the next rising edge of the line lock clock CLK after the horizontal counter output WH = HMAX (HMAX is a natural number of 2 or more). That is, the timing of resetting the horizontal counter 7 is performed as illustrated.

The output WH of the horizontal counter 7 is supplied to the H / 2 killer circuit 1 together with the composite synchronizing signal CSYNC of the video signal input from the composite sync input terminal 10, and WH ≧ WC (where WC is a natural number of 2 or more) HMAX / 2 <W
HP is output by making the falling pulse of the composite synchronization signal CSYNC input during the period of C <HMAX) valid. Furthermore, H / 2
The output HP of the killer circuit 1, the output WH of the horizontal counter 7, and the reference clock FCK input to the reference clock input terminal 9 are supplied to the skew cancel circuit 2. Here, the reference clock FCK is a clock synchronized with the standard video format.

Next, the operation of the skew cancel circuit 2 will be described with reference to FIGS. 5 and 6 (a) to 6 (e).

FIG. 5 is a timing chart of signals for explaining the internal operation of the skew cancel circuit shown in FIGS. As shown in FIG. 5, in the skew cancellation circuit 2, the output WH of the horizontal counter 7 and the reference clock FCK are supplied to the first counter 12.
The counter 12 is reset at the rising edge of the reference clock FCK immediately after WH = HMAX, counts the reference clock FCK, and counts the count value WF.
Is output. Since the output WF of the counter 12 and the output WH of the horizontal counter 7 are supplied to the window generating circuit 14, the window generating circuit 14 outputs the output WH = W1 (W1 is a natural number of 2 or more and WC <W1 <HM).
AX) to WF = W2 (W2 is a natural number and W2 <HMAX / 2) from the first counter 1 (hereinafter, this period is referred to as a window period) and outputs a signal WDW.

Next, the output WD of the window generation circuit 14
The output HP of the W and H / 2 killer circuit 1 is the edge detection circuit 1
5 is supplied. The edge detection circuit 15 determines whether the rising edge and the falling edge of the HP are within the WDW window period, and outputs the EDG. The output EDG of the edge detection circuit 15 and the reference clock FCK
Is supplied to the second counter 13. Counter 13 is H
When the falling edge of the output HP of the / 2 killer circuit 1 is within the window period of the output WDW of the window generating circuit 14, it is reset at the falling timing of the HP, counts FCK, and outputs the count value WE to the control signal. Output to the generation circuit 16. The control signal generation circuit 16 receives the output WF of the first counter 12, the output WE of the second counter 13, the output EDG of the edge detection circuit 15, and the output WH of the horizontal counter 7,
Clock start signal HS, skew detection signal SKD, and skew start signal SKS according to WE and EDG
Is output.

FIGS. 6A to 6E are signal timing diagrams for explaining the operation of the skew cancel circuit shown in FIGS. 1 and 2 in various patterns.
As shown in FIG. 6A, here, the H / 2 killer circuit 1
Falling edge of output HP of window generation circuit 1
4 is within the window period of the output WDW, the clock start signal HS and the skew detection signal SKD fall at the timing of the fall of HP. At this timing, the output WE = EN (E (E
If the HP does not rise during the period up to N is a natural number, the clock start signal H is output at the timing of the output WH of the horizontal counter 7 = WA (WA is a natural number of 2 or more and WA <WC).
Start S. Next, as shown in FIG. 6B, in this case, if the HP rises during the period up to WE = EN at the timing of FIG. To launch HS and SKD.

Next, as shown in FIG. 6C, when there is a rising edge of HP in the window period, this is determined as noise or skew of the synchronizing signal, and HS and SKD are determined at the rising edge of HP. Start up.
Further, as shown in FIG. 6D, when there is no HP edge within the window period, it is determined that the skew of the synchronizing signal, the HS is not lowered, and the output WF of the first counter 12 is not lowered.
= W2 (at the end of the window period) to start SKD.
Further, as shown in FIG. 6 (e), the output HS of the second counter 13 becomes HS = W3 (W3 is a natural number and W3> W2).
Does not fall, the skew start signal SKS falls at the timing of WF = W3, and rises at the output WH = WA of the horizontal counter 7.

FIG. 7 is a signal timing chart for explaining the operation of the first analog delay section and the control circuit shown in FIG. As shown in FIG. 7, the clock start signal HS of the output of the skew cancel circuit 2 is supplied to the first analog delay unit 3, and after being analog-delayed for a predetermined time, is output to the control circuit 5 as an HSI. The output HSI of the first analog delay unit 3 and the output WH of the horizontal counter 7
When the skew start signal SKS among the outputs of the skew cancel circuit 2 is supplied to the control circuit 5, the control circuit 5 outputs the signal ST which becomes high only immediately after WH = HMAX during the falling time of the HSI or the falling time of SKS. /
Output SP. The above is the operation centering on the control circuit 5.

FIGS. 8A and 8B are timing charts of signals for explaining the operation of the frequency dividing circuit shown in FIG. As shown in FIG. 8A, the skew detection signal SKD, the output WH of the horizontal counter 7 and the reference clock FCK of the reference clock input terminal 9 among the outputs of the skew cancellation circuit 2 are supplied to the frequency dividing circuit 8. When the skew detection signal SKD = 0 (when there is no skew), the output FH of the frequency dividing circuit 8 is WH = WT1 of the horizontal counter 7.
(WT1 is a natural number of 2 or more and WT1 <WA), and WH = WT2 (WT2 is a natural number of 2 or more and WC <W
T2 <WT1 and WT2−WT1 ≦ WA). That is, 0 counted by the reference clock FCK
C9F of the counter that repeats the steps from to HMAX / 2
At the timings of WH = WT1 and WH = WT2.

As shown in FIG. 8B, when the skew detection signal SKD = 1 (at the time of skew), the output FH of the frequency dividing circuit 8 is the value M of the value M latched by C9F at the last WH = WT1. It rises at the time, and falls when C9F finally reaches the value N latched at WH = WT2.

On the other hand, the clock start signal HS of the output of the skew cancel circuit 2 is
HSD after a predetermined period of analog delay
Is output to the ringing oscillator 6. This second
The output HSD of the analog delay unit 4 and the output S of the control circuit 5
The T / SP and the output FH of the frequency divider 8 are supplied to a ringing oscillator. Thus, the ringing oscillator 6 supplies the output HSD of the second analog delay unit 4 and the output FH of the frequency divider 8 to the phase comparator 17 of FIG.
As a result of the phase comparison, a signal PH which becomes high only during a period from the rise of FH to the rise of HSD is output.
The output PH of the phase comparison circuit 17 is filtered by the filter circuit 18 and supplied to the ringing circuit 19 as a voltage level signal VH converted into a low frequency component of the pulse signal PH. Also, the output ST / SP of the control circuit 5
Is supplied to a control terminal of a switch 20, one of the switches 20 is grounded and the other is connected to a ringing circuit 19. The switch 20 is turned on (connected) at the rise of the output ST / SP of the control circuit 5, and the ringing circuit 19 stops generating the clock CKL. Conversely, the switch 20 is turned off (disconnected) at the fall of ST / SP, and the ringing circuit 1 starts the clock CKL having a frequency corresponding to the output VH of the filter circuit 18. Thereafter, while ST / SP = 0 (when the switch 20 is off), the ringing circuit 19 outputs a clock CKL having a frequency corresponding to the output VH of the filter circuit 18. The clock CKL generated by the ringing oscillator 6 is supplied to the horizontal counter 7 and, at the same time, is output via the line lock clock output terminal 11.

In short, in this embodiment, the start / stop of the clock CKL generated by the ringing oscillator 6 is controlled by the output signal ST / SP of the control circuit 5, so that the clock phase at the start point of each horizontal line of the image is controlled. be able to. Further, the skew cancel circuit 2 detects the skew of the composite synchronizing signal CSYNC, and the dividing circuit 8 can output the divided output FH at the same timing as the previous line at the time of skew. Frequency control without noise.

FIG. 9 is a block diagram of a clock generation circuit showing a second embodiment of the present invention. As shown in FIG. 9, the present embodiment differs from the above-described first embodiment in that a clock switching circuit 21 is provided, and the same applies to the other H / 2 killer circuits 1 to the frequency dividing circuit 8. is there. In this embodiment, the output ST / SP of the control circuit 5 is supplied to the ringing oscillator 6 and the clock switching circuit 21, and the output CKL of the ringing oscillator 6 is supplied to the horizontal counter 7 and the clock switching circuit 21. Further, the reference clock FCK from the reference clock input terminal 9 is also supplied to the clock switching circuit 21, and the clock switching circuit 2
1 output CKL2 is a line lock clock output terminal 11
Is output via.

Next, the operation of the clock switching circuit 21 will be described with reference to FIG. FIG. 10 is a timing chart of various signals in FIG. As shown in FIG. 10, the output ST / SP of the control circuit 5, the output clock CKL of the ringing oscillator 6, and the reference clock FCK input to the reference clock input terminal 9 are supplied to the clock switching circuit 21. Here, the output CKL of the ringing oscillator 6 generated by the same operation as in the first embodiment described above is a clock synchronized with the reproduced video signal having a time-axis fluctuation component in the standard format of the video signal. The reference clock FCK input via the clock input terminal 9 is a clock synchronized with the standard format of the video signal.

Next, when the output ST / SP of the control circuit 5 is "0", the clock switching circuit 21 outputs the output CKL of the ringing oscillator 6 as the output CKL2, and conversely, when the output ST / SP is "1". At this time, the reference clock FCK is output. In this clock switching operation, ST / S
FCK is output from the first rising edge of FCK after the rise of P, and CKL is output from the first rising edge of CKL after the fall of ST / SP. Thus, the output CKL2 of the clock switching circuit 21
Is output via a line lock clock output terminal 11.

In this embodiment, the output ST / SP of the control circuit 5 =
The continuous clock CKL2 can be obtained by inserting the reference clock FCK of the reference clock input terminal 9 during the stop period of the output clock CKL of the ringing oscillator 6 that stops during the period of "1". Further, since the pulse shorter than one clock width is canceled at the clock switching point, the clock CKL obtained in this embodiment is cancelled.
In the case where signal processing is performed using No. 2, malfunction at a clock switching point can be prevented.

Further, the output CK of the ringing oscillator 6
The stop period of L is a horizontal retrace period or a vertical retrace period of an image. However, if signal processing is desired to be performed during this period, the signal cannot be processed if the clock stops, but the continuous clock CKL2 of the present embodiment can realize signal processing during the flyback period. That is, in the output of this embodiment, the clock becomes discontinuous at the clock switching point, but since the retrace period is not on the actual screen, there is no problem in image quality.

[0035]

As described above, the clock generation circuit of the present invention controls the start / stop of the clock generated by the ringing oscillator by the ST / SP output of the control circuit, thereby starting each horizontal line of an image. There is an effect that the clock phase of the point can be controlled. Therefore, in the time base collector, the reproduced video signal is A / D-converted by the clock CKL and written into the memory,
When the D / A conversion is performed by reading data from the memory using a reference clock having a fixed phase relationship with the horizontal line cycle synchronized with the standard format of the video signal, the phase relationship between the clock CKL and the horizontal line cycle matches. It is possible to completely correct the time axis fluctuation from the starting point of the line.

Further, the clock generation circuit of the present invention converts the chroma signal of a video signal from analog to digital by the generated clock CKL, writes it in the memory, reads it out with the reference clock, and then replaces it with a burst signal generated from the reference clock. Since the horizontal line cycle and the burst position and phase in the standard format video signal have a fixed relationship, the phase of the read chroma signal completely matches, and the color reproduction of the video can be accurately performed.

Further, according to the present invention, the skew of the composite synchronizing signal CSYNC is detected by the skew cancel circuit, and the divided circuit can output the divided output at the same timing as the previous line at the time of skew. Frequency control without the influence of the above.

As described above, if the time axis fluctuation is corrected using the clock generated according to the present invention, more accurate correction can be performed as compared with the related art, and the image quality of the video recorded / reproduced image can be improved. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock generation circuit showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a skew cancellation circuit shown in FIG. 1;

FIG. 3 is a configuration diagram of a ring oscillator shown in FIG. 1;

FIG. 4 is a timing chart of signals for explaining the operation of the horizontal counter shown in FIG. 1;

FIG. 5 is a timing chart of signals for describing an internal operation of the skew cancellation circuit shown in FIGS. 1 and 2;

FIG. 6 is a timing chart of signals for explaining operations of the skew cancel circuit shown in FIGS. 1 and 2 in various patterns.

FIG. 7 is a timing chart of signals for explaining operations of a first analog delay unit and a control circuit shown in FIG. 1;

FIG. 8 is a timing chart of signals for explaining the operation of the frequency divider shown in FIG. 1;

FIG. 9 is a block diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 10 is a timing chart of various signals in FIG. 9;

FIG. 11 is a block diagram of a clock generation circuit showing an example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 H / 2 killer circuit 2 Skew cancellation circuit 3, 4 Analog delay part 5 Control circuit 6 Ringing oscillator 7 Horizontal counter 8 Divider circuit 9 Reference clock input terminal 10 Composite sync input terminal 11 Line lock clock output terminal 12, 13 Counter 14 Window generation circuit 15 Edge detection circuit 16 Control signal generation circuit 17 Phase comparison circuit 18 Filter circuit 19 Ringing circuit 20 Switch 21 Clock switching circuit

Claims (3)

(57) [Claims] When generating a clock synchronized with a reproduced video signal in a video signal recording / reproducing device, a half H included in an equivalent pulse of the reproduced video signal is inputted by inputting a composite synchronous signal of the reproduced video signal. H / 2 to be removed
A killer circuit, a skew cancel circuit for inputting a reference clock and removing a skew of the synchronization signal, and a first circuit for delaying a part of an output of the skew cancel circuit
And a second analog delay unit, a control circuit for controlling the phase of the clock, a ringing oscillator for generating a clock by the output of the control circuit, and a horizontal coordinate of the reproduced video signal based on the clock generated by the ringing oscillator. And a frequency dividing circuit for dividing a clock by an output of the horizontal counter, and outputting a clock synchronized with the reproduced video signal from a line lock clock output terminal. Generator circuit. 2. A skew cancel circuit comprising: a first and a second counter for counting the reference clock; a window generating circuit for generating a skew width of a synchronizing signal of the reproduced video signal; 2. The clock generation circuit according to claim 1, further comprising: an edge detection circuit that detects an edge of the synchronization signal; and a control signal generation circuit that determines a skew of the synchronization signal from a position of the edge of the synchronization signal to generate a control signal. . 3. The ringing oscillator includes: a phase comparison circuit that compares phases of two signals; a filter circuit that receives an output of the phase comparison circuit and performs filtering;
2. The clock generation circuit according to claim 1, further comprising: a ringing circuit that inputs an output of the filter circuit to generate a clock having a specific phase and frequency; and a switch that is controlled by a clock start control signal and a clock frequency control signal.