JPS6180983A - Digital picture memory device - Google Patents

Digital picture memory device

Info

Publication number
JPS6180983A
JPS6180983A JP59201728A JP20172884A JPS6180983A JP S6180983 A JPS6180983 A JP S6180983A JP 59201728 A JP59201728 A JP 59201728A JP 20172884 A JP20172884 A JP 20172884A JP S6180983 A JPS6180983 A JP S6180983A
Authority
JP
Japan
Prior art keywords
signal
cycle
synchronization signal
video signal
picture memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59201728A
Other languages
Japanese (ja)
Inventor
Teruaki Ono
輝昭 大野
Shinjiro Katagiri
片桐　信二郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Naka Seiki Ltd
Original Assignee
Hitachi Naka Seiki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Naka Seiki Ltd filed Critical Hitachi Naka Seiki Ltd
Priority to JP59201728A priority Critical patent/JPS6180983A/en
Publication of JPS6180983A publication Critical patent/JPS6180983A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To write on a picture memory irrespective of the cycle of a synchronizing signal, by separating the synchronization signal component from the compound video signal, and variably controlling the writing cycle onto the picture memory according to the cycle of the synchronization signal. CONSTITUTION:Compound video signal outputted from an outside video signal outputting device 1 contains a video signal and a synchronizing signal whose signal component is separated by a separator 2, and further separated into a horizontal synchronization signal and a vertical synchronization signal by a pulse width discriminator 3. These signals are then inputted to frequency meters 4, 5 and the frequency of each signal is detected. According to the frequency thus detected, a timing control 6 automatically changes and controls the cycle of a write signal for a picture memory 7 and the cycle of a sampling pulse for an A/D converter 8.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はデジタル画像メモリ装置に係シ、特に入力する
複合映像信号に含まれる、同期信号の周期が既知でない
場合にでも使用可能なデジタル画像メモリ装置に関する
。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a digital image memory device, and in particular to a digital image memory that can be used even when the period of a synchronization signal included in an input composite video signal is unknown. Regarding equipment.

〔発明の技術的背景〕[Technical background of the invention]

従来のデジタル画像メモリ装置は、入力する複合映像信
号が、ＮＴＳＣ方式のテレビ信号のように、同期信号の
周期が既知である場合にしか適用できず、定められた周
期以外の同期信号が入力されると、正常な画像記憶が不
可能であった。Conventional digital image memory devices can only be applied when the input composite video signal has a known synchronization signal period, such as an NTSC television signal, and if a synchronization signal with a period other than the specified period is input. As a result, normal image memory was impossible.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、いかなる周期の同期信号を有する複合
映像信号が入力されても、正常な画像が記憶可能なデジ
タル画像メモリ装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a digital image memory device that can store normal images even if a composite video signal having a synchronization signal of any period is input.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明では、入力される複
合映像信号の中から同期信号成分を、分離し、さらにそ
の同期信号を水平同期信号と垂直同期信号とに分離する
。さらにこの分離された同期信号の周期を自動的に検出
し、その周期に応じてメモリ装置への曹き込み周期が自
動的に設定されるようにしたものであろう 〔発明の実施例〕 以下、本発明の一実施例を第１図によシ説明する。In order to achieve the above object, the present invention separates a synchronization signal component from an input composite video signal, and further separates the synchronization signal into a horizontal synchronization signal and a vertical synchronization signal. Furthermore, the period of this separated synchronization signal would be automatically detected, and the filling period to the memory device would be automatically set according to the period. [Embodiment of the invention] The following , one embodiment of the present invention will be explained with reference to FIG.

外部映像信号出力装置１より出力される信号は、例えば
、第２図の１に示す様な複合映像信号である。この信号
１−ｉ、同期信号分離器２に入り、ここで、レベル・ス
ライス方式によシ同期信号成分が分離されるっ分離され
た同期信号は、パルス幅弁別器３に入力され、ここで、
パルス幅の違う２種類の同期信号すなわち水平同期信号
と垂直同期信号に分離される。この分離された同期信号
は、それぞれ、周波数計測器４および周波数計測器５に
入力され、ここで水平同期周波数および垂直同期周波数
が求まる。この値によりタイミング制御部６が、画像メ
モリ７への書き込み信号や、アナログ・デジタル変換器
８へのテンプリング・パルスの周期を自動的に制御する
。このタイミング制御部には、マイクロ・コンピュータ
を利用してもよい。The signal output from the external video signal output device 1 is, for example, a composite video signal as shown in 1 in FIG. This signal 1-i enters the sync signal separator 2, where the sync signal component is separated by a level slicing method.The separated sync signal is input to the pulse width discriminator 3, where the sync signal component is separated. ,
It is separated into two types of synchronization signals with different pulse widths: a horizontal synchronization signal and a vertical synchronization signal. The separated synchronization signals are input to a frequency measuring device 4 and a frequency measuring device 5, respectively, where the horizontal synchronizing frequency and the vertical synchronizing frequency are determined. Based on this value, the timing control section 6 automatically controls the cycle of the write signal to the image memory 7 and the period of the tempering pulse to the analog-to-digital converter 8. A microcomputer may be used for this timing control section.

〔発明の効果〕〔Effect of the invention〕

号が制御されるので、いかなる複合映像信号が入力され
ても正常にメモリ装置に記憶できる効果がある。Since the signal is controlled, any composite video signal that is input can be stored normally in the memory device.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明によるデジタル画像メモリ装置の実施
例を示すブロック図である、第２図は第１図の各部の信
号波形図である。 １・・・外部映像信号出力装置、２・・・同期信号分離
器、３・・・パルス幅弁別器、４・・・周波数計測器（
水平同期信号用）、５・・・周波数計測器（垂直同期信
号用）、６・・・タイミング制御部、７・・・画像メモ
リ、８・・・アナログ・デジタル変換器、９・・・増幅
器。FIG. 1 is a block diagram showing an embodiment of a digital image memory device according to the present invention, and FIG. 2 is a signal waveform diagram of each part of FIG. 1. 1... External video signal output device, 2... Synchronization signal separator, 3... Pulse width discriminator, 4... Frequency measuring device (
(for horizontal synchronization signal), 5... Frequency measuring device (for vertical synchronization signal), 6... Timing control section, 7... Image memory, 8... Analog-to-digital converter, 9... Amplifier .

Claims (1)

【特許請求の範囲】[Claims] １、映像信号と同期信号を複合した、複合映像信号を入
力信号とし、その入力信号に含まれる映像信号をデジタ
ル化し、メモリ装置に記憶させる手段を有したデジタル
画像メモリ装置において、その入力信号に含まれる同期
信号の周期が、いかなる周期であろうとも、その周期を
自動的に検出し、その周期の緩急に応じて、自動的にメ
モリ装置への記憶速度が変更されるように構成されたこ
とを特徴とするデジタル画像メモリ装置。1. In a digital image memory device that takes a composite video signal that is a composite of a video signal and a synchronization signal as an input signal, and has means for digitizing the video signal included in the input signal and storing it in the memory device, the input signal is No matter what the period of the included synchronization signal is, it is configured to automatically detect the period and automatically change the storage speed to the memory device according to the speed of the period. A digital image memory device characterized by:
JP59201728A 1984-09-28 1984-09-28 Digital picture memory device Pending JPS6180983A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59201728A JPS6180983A (en) 1984-09-28 1984-09-28 Digital picture memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59201728A JPS6180983A (en) 1984-09-28 1984-09-28 Digital picture memory device

Publications (1)

Publication Number Publication Date
JPS6180983A true JPS6180983A (en) 1986-04-24

Family

ID=16445946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59201728A Pending JPS6180983A (en) 1984-09-28 1984-09-28 Digital picture memory device

Country Status (1)

Country Link
JP (1) JPS6180983A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS637083A (en) * 1986-06-27 1988-01-12 Olympus Optical Co Ltd Memory read control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS637083A (en) * 1986-06-27 1988-01-12 Olympus Optical Co Ltd Memory read control circuit

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