JPS60247377A - Automatic horizontal hold adjusting circuit - Google Patents

Abstract

PURPOSE:To make adjustment of the horizontal synchronizing phase unnecessary by constituting a circuit of two kinds of horizontal synchronizing signal separator and phase detector and three kinds of horizontal synchronizing counter and detecting the phase shift between an input video signal and an input synchronizing signal to correct automatically the phase. CONSTITUTION:The phase difference between synchronizing signals from horizontal synchronizing signal separators 4 and 20 is detected by a phase detector 21 [figure (f)]. This phase difference signal is counted by a horizontal synchronizing counter 23 as shown by A only when this signal is in the high level [figure (g)]. When phases of horizontal synchronizing signals coincide with each other, a phase detector 22 generates a pulse to reset the output of the counter 23. The output of the detector 22 is in the high level because of disaccord [figure (h)]. Set offset data from a terminal 25 is added to data obtained in the counter 23 by an adder 24; and when this data is loaded at a point C by loading it to a horizontal synchronizing counter 6, horizontal synchronizing pulses coinciding with the horizontal synchronizing signal of the input signal are obtained from a point D.

Description

TECHNICAL FIELD The present invention relates to an automatic horizontal synchronization adjustment circuit for writing or reading television video signals to or from an image memory device.

(Prior Art) Conventionally, this type of image memory device has used a reference pulse generation circuit as shown in FIG. 1 to form write and read timings. In this circuit, a horizontal synchronizing signal of a television synchronizing signal inputted from an input terminal 1 is extracted by a horizontal synchronizing separator 4, and converted by a horizontal reference counter 5 into pulses used within the circuit. This horizontal reference counter 5 is set to the zero position by the deJ resin b setting value from the zero setting input terminal 11. This output pulse of the horizontal reference counter 5 is applied to the load terminal of the horizontal synchronization counter 6 and becomes a timing pulse. This horizontal synchronization counter 6 can adjust the position of the horizontal synchronization pulse to be output by a horizontal synchronization adjuster 10 that can be digitally set arbitrarily.

On the other hand, the television video signal is sent from the input terminal 2 to the A/D
It is applied to the converter 7 and converted into a digital signal, and is sent to the image memory device 8 according to the synchronization signal from the horizontal synchronization counter 6.
is read into. Further, the digital signal read from the image memory device 8 is converted into an analog signal by a D/A converter 9, and outputted from the output terminal 3 as a video signal.

This conventional horizontal synchronization pulse generation circuit has the disadvantage that the horizontal synchronization adjuster 10 must be adjusted to match the synchronization signal every time the input video signal changes, and the adjustment takes time.

(Object of the Invention) An object of the present invention is to eliminate such drawbacks and to detect a phase shift between an input video signal and an input synchronization signal and automatically correct the phase, thereby adjusting the horizontal synchronization phase. The purpose of this invention is to provide an automatic φ horizontal synchronization adjustment circuit that allows accurate alignment without adjustment.

(Structure of the Invention) The structure of the automatic horizontal synchronization adjustment circuit of the present invention includes: a first horizontal synchronization separator that extracts a horizontal synchronization signal from an input reference synchronization signal; and a reference horizontal synchronization signal based on the horizontal synchronization signal. a horizontal reference counter that outputs a horizontal reference counter, a first horizontal synchronization counter that shifts horizontal synchronization pulses from the horizontal reference counter in accordance with control data, and a second horizontal synchronization counter that extracts only a horizontal synchronization signal from an input video signal. A horizontal sync separator, a phase detector that detects the phase shift of each output of the first and second horizontal sync separators, and a second phase detector that is set with a count value corresponding to the phase shift of the phase detector. a horizontal synchronization counter; an adder for adding the output of the second horizontal synchronization counter to a predetermined set value; The present invention is characterized in that a horizontal synchronization pulse output from the first horizontal synchronization counter is synchronized with a horizontal synchronization signal of the video signal.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram of an image memory device including an embodiment of the present invention, and FIGS. 3(a) to 3(i) are operational waveform diagrams of FIG. 2. In this embodiment, in contrast to the conventional circuit shown in FIG. 1, a second horizontal sync separator 20. First and second synchronization detector 21
．． 22, a second horizontal synchronization counter 23, and an adder 24 are added.

From the synchronization signal inputted from the input terminal 1 (FIG. 3(a)), only the horizontal synchronization signal is extracted by the first horizontal synchronization separator 4 (FIG. 3(b)). This horizontal synchronizing signal is applied to the clear terminal of the horizontal reference counter 5 in the next stage, and is converted into a pulse that is actually used inside the circuit (FIG. 3(C)). The phase of this horizontal synchronization pulse matches the input horizontal synchronization. This horizontal synchronization pulse is applied to the load terminal of the first horizontal synchronization counter 6 in the next stage, and serves as a timing pulse for loading data from the adder 24.

On the other hand, the input video signal from input terminal 2 (Fig. 3(d))
Similarly, only the horizontal synchronization of the input video signal is extracted in the second horizontal synchronization separator 20 (FIG. 3(e)). The synchronization signals from the first and second horizontal synchronization separators 4.degree. 20 enter the first phase detector 21, which detects the phase difference between them (FIG. 3(f)). This phase difference signal acts as a count enable for the second horizontal synchronization counter 23, and counting is performed as shown in A only during the high level period of this phase difference signal (Fig. 3 (g)), and counting is performed at point B. Stop.

The other second phase detector 22 generates a pulse when the phases of the horizontal synchronization signals match, and resets the output of the second horizontal synchronization counter 23 to zero. The output of the second phase detector 22 is at a high level because of the mismatch (FIG. 3(h)). Second horizontal synchronization counter 23
The data obtained in FIG. When loaded at point C in FIG. 3(g), a horizontal synchronization pulse corresponding to the horizontal synchronization of the input video signal is obtained from the point in FIG. 3(il).

(Effects of the Invention) As explained above, the present invention eliminates the need for conventional horizontal synchronization adjustment by being configured with two types of horizontal synchronization separators, two types of phase detectors, and three types of horizontal synchronization counters. It becomes possible to create a device that requires no adjustment.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image memory device including a conventional horizontal synchronization circuit, FIG. 2 is a block diagram including an embodiment of the present invention, and FIG. 3 shows the operation of this embodiment. FIG. In the figure, 1, 2 - input terminal, 3... output terminal, 4
．． 20 horizontal sync separator, 5/horizontal reference counter, 6,
23・Horizontal synchronization counter, 7・・A/D converter, 8・・
・Image memory device, 9...D/A converter, 10...Horizontal synchronization adjuster, 11...Zero setting terminal, 21, 22
- Phase detector, 24... Adder, 25... Offset setting terminal.

Claims (1)

[Claims] a first horizontal synchronization separator that extracts a horizontal synchronization signal from an input reference synchronization signal; a horizontal reference counter that outputs a reference horizontal synchronization pulse using the horizontal synchronization signal as a reference; and a horizontal synchronization pulse from the horizontal reference counter. a first horizontal synchronization counter that shifts in accordance with control data, a second horizontal synchronization separator that extracts only a horizontal synchronization signal from an input video signal, and these first and second horizontal synchronization separators. a phase detector that detects the phase shift of each output of the phase detector; a second horizontal synchronization counter to which a count value corresponding to the phase shift of this phase detection path is set; and the output of the second horizontal synchronization counter is set to a predetermined value. an adder for adding the value, the addition output of the adder is loaded as the control data into the first horizontal synchronization counter, and the horizontal synchronization pulse output from the first horizontal synchronization counter is added to the video image. An automatic horizontal synchronization adjustment circuit characterized by synchronizing with a horizontal synchronization signal of a signal.