JPH04328967A - Sampling phase adjustment device in picture processing system - Google Patents

Abstract

PURPOSE:To obtain higher picture quality by realizing the phase adjustment device making a sampling timing of a video camera section coincident with a phase of an A/D conversion timing of a picture processing section automatically. CONSTITUTION:A test signal of a test signal generating circuit 33 is A/D- converted by an A/D converter circuit 28 after the test mode is set and the result is analyzed by a system control circuit 39 to obtain a phase error of timing clocks between a video camera section 21 and a picture processing section 22 and a phase adjustment circuit 27a of a synchronizing coupling circuit 27 adjusts the phase of the clock of a timing clock generating circuit 25 based on the error information. The phases of both the timing clocks are made coincident through the repetition of the sequence thereby eliminating deterioration in picture due to a phase difference of the sampling time in the normal mode and the timing of the A/D conversion.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling phase adjusting device in an image processing system, and relates to a sampling phase adjusting device for an image processing system, which adjusts the phase of sampling timing on the video camera side and the A/
It is an object of the present invention to provide a device that automatically matches the phase of D conversion timing and obtains higher image quality.

0002

2. Description of the Related Art When a video camera section is connected to a digital image processing section (image processing board, etc.), the system has a circuit configuration as shown in FIGS. 5 to 7.

First, FIG. 5 shows a circuit configuration when a general-purpose video camera unit 51 is connected to an image processing unit 52. H) The signal sampled in the circuit 54 and subjected to color separation, etc. is subjected to real-time video processing in the signal processing circuit 55, and then sent to the image processing section 52 as an analog video signal (RGB output). On the other hand, the image processing section 52 converts the received video signal into A/
It is converted into a digital signal by the D conversion circuit 56 and stored in the memory 57.
After digital signal processing is performed for each frame in the signal processing circuit 58, the signal is converted into an analog signal in the D/A conversion circuit 59 and output to a recording system or the like (not shown). In this type of system, the video camera section 51 and the image processing section 52 independently operate a timing clock generation circuit 60,
61, and the video camera section 51 or the image processing section 52 is provided with a synchronous coupling means as shown in FIG. 6 or 7, which will be described later. Note that 62 represents a drive circuit for the solid-state image sensor 53, and 63 represents a system control section for the image processing section 52. In this system, since the video camera section 51 and the image processing section 52 include the signal processing circuits 55 and 58 as described above, the circuit scale becomes large. Further, the signal processing circuit 55 complements the discretely changing signal obtained by the S/H circuit 54 and outputs it as a band-limited continuous signal. The amount of information in the video signal decreases, leading to deterioration in image quality. Furthermore, there is a drawback that signal processing for correcting this on the image processing section 52 side becomes extremely complicated.

In contrast to the above-mentioned system, FIG. 6 shows a circuit configuration in which a video camera section 64 and an image processing section 65 are integrated into an assembly. No signal processing circuit is provided for this purpose, and the signal processing section 58a on the image processing section 65 side also executes the processing executed by the signal processing circuit 55 in the system of FIG. 5 through digital processing. In this system, the vertical and horizontal synchronization signals of the timing clock generation circuit 61 on the image processing section 65 side are outputted to the synchronization coupling circuit 66 provided on the video camera section 64 side, and the reference clock signal on the video camera section 64 side is control and synchronization.

Furthermore, FIG. 7 shows a system for establishing synchronization of reference clocks, similar to the system shown in FIG.
Contrary to the case in FIG. 6, synchronization is achieved by outputting the composite synchronization signal output from the timing clock generation circuit 60 on the video camera section 67 side to the synchronization coupling circuit 66 provided on the image processing section 68 side. There is.

By the way, even if synchronization is achieved using the synchronization coupling circuit 66 as in the systems shown in FIGS. 6 and 7, it is actually necessary to adjust the horizontal phase due to differences in the timing of the synchronization signals. For this reason, a phase adjustment circuit 66a is built into the synchronization coupling circuit 66, and the horizontal phase is adjusted by changing the phase of the horizontal synchronization signal. An example of the synchronous coupling circuit 66 incorporating this phase adjustment circuit 66a is shown in FIG. The horizontal phase can be adjusted by inputting the horizontal synchronization signal to the phase comparator 71 via the phase adjustment circuit 66a and controlling the phase adjustment voltage of the phase adjustment circuit 66a.

The detailed operation of the phase adjustment circuit 66a will now be described with reference to FIG. 9. First of all,
The edge detection circuit 7 detects the falling edge of one horizontal synchronization signal.
4 and sets the RS-FF circuit 75. As a result, the npn transistor 76 is cut off by the output of the RS-FF circuit 75, discharging of the capacitor 77 is stopped, and charging from the current source 78 is started. When this charging voltage becomes larger than the phase adjustment voltage, the RS-FF circuit 75 is reset by the output of the voltage comparator 79, triggering the one-shot circuit 80, and inputting its output to the phase comparator 71. With the above operation, one horizontal synchronization signal can be input to the phase comparator 71 after being delayed by a time proportional to the phase adjustment voltage, and the horizontal phase can be adjusted by changing the phase adjustment voltage. .

[0008]

By the way, it is good to adjust the horizontal phase between the video camera units 64, 67 and the image processing units 65, 68 as in the systems shown in FIGS. The analog video signals outputted from the sections 64 and 67 change discretely with a change band as shown in FIG. 10(a). Therefore, the video camera sections 64, 67
Side sampling timing and image processing units 65, 68
If there is a phase difference in the timing of A/D conversion on the side,
In some cases, A/D conversion is performed in a changing band of the video signal, resulting in image deterioration. For example, the central A/D conversion timing in FIG. 10(b) corresponds to the change band of the video signal,
As a result, the level after conversion is lower than the normal conversion level. The signal processing circuit 58a on the image processing units 65 and 68 side in the systems shown in FIGS. 6 and 7 cannot perform correction in that case. In principle, this problem can be solved by adjusting the sampling phase, and as a result, the above-mentioned horizontal phase adjustment method can achieve this purpose, but in reality, the image (or signal) after A/D conversion Adjustments must be made repeatedly while observing (data), which takes too much time and effort, and the accuracy of the adjustments cannot be expected to be very high.

On the other hand, in the system shown in FIG. 7, the sampling clock of the video camera section 67 is outputted to the synchronous coupling circuit 66 of the image processing section 68, as shown in FIG. A device capable of creating an A/D conversion clock synchronized with a sampling clock has also been proposed (Japanese Patent Application Laid-open No. 2003-11002-1).
No. 274194). According to this method, (c) in FIG.
By setting the A/D conversion timing with respect to the sampling timing to a phase difference ψ greater than the change time of the video signal, a regular conversion level can always be obtained. However, normal image processing units do not have the ability to receive sampling clocks from outside, and configuring such a system requires designing a dedicated image processing unit, which reduces versatility and expandability. It will be missing.

Accordingly, the present invention provides a system comprising an image processing section and a video camera section that operates in synchronization with its synchronization signal, in which the phase of the A/D conversion timing of the image processing section and the sampling timing of the video camera section is adjusted. It was created with the aim of providing an image processing system that automatically fine-tune errors and eliminate image deterioration.

[0011]

[Means for Solving the Problems] The basic configuration of the present invention is shown in FIG.
A video camera section 6 outputs an analog video signal sampled (S/H circuit 5) in synchronization (synchronous coupling circuit 4) with a synchronization signal (synchronization signal generation circuit 3) of In an image processing system comprising an image processing section 2 that captures image information by synchronizing an analog video signal with an internal synchronization signal and performing A/D conversion (A/D conversion circuit 7), on the video camera section 6 side,
mode setting means 8 for switching between normal mode and test mode; signal generating means 9 for generating a predetermined test signal synchronized with sampling timing when setting the test mode; and generating a signal in place of the analog video signal when setting the test mode. A switching means 10 for outputting the test signal of the means 9 and a phase adjustment means 11 for adjusting the sampling phase using phase error information from the image processing section 2 are provided. a phase error detection means 12 that detects error information between the phase of the A/D conversion timing and the phase of the sampling timing of the video camera section 6 using the level information after the A/D conversion; The present invention relates to a sampling phase adjustment device in an image processing system characterized in that a phase error output means 13 for outputting to a video camera section 6 is provided.

0012

[Operation] In this image processing system, when the mode setting means 8 sets the normal mode, the switching means 10 constitutes a circuit that connects the S/H circuit 5 and the image processing section 2, and the solid-state image sensor 1 The obtained analog video signal is S/H
After being sampled by the circuit 5, it is output to the A/D conversion circuit 7 of the image processing section 2, and the digital signal after A/D conversion is processed by the signal processing circuit 14 and output to a recording system, etc. . On the other hand, when the mode setting means 8 sets the test mode,
The switching means 10 constitutes a circuit that connects the signal generating means 9 and the image processing section 2, and causes the test signal outputted by the signal generating means 9 to be outputted to the A/D conversion circuit 7. Here, the test signal is synchronized with the sampling clock controlled by the synchronous coupling circuit 4 and has a constant signal waveform.

Similar to the video signal, this test signal is also A/D converted by the A/D conversion circuit 7 of the image processing section 2, but the A/D conversion is performed using a clock generated by the synchronization signal generation circuit 3. executed synchronously. By the way, since the test signal has a constant signal waveform, analysis of the conversion level after A/D conversion reveals that the sampling timing of the S/H circuit 5 and the A/D conversion by the A/D conversion circuit 7 are Timing phase errors can be quantitatively detected. Therefore, the phase error detection means 12 detects the phase error using the test signal after A/D conversion, and furthermore, the phase error information is outputted to the video camera section 6 side by the phase error output means 13.

On the other hand, in the video camera section 6, the phase error information is received by the phase adjustment means 11, and the means 11 outputs it to the signal generation means 9 by controlling the synchronous coupling circuit 4 based on the error information. Adjust the phase of the synchronized clock. As a result, it is possible to match the phase of the sampling clock to the timing of A/D conversion, and it is possible to eliminate image deterioration caused by phase shift.

[0015]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 2 to 4. First, FIG. 2 is a circuit diagram of an image processing system according to an embodiment, in which 21 indicates a video camera section and 22 indicates an image processing section. In the figure, a solid-state image sensor 23, an S/H circuit/color separation circuit 24, a timing clock generation circuit 25, a drive circuit 26, and a synchronous coupling circuit 27 (with a built-in phase adjustment circuit 27a) are incorporated in the video camera section 21 side. FIG. 6 shows that the A/D conversion circuit 28, memory 29, D/A conversion circuit 31, signal processing circuit 30, and timing clock generation circuit 32 are incorporated in the image processing section 22 side. The system is similar to that of the above system, and the explanation of the operation related to each part will be omitted here.

The system of this embodiment is characterized by a test signal generation circuit 33 and an S/H circuit on the video camera section 21 side.
The image processing unit 22 switches between the analog video signal from the color separation circuit 24 and the test signal from the test signal generation circuit 33.
It incorporates a switch circuit 34 for outputting to the image processing section 22, an I/O 35 for inputting and outputting control signals between the image processing section 22, a D/A conversion circuit 36, and a microcomputer circuit 37 for controlling them; Furthermore, an I/O 38 for inputting and outputting control signals to and from the video camera section 21 is incorporated in the image processing section 22, and a signal analysis program related to phase error detection is provided in the system control section 39.

In this system, unlike conventional systems, a test mode and a normal mode are set, the sampling phase adjustment according to the present invention is executed in the test mode, and the actual video signal acquisition and processing is executed in the normal mode. do. The operation of the system in the test mode will be described in detail below with reference to the flowchart of FIG.

First, the microcomputer circuit 37 sets the test mode, starts the test signal generation circuit 33, and also activates the test signal generation circuit 33 and the image processing section 22.
The switch circuit 34 is set to connect. Further, the microcomputer circuit 37 sends a test mode setting notification signal to the image processing section 22 side through the I/O 35, and the system control section 39, which receives this through the I/O 38, ready-sets the signal analysis program. still,
Setting of this test mode can be performed by detecting the start-up of the system or by an instruction signal from the outside. In this state, the test signal generation circuit 33 outputs a test signal synchronized with the clock of the timing clock generation means 25 (sampling clock in normal mode), and the signal is sent to the A/ Input to the D conversion circuit 28 (F1, F2
). However, as shown in FIG. 4(a), this test signal increases linearly for three periods of the clock, and then
It has a waveform that is constant over a period and falls at the end of six periods.

On the other hand, the A/D converter 28 which has received the test signal performs A/D conversion in synchronization with the clock of the timing clock generating means 32, and the converted test signal is written into the memory 29. Here, the data in the memory 29 is subjected to predetermined processing by the signal processing circuit 30, but at that stage, the signal analysis program in the system control circuit 39 is activated to extract the test signal for one horizontal scan and to extract the test signal for one horizontal scan. 1 Detect the start point of the test signal (F3, F4)
.

Next, the system control circuit 39 measures the signal level after A/D conversion at each timing (F5
). That is, the A/D conversion level closest to the starting point of one test signal is D1, and the immediately preceding A/D conversion level D is
0 and the level D of two consecutive A/D conversions immediately after that
2. Measure D3. For example, FIG. 4(b) shows a case where the clock of the timing generation circuit 25 is advanced in phase, and in this case, D0 to D3 are measured according to the relationships shown in the figure. In addition, the system control circuit 39 uses these measured values to determine the difference between the level values at different timings (S0=D1-D0).
, S1=D2-D1, S2=D3-D2) and calculate (F
6) Furthermore, it is determined whether the differences in the level values obtained above are equal to each other (F7). That is, as can be understood from FIG. 4(b), if the timing clock generating means 25
If the phase of the clock and the timing of the A/D conversion match, the A/D conversion level D0 will be obtained at the start point of the test signal. Since the area is linear, S0=S
1 and S1=S2 hold at the same time, it can be confirmed by looking at whether or not the relationship 1 and S1=S2 is established at the same time, and this is determined in this step (F7).

Therefore, when it is confirmed in the above judgment that S0=S1 and S1=S2, the system control unit 3
9 outputs a test completion notification signal via the I/O 38, and on the video camera unit 21 side that receives this signal via the I/O 35, the microcomputer circuit 37 cancels the test mode, turns off the signal generation circuit 33, and The switch circuit 34 is returned to the normal mode connection state (F8).

On the other hand, if the conditions of S0=S1 and S1=S2 are not satisfied, the above-mentioned phase is shifted. Therefore, the system control unit 39 compares the set threshold P (initial value is 0:←F2) and S0, and if P<
If S0, information for shifting the phase of the test signal by +θ degrees (shifting to the left in Figure 4); if P = S0, shifting the phase of the test signal by -θ degrees (shifting to the right in Figure 4). Create information for this and output it to the video camera section 21 side via the I/O 38 (F9, F10,
F11). Note that the value of θ in this case corresponds to a minute phase amount that is changed in one adjustment sequence, and is selected as a value that does not cause image deterioration within the range of phase amount deviation. Further, the system control unit 39 changes the value of the threshold P to S0 at that stage (F12).

Through the above procedure, the microcomputer circuit 37 of the video camera section 21 receives the shift information via the I/O 35, but the circuit 37 immediately transfers the information to the voltage setting information for the phase adjustment circuit 27a. The data is converted into a D/A conversion circuit 36 and outputted to the D/A conversion circuit 36. And D
The /A conversion circuit 36 outputs a phase adjustment voltage corresponding to the voltage setting signal to the phase adjustment circuit 27a of the synchronous coupling circuit 27. As a result, the synchronous coupling circuit 27 operates as described in FIGS. 8 and 9 to cause the timing clock generation circuit 25 to
The test signal generating circuit 33 synchronizes with the clock by changing the phase of the clock by +θ degrees or −θ degrees.
The phase of the test signal is changed (F13).

[0024] From then on, in the above sequence (F3 to F12) in the test mode, S0=
The process is repeated until the conditions S1 and S1=S2 are satisfied (F3 to F12→F3). That is, the phase of the clock of the timing generating means 25 is adjusted so that the starting point of the test signal converges to the timing of A/D conversion from which the measured value D0 is obtained. When the same condition is met, the microcomputer circuit 37 cancels the test mode, turns off the test signal circuit 33, and switches the switch circuit 34 back to its original state to shift to the normal mode (F7, F8). As a result, in the normal mode after transition, the phase of the sampling timing by the S/H circuit 24 and the phase of the A/D conversion timing of the A/D conversion circuit 28 match, and digital image information without image deterioration can be obtained. It will be done.

[0025]

Effects of the Invention With the above configuration, the present invention allows the sampling timing on the video camera section side to match the phase of the A/D conversion timing on the image processing section side in advance in the test mode, and then in the normal mode. Since the image processing can be shifted to image processing, the problem of image deterioration caused by a phase shift between the sampling timing and the A/D conversion timing in the image processing system can be solved. Furthermore, the phase adjustment sequence can be automatically executed by simply adding software to a conventional system, making it possible to easily perform accurate phase adjustment without increasing the circuit scale. Furthermore, since it can be realized by simply adding software, it can be applied to most image processing systems, and has the advantage of being excellent in versatility and expandability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a sampling phase adjustment device in an image processing system of the present invention.

FIG. 2 is a circuit diagram of an image processing system according to an embodiment.

FIG. 3 is a flowchart showing the operation of the image processing system in a test mode according to the embodiment.

[Fig. 4] Waveform of test signal, clock (sampling timing) of timing clock generation circuit 25, and A/
5 is a timing chart showing an example of timing of D conversion.

FIG. 5 is a circuit diagram of a conventional image processing system.

FIG. 6 is a circuit diagram of a conventional image processing system.

FIG. 7 is a circuit diagram of a conventional image processing system.

FIG. 8 is a circuit diagram of a synchronous coupling circuit incorporating a phase adjustment circuit.

FIG. 9 is a timing chart showing the operation of the phase adjustment circuit.

FIG. 10 is a timing chart showing the A/D conversion level depending on the sampling timing of an analog video signal and the timing of its A/D conversion.

FIG. 11 is a circuit diagram of a conventional image processing system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Solid-state image sensor, 2... Image processing section, 3... Synchronous signal generation circuit, 4... Synchronous coupling circuit, 5... S/H circuit, 6... Video camera section, 7... A/D conversion circuit, 8... Mode setting means,
9... Signal generation means, 10... Switching means, 11... Phase adjustment means, 12... Phase error detection means, 13... Phase error output means.

Claims (1)

[Claims] 1. A video camera unit that outputs an analog video signal sampled by synchronizing an output signal of a solid-state image sensor with a synchronization signal of an image processing unit, and an internal synchronization signal that outputs an analog video signal input from the video camera unit. In an image processing system consisting of an image processing unit that captures image information by performing A/D conversion in synchronization with signal generating means for generating a predetermined test signal synchronized with the sampling timing when the test mode is set; switching means for outputting the test signal of the signal generating means in place of the analog video signal when setting the test mode; and phase error information from the image processing section. A phase adjustment means is provided for adjusting the sampling phase using the A/D conversion timing of the A/D conversion timing and the sampling timing of the video camera section using the level information after A/D conversion of the test signal on the image processing section side. A sampling phase adjustment device in an image processing system, comprising: a phase error detection means for detecting error information with respect to the phase of the image processing system; and a phase error output means for outputting the detected phase error information to a video camera section. .