JPH114359A - Television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a stable vertical timing signal by detecting a reference position of a vertical synchronizing signal, sampling the vertical synchronizing signal based on a proper horizontal sampling pulse and delaying the sampled signal so as to cancel jitter in the vertical synchronizing signal. SOLUTION: Before a vertical synchronizing signal 2 is given to a vertical address counter 6, an edge detection circuit 14 detects a reference edge position of the vertical synchronizing signal 2, a sampling signal generating circuit 13 generates a signal resulting from deviating a horizontal synchronizing signal 2 based on the detection result of the reference edge position. Then a delay circuit 12 samples the vertical synchronizing signal based on the signal generated by the sampling signal generating circuit 13 and delays the vertical synchronizing signal 2 to produce a vertical synchronizing reference waveform without jitter. A reset signal for a vertical address counter 6 is obtained by allowing the vertical address counter 6 to be sampled based on the waveform by means of a horizontal synchronizing signal 1. Based on the generated vertical address signal, a vertical pulse generator 7 generates various vertical pulses 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing signal generating circuit (International Patent Classification H04N9 / 28) in a color television receiver.

[0002]

2. Description of the Related Art Generally, in a color television receiver, in order to perform internal signal processing, various horizontal pulse signals having different phases synchronized with a horizontal synchronization signal and various vertical pulses having different phases synchronized with a vertical synchronization signal are used. I use a lot of signals. In order to create these pulse signals, pulses with different phases are created using analog delay elements based on the video horizontal and vertical synchronization signals, but there are problems with accuracy, stability, and circuit scale. There is. Therefore, as a method for solving the above problem, a timing generation circuit by digital signal processing that can operate stably with high accuracy and can reduce the circuit scale by high integration has been proposed.

An example of this conventional timing generation circuit will be described below with reference to the drawings. FIG. 7 shows a block diagram of a conventional timing generation circuit. This is the level of the video signal,
This is a circuit that generates various vertical pulse signals and horizontal pulse signals used in the television receiver from the vertical synchronization signal.

In FIG. 7, 1 is a horizontal synchronization signal, 2 is a vertical synchronization signal, 3 is a horizontal synchronization PLL circuit, 4 is a horizontal address counter, 5 is a horizontal pulse generator, 6 is a vertical address counter, and 7 is a vertical pulse. A generation unit, 8 is a mixing circuit for horizontal and vertical pulses, 9 is a horizontal pulse signal created from a horizontal synchronization signal, 10 is a vertical pulse signal created from a vertical synchronization signal, and 11 is the horizontal pulse signal and the vertical pulse signal. Is a horizontal / vertical pulse signal created from.

A horizontal synchronizing signal 1 synchronized with a video signal
Is input to the horizontal PLL circuit 3, which
A clock signal and a horizontal reference signal synchronized with the horizontal synchronization signal 1 are output from the circuit, and the horizontal address counter 4 is driven by the clock signal and the horizontal reference signal. The horizontal address signal output from the horizontal address counter 4 is supplied to the horizontal pulse signal generating circuit 5 to synchronize with the horizontal synchronizing signal and to shift the phase accurately in the clock unit generated from the horizontal PLL circuit 3. Horizontal pulse signal 9
Create

The vertical synchronization signal 2 is input to a vertical address counter 6 as a reference signal. Then, by inputting the horizontal synchronizing signal 1 as a clock signal, the vertical address counter 6 generates a vertical address signal corresponding to the scanning line of the video signal. By supplying the vertical address signal to the vertical pulse generation circuit 7, a stable vertical pulse signal whose phase is accurately shifted for each scanning line is created. The horizontal / vertical signal obtained by combining the horizontal pulse signal and the vertical pulse signal is also created by the horizontal / vertical pulse mixing circuit 8.

As described above, by digitally sampling various pulse signals synchronized with the horizontal synchronizing signal and the vertical synchronizing signal used in the television receiver, it is possible to stably produce the signal with high precision. Further, since the digital circuit is used, high integration can be easily performed and the circuit scale can be reduced.

[0008]

However, in the above-described conventional configuration, a pulse signal with stable accuracy can be generated when there is no jitter in the vertical synchronization signal.
When the vertical synchronization signal has a jitter with respect to the horizontal synchronization signal, the jitter causes a sampling error due to the horizontal synchronization signal in the vertical address counter. As a result, a sampling error occurs at the reference position of the vertical synchronization, and the sampling occurs with the horizontal reference signal. Therefore, there is a problem that the jitter is further emphasized and a vertical pulse signal having a jitter in one horizontal period is output.

[0009]

In order to solve this problem, a timing generation circuit according to the present invention detects a reference edge of a vertical synchronizing signal when sampling a vertical synchronizing signal with a horizontal synchronizing signal. Generates a horizontal sampling pulse shifted from the vicinity of the edge by more than the amount of jitter,
The vertical synchronizing signal is first sampled by the sampling pulse to delay the vertical synchronizing signal. By sampling the delayed vertical synchronizing signal with the horizontal synchronizing signal, it is possible to cancel the jitter in one horizontal period of the vertical pulse signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A timing generating circuit according to a first aspect of the present invention, when digitally generating various vertical timing signals in an internal timing signal generator of a television receiver, first generates a vertical synchronizing signal. By detecting the reference position, sampling with an appropriate horizontal sampling pulse, and delaying it, the jitter of the vertical synchronizing signal is canceled and a stable vertical timing signal can be realized.

Next, the timing generator according to the second aspect of the present invention is characterized in that in detecting the reference position of the vertical synchronizing signal according to the first aspect, the horizontal synchronizing cycle is detected by a signal which is equally divided by a PLL circuit. This makes it possible to accurately detect the reference position of the vertical synchronization signal even if the horizontal synchronization frequency and the vertical synchronization frequency change.

According to a third aspect of the present invention, there is provided a timing signal generating apparatus for delaying a vertical synchronizing signal according to the first aspect of the present invention, wherein a horizontal synchronizing PLL circuit based on a reference position detection result according to the second aspect. It is characterized by delaying by sampling the vertical synchronizing signal by the created signal, and can realize an appropriate delay of the vertical synchronizing signal even if the horizontal synchronizing frequency and the vertical synchronizing frequency change. .

(Embodiment 1) An embodiment of the invention described in claim 1 of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram of a timing signal generator in a television receiver according to a first embodiment of the present invention. FIG. 2 is a timing signal diagram for explaining the operation of the first embodiment of the present invention. In FIG. 1, reference numeral 12 denotes a delay circuit that delays a vertical synchronization signal, 13 denotes a sampling signal generation circuit that generates a sampling signal for delaying the vertical synchronization signal, and 14 denotes an edge detection circuit that detects a reference edge of the vertical synchronization signal. In addition, the figure of the conventional example? Those which operate in the same manner as in the above are denoted by the same reference numerals and description thereof is omitted. FIG. 2 is a timing signal diagram for explaining the operation of the first embodiment of the present invention.

The operation of the timing generation circuit in the television receiver according to the present embodiment having the above-described configuration will be described below. First, sampling is performed with a horizontal synchronizing signal 1 as shown in FIG. 2B with reference to a vertical synchronizing signal 2 having a jitter as shown in FIG. 2A (a solid line is a regular waveform and a wavy line is a jitter). Accordingly, when the vertical address counter 6 is driven, a sampling error due to the horizontal synchronization signal 1 occurs due to the jitter of the vertical synchronization signal 2, and the reference of the vertical address counter 6 is set in one horizontal synchronization period as shown in FIG. It becomes big jitter. As a result, the vertical pulse 10 generated by the vertical address counter 6 has a large jitter component in one horizontal period.

Therefore, before inputting the vertical synchronizing signal 2 to the vertical address counter 6, the edge detecting circuit 14 detects the reference edge position of the vertical synchronizing signal 2 and generates a sampling signal based on the result of the reference edge position. Circuit 13
A waveform is created in which the phase of the waveform of FIG. 2B, which is the horizontal synchronizing signal 2 as shown in FIG. Next, in the delay circuit 12, sampling is first performed at a position where the jitter of the waveform of FIG. 2A, which is the vertical synchronizing signal 2, is not affected by the signal shown in FIG. Then, the vertical synchronization signal 2 is delayed, and a vertical synchronization reference waveform having no jitter shown in FIG. By sampling the vertical address counter 6 based on the vertical synchronization reference waveform with the horizontal synchronization signal 1 shown in FIG. 2B, a reset signal of the vertical address counter 6 shown in FIG. 2F is obtained. Can be A vertical pulse generator 7 based on the vertical address signal generated by the vertical counter 6 by the reset signal and the horizontal synchronization signal 2
Thus, various vertical pulses 10 are created.

According to this configuration, even if there is a jitter in the vertical synchronizing signal, when the vertical synchronizing signal is stable, sampling and delaying are performed first, and then a horizontal synchronizing signal is sampled to generate a vertical pulse signal. Can be canceled, and a stable vertical pulse signal can be obtained.

(Embodiment 2) An embodiment of the present invention described in claim 2 of the present invention will be described below with reference to FIGS.

FIG. 3 is a block diagram of the vertical synchronization reference edge position detection circuit. FIG. 4 is a timing signal diagram for explaining the operation of the second embodiment of the present invention.

In FIG. 3, reference numeral 15 denotes an edge detection signal generator for generating a signal for detecting a reference edge position of the vertical synchronization signal, and 16 denotes a horizontal synchronization signal of the edge of the vertical synchronization signal from the edge detection signal generator 15. A first edge detection circuit for detecting the vicinity of the reference position, a second edge detection circuit for detecting the vicinity of the edge of the vertical synchronizing signal and shifted by a half of the cycle of the horizontal synchronizing signal, and a first edge detecting circuit for the first edge detecting circuit. A discrimination circuit for discriminating an edge position based on a signal from the edge detection circuit and a signal from the second edge detection circuit. Components that operate in the same manner as FIG. 1 of the configuration example of the first embodiment and FIG. 7 of the conventional example are denoted by the same reference numerals, and descriptions of the operations are omitted.

A method for detecting the reference edge position of the vertical synchronizing signal will be described with reference to FIGS. First, a reference pulse and a clock signal synchronized with the horizontal synchronizing signal are obtained by driving the PLL circuit 3 from the horizontal synchronizing signal shown in FIG. The signal obtained in this way is input to the edge detection signal generation unit 15 and is divided by 1 / the cycle of the horizontal synchronization signal.
FIG. 4B shifted by 8 phases, FIG. 4C shifted by 3/8 phase, and FIGS. 4D and 7 shifted by 5/8 phase.
A signal (e) of FIG. 4 shifted by / 8 phase is created.

Next, when there is a vertical synchronizing signal having substantially the same phase as the reference position shown in FIG. 4A of the horizontal synchronizing signal as shown in FIG. When the synchronization signal is input to the detection circuit 16 and the synchronization signal is sampled from the signal (e) of FIG. 4 and the signal (a) of FIG. 4 which are the signals from the edge detection signal generation unit 15, 0 and 1 changes of the vertical synchronization signal can be detected. It can be detected that the reference edge of the vertical synchronizing signal is in the same phase as the horizontal synchronizing signal. Similarly, the horizontal synchronizing signal as shown in FIG.
When there is a vertical synchronizing signal with a phase shifted by １ ／ from the reference position, the signal is input to the second edge detecting circuit 17 and the signal from the edge detecting signal generating unit 15 shown in FIG. When the synchronization signal is sampled from the signal (d) in FIG. 4, a change of 0 or 1 of the vertical synchronization signal can be detected, and it can be detected that the edge of the vertical synchronization signal is located at a position shifted by half from the horizontal synchronization signal. . An edge position determination circuit 18 determines a reference edge position of the vertical synchronization signal based on the detection information from each of the edge detection units.

According to this configuration, since the horizontal PLL circuit 3 generates an edge detection signal and detects a vertical edge position, even if the horizontal frequency or the vertical frequency changes, the position of the reference edge of the vertical synchronizing signal is equal to the horizontal period. What percentage of the position can be detected accurately, and the reference edge position of the vertical synchronization signal can be detected accurately even if the phase of the vertical synchronization signal changes.

(Embodiment 3) An embodiment of the present invention described in claim 3 of the present invention will be described below with reference to FIGS.

FIG. 5 is a block diagram of a vertical synchronizing signal delay circuit of a timing signal generating circuit according to a third embodiment of the present invention. FIG. 6 is a timing signal diagram for explaining the operation of the third embodiment of the present invention. In FIG. 5, reference numeral 20 denotes a sample signal generator for generating a sample signal for delaying the vertical synchronization signal, and reference numeral 21 denotes a signal selection circuit for selecting a signal for delaying the vertical synchronization signal. 1 and 3 showing the configurations of the first and second embodiments.
7 which operate in the same manner as in FIG. 7 of the conventional embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The vertical synchronizing signal delay circuit will now be described with reference to FIGS. First, by driving the PLL circuit 3 from the horizontal synchronization signal shown in FIG. 6A, a reference pulse and a clock signal synchronized with the horizontal synchronization signal 2 are obtained. The obtained signal is input to the sample pulse signal generator 20 to generate a signal shown in FIG. 6B in which the phase of the horizontal synchronizing signal is shifted by １ ／ phase, and a signal shown in FIG. 6C having the same phase. Next, when there is a vertical synchronizing signal having substantially the same phase as the reference position shown in FIG. 6A of the horizontal synchronizing signal as shown in FIG. The information that the phase is the same as that of the synchronizing signal is obtained, and a signal for delaying the vertical synchronizing signal 2 by the signal selection circuit 21 is selected from the signals from the sample signal generator 20 as shown in FIG. And outputs it to the delay circuit 12. First, the vertical synchronizing signal 2 is sampled by the delay circuit 12 using the signal, and the jitter of the vertical synchronizing signal can be canceled by sampling the position without being affected by the jitter of the vertical synchronizing signal.

Similarly, when there is a vertical synchronizing signal 2 whose phase is shifted by 1/2 from the reference position shown in FIG. 6A of the horizontal synchronizing signal as shown in FIG. (C) The jitter can be canceled by first sampling the signal.

According to this configuration, the reference edge position of the vertical synchronizing signal is automatically detected, and sampling is first performed with the vertical synchronizing signal using the optimum sampling signal generated by the horizontal PLL circuit, whereby the stable vertical synchronizing signal is obtained. And the jitter of the reference edge of the vertical synchronizing signal can be accurately and stably canceled even if the horizontal frequency and the vertical frequency change.

In the first, second, and third embodiments, the input synchronization signal of the television receiver has been described for easy understanding, but the deflection synchronization signal inside the television receiver is also described. Needless to say, it is effective.

[0030]

According to the present invention, even when the vertical synchronizing signal has a jitter with respect to the horizontal synchronizing signal and the phase of the vertical synchronizing signal changes, an optimum horizontal sampling pulse signal is detected by detecting the reference edge of the vertical synchronizing signal including the jitter. First, the vertical synchronizing signal is sampled, delayed, and then sampled by the horizontal synchronizing signal, thereby canceling the jitter of the vertical synchronizing signal. As described above, the vertical synchronizing signal is sampled by the horizontal synchronizing signal, so that the jitter of various vertical timing signals can be canceled, and a digital timing generating circuit for generating a more stable vertical pulse signal can be realized. The same can be realized when the horizontal and vertical frequencies change.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a timing generator in a television receiver according to a first embodiment of the present invention.

FIG. 2 is a timing signal diagram for explaining the operation of the block diagram.

FIG. 3 is a block diagram illustrating a vertical synchronization reference edge position determination circuit according to a second embodiment of the present invention;

FIG. 4 is a timing signal diagram for explaining the operation of the block diagram;

FIG. 5 is a block diagram showing a vertical synchronization delay circuit according to a third embodiment of the present invention;

FIG. 6 is a timing signal diagram for explaining the operation of the block diagram.

FIG. 7 is a diagram showing a timing generation circuit diagram in a conventional television receiver.

[Explanation of symbols]

 Reference Signs List 1 horizontal synchronization signal 2 vertical synchronization signal 3 PLL circuit 4 horizontal address counter 5 horizontal pulse generation circuit 6 vertical address counter 7 vertical pulse generation circuit 8 horizontal / vertical pulse synthesis circuit 9 horizontal pulse 10 vertical pulse 11 horizontal / vertical pulse 12 delay circuit 13 Sampling signal generation circuit 14 Edge detection circuit 15 Edge detection signal generation unit 16 Edge 1 detection circuit 17 Edge 2 detection circuit 18 Edge position discrimination signal 19 Discrimination signal 20 Sample signal generation unit 21 Signal selection circuit

Claims (3)

[Claims] 1. A means for sampling a vertical synchronizing signal of a video signal with a horizontal synchronizing signal; a means for detecting a reference edge of the vertical synchronizing signal; A television which comprises: means for delaying a vertical synchronization signal by means of a video signal; means for generating a signal for delaying the vertical synchronization signal; and means for generating a timing signal based on a vertical signal of a video signal. John receiver. 2. The television receiver according to claim 1, wherein the reference edge of the vertical synchronization signal is detected by a pulse obtained by dividing one cycle of the horizontal synchronization signal. 3. The vertical synchronizing signal according to claim 1, wherein the delay means generates a horizontal sampling signal having a phase shifted from the horizontal synchronizing signal, and delays the vertical synchronizing signal by sampling the vertical synchronizing signal. Television receiver.