JPH11136596A - Television image receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a stable vertical synchronizing timing signal by detecting the reference position of the vertical synchronizing signal, and making an interlace/progressive(IP) decision on an input signal and then generating proper horizontal sampling pulses, and sampling and delaying the vertical synchronizing signal. SOLUTION: A delay circuit 12 delays a vertical synchronizing signal 2, whereas a sampling signal generating circuit 13 generates a sampling signal for delaying the vertical synchronizing signal 2. Then when the vertical synchronizing signal 2 is sampled with a horizontal synchronizing signal 1, an edge detecting circuit 14 detects the reference edge of the vertical synchronizing signal 2. Further, an I/P decision circuit 22 determines whether or not the input signal is an interlaced signal or progressive signal. According to the edge detection result and I/P decision result, horizontal sampling pulses which are shifted from nearby the reference edge by more than a jitter quantity are generated and the vertical synchronizing signal 2 is sampled first to delay the vertical synchronizing signal 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing signal generating circuit (International Patent Classification H04N9 / 28) in a color television receiver.

[0002]

2. Description of the Related Art Generally, in a color television receiver, in order to perform internal signal processing, various horizontal pulse signals having different phases synchronized with a horizontal synchronization signal and various vertical pulses having different phases synchronized with a vertical synchronization signal are used. I use a lot of signals. In order to create these pulse signals, pulses with different phases are created using analog delay elements based on the video horizontal and vertical synchronization signals, but there are problems with accuracy, stability, and circuit scale. There is. Therefore, as a method for solving the above problem, a timing generation circuit by digital signal processing that can operate stably with high accuracy and can reduce the circuit scale by high integration has been proposed.

An example of a conventional timing generation circuit when a signal input to a television receiver is a progressive signal will be described below with reference to the drawings. FIG. 9 shows a block diagram of a conventional timing generation circuit. This is a circuit for generating various vertical pulse signals and horizontal pulse signals used in the television receiver from horizontal and vertical synchronization signals of a video signal.

In FIG. 9, 1 is a horizontal synchronization signal, 2 is a vertical synchronization signal, 3 is a horizontal synchronization PLL circuit, 4 is a horizontal address counter, 5 is a horizontal pulse generator, 6 is a vertical address counter, and 7 is a vertical pulse. A generation unit, 8 is a mixing circuit for horizontal and vertical pulses, 9 is a horizontal pulse signal created from a horizontal synchronization signal, 10 is a vertical pulse signal created from a vertical synchronization signal, and 11 is the horizontal pulse signal and the vertical pulse signal. Is a horizontal / vertical pulse signal created from.

A horizontal synchronizing signal 1 synchronized with a video signal
Is input to the horizontal PLL circuit 3, which
A clock signal and a horizontal reference signal synchronized with the horizontal synchronization signal 1 are output from the circuit, and the horizontal address counter 4 is driven by the clock signal and the horizontal reference signal. The horizontal address signal output from the horizontal address counter 4 is supplied to the horizontal pulse signal generating circuit 5 to synchronize with the horizontal synchronizing signal and to shift the phase accurately in the clock unit generated from the horizontal PLL circuit 3. Horizontal pulse signal 9
Create

The vertical synchronization signal 2 is input to a vertical address counter 6 as a reference signal. Then, by inputting the horizontal synchronizing signal 1 as a clock signal, the vertical address counter 6 generates a vertical address signal corresponding to the scanning line of the video signal. By supplying the vertical address signal to the vertical pulse generation circuit 7, a stable vertical pulse signal whose phase is accurately shifted for each scanning line is created. The horizontal / vertical signal obtained by combining the horizontal pulse signal and the vertical pulse signal is also created by the horizontal / vertical pulse mixing circuit 8.

The timing generation circuit based on the digital circuit in the case where the input signal is a progressive signal has been described above. In the case of the interlace signal, a double horizontal synchronizing signal becomes a clock signal for generating a vertical pulse and becomes a vertical scanning in units of 1/2 scanning line. It goes without saying that a pulse is created.

[0008] In this way, by digitally sampling various pulse signals synchronized with the horizontal synchronizing signal and the vertical synchronizing signal used in the television receiver, it is possible to stably produce the signal accurately and stably. Further, since the digital circuit is used, high integration can be easily performed and the circuit scale can be reduced.

[0009]

However, in the above-described conventional configuration, a pulse signal with stable accuracy can be generated when there is no jitter in the vertical synchronization signal.
If the vertical synchronization signal has a jitter with respect to the horizontal synchronization signal, the progressive signal causes a sampling error due to the horizontal synchronization signal in the vertical address counter due to the jitter. As a result, a sampling error occurs at the reference position of the vertical synchronization signal. Since the signal is sampled, the jitter is further emphasized, and a vertical pulse signal having a jitter of one horizontal period is output.
In addition, since the interlaced signal is sampled by the double horizontal synchronizing signal, there is a problem that a vertical pulse signal having a jitter of 1/2 horizontal period is output.

[0010]

In order to solve this problem, a timing generation circuit according to the present invention detects a reference edge of a vertical synchronizing signal when sampling a vertical synchronizing signal with a horizontal synchronizing signal, and detects an input signal. It is determined whether the signal is an interlace signal or a progressive signal (hereinafter referred to as I / P determination), and a horizontal sampling pulse shifted from the vicinity of the reference edge by the amount of jitter or more is generated in accordance with the edge detection result and the I / P determination. First, the vertical synchronization signal is sampled first to delay the vertical synchronization signal. By delaying the vertical sync signal from the sampling point of the horizontal sync signal, which is the clock signal, to a phase where jitter does not become a problem, sampling errors of the vertical sync signal serving as a reference for vertical pulse generation are eliminated, and the vertical sync signal and the horizontal It is possible to cancel the jitter of the vertical pulse signal created by the synchronization signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A timing generating circuit according to a first aspect of the present invention, when digitally generating various vertical timing signals in an internal timing signal generator of a television receiver, first generates a vertical synchronizing signal. A stable vertical timing signal is realized by detecting a reference position, creating an appropriate horizontal sampling pulse by I / P discrimination of the input signal, sampling and delaying the vertical synchronization signal and canceling the jitter of the vertical synchronization signal. It is a good thing.

In the timing generator according to a second aspect of the present invention, in detecting the reference position of the vertical synchronizing signal according to the first aspect, the horizontal synchronizing cycle is detected by a signal equally divided by a PLL circuit. In the circuit for delaying the vertical synchronization signal, a vertical synchronization signal is sampled by a signal generated by a horizontal synchronization PLL circuit based on the reference position detection and the I / P determination result. Even if the frequency and the vertical synchronization frequency change, an appropriate delay of the vertical synchronization signal can be realized.

According to a third aspect of the present invention, there is provided a timing generation device, wherein the I / P determination according to the first aspect is an input signal determination and data stored in a memory provided in the receiver, which is preset in advance. It is characterized by the fact that even if the input signal changes, the vertical sync signal is sampled with an appropriate horizontal sampling pulse and delayed, thereby canceling the jitter of the vertical sync signal and stabilizing the vertical signal. A timing signal can be realized.

In the timing generator according to a fourth aspect of the present invention, the I / P discrimination according to the first aspect detects an edge of each field of a vertical synchronizing signal by a signal obtained by equally dividing a horizontal synchronizing cycle by a PLL circuit. Even if the input signal changes, the vertical synchronization signal is sampled and delayed with an appropriate horizontal sampling pulse to cancel the jitter of the vertical synchronization signal and realize a stable vertical timing signal. It is possible.

(Embodiment 1) An embodiment of the invention described in claim 1 of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram of a timing signal generator in a television receiver according to a first embodiment of the present invention. FIGS. 2 and 3 are timing signal diagrams for explaining the operation of the first embodiment of the present invention. In FIG. 1, reference numeral 12 denotes a delay circuit for delaying a vertical synchronization signal,
Reference numeral 3 denotes a sampling signal generating circuit for generating a sampling signal for delaying the vertical synchronizing signal, 14 denotes an edge detecting circuit for detecting a reference edge of the vertical synchronizing signal, and 22 denotes an I for determining whether the input signal is an interlace signal or a progressive signal. / P determination circuit.

Elements operating in the same manner as in FIG. 9 of the conventional embodiment are denoted by the same reference numerals, and description thereof is omitted. FIG. 2 is a timing signal diagram for explaining the operation of the first embodiment of the present invention when an interlace signal is input. FIG. 3 is a timing signal diagram for explaining the operation of the first embodiment of the present invention when a progressive signal is input.

The operation of the timing generation circuit in the television receiver of this embodiment having the above-described configuration will be described below. First, the I / P determination unit 22 determines whether the input signal is an interlace signal or a progressive signal. Based on the result, a signal generated by the sampling signal generating circuit 13 is selected, and a delay amount of the delay circuit 12 for delaying the vertical synchronizing signal is controlled.

First, the case where an interlace signal is input will be described with reference to FIG. (A), (b) of FIG.
As shown in FIG. 2D, there is a jitter having a time width of t0 having a phase difference of 水平 horizontal period for each field (solid line is a normal waveform and wavy line is a jitter) as shown in FIG. When the vertical address counter 6 is driven by sampling with a signal twice as large as the horizontal synchronization signal 1, as shown in FIG. The reference of the counter 6 becomes a large jitter in a 1/2 horizontal period. As a result, the vertical address counter 6
Has a large jitter component in a 1/2 horizontal period.

Therefore, before inputting the vertical synchronizing signal 2 to the vertical address counter 6, the edge detecting circuit 14 detects the reference edge position of the vertical synchronizing signal 2 and generates a sampling signal based on the result of the reference edge position. Circuit 13
A waveform is generated by shifting the phase t1 of the waveform of FIG. 2D, which is a signal twice as large as the horizontal synchronization signal 2 as shown in FIG. Next, in the delay circuit 12, the jitter of the waveforms of FIGS. 2A and 2B, which are the vertical synchronizing signal 2, is not affected by the signal shown in FIG. 2E created by the sampling signal generating circuit 13. First, the vertical synchronization signal 2 is sampled at the position to delay the vertical synchronization signal 2 to create the jitter-free vertical synchronization reference waveform shown in FIGS.

By sampling the vertical address counter 6 on the basis of this vertical synchronization reference waveform with a signal twice as large as the horizontal synchronization signal 1 in FIG. 2C, as shown in FIG. 2D. (H) and (i) reset signals of the vertical address counter 6 are obtained. The vertical pulse generator 7 generates various vertical pulses 10 based on the vertical address signal generated by the vertical counter 6 based on the reset signal and the horizontal synchronization signal 2. Here, from FIG. 2, the conditions for canceling the jitter are as follows: t0 <t1 (t1 = sampling signal phase delay amount) t0 <t2 (t2 = tH / 2−t0) t1 + t2 = tH / 2 (th = horizontal scanning period) . Therefore, the condition for the maximum jitter amount t0 is t1 = t2 = tH / 4.

As described above, the vertical synchronization signal is first sampled with a signal whose phase is delayed by t1 = tH / 4, thereby canceling the jitter of the vertical synchronization signal whose jitter amount t0 satisfies t0 <th / 4. Can do things.

Next, the case where the input signal is a progressive signal will be described with reference to the timing chart of FIG. Needless to say, the period of the vertical synchronizing signal of the progressive signal is one horizontal synchronizing signal period as shown in FIG. 3A. Therefore, the sampling pulse for generating the vertical timing pulse is shown in FIG. The horizontal synchronization signal shown in FIG. Here, assuming that the jitter of the vertical synchronizing signal in the progressive signal is t3, as in the case of the above-described interlace signal, FIG.
As shown, t3 <t4 (t4 = sampling signal phase delay amount) t3 <t5 (t5 = tH−t3) t4 + t5 = tH Therefore, the condition of the maximum value of the jitter amount t3 is t4 = t5 = tH / 2.

As described above, the vertical synchronization signal is first sampled with a signal whose phase is delayed by t4 = tH / 2, so that the jitter of the vertical synchronization signal whose jitter amount t3 satisfies t3 <th / 4 can be canceled. it can.

As described above, the maximum jitter amount tH / 4 for an interlaced signal and the maximum jitter amount t for a progressive signal
Since it is possible to cancel H / 2 jitter,
In the case of a progressive signal, it is possible to cancel twice the jitter of the interlace signal.

With this configuration, even if there is a jitter in the vertical synchronizing signal, sampling and delaying are performed first when the vertical synchronizing signal is stable in accordance with the interlace signal and the progressive signal, and then the horizontal synchronizing signal is sampled and the vertical pulse is sampled. By creating a signal, the amount of jitter cancellation can be maximized for each signal, and a more stable vertical pulse signal can be obtained.

(Embodiment 2) An embodiment of the present invention described in claim 2 of the present invention will be described below with reference to FIGS.

FIG. 4 is a block diagram of the vertical synchronizing signal delay circuit. FIG. 5 is a timing signal diagram for explaining the operation of the second embodiment of the present invention.

In FIG. 4, reference numeral 15 denotes an edge detection signal generator for generating a signal for detecting a reference edge position of the vertical synchronization signal, and 16 denotes a horizontal synchronization signal of the edge of the vertical synchronization signal from the edge detection signal generator 15. A first edge detection circuit for detecting the vicinity of the reference position, a second edge detection circuit for detecting the vicinity of the edge of the vertical synchronizing signal and shifted by a half of the cycle of the horizontal synchronizing signal, and a first edge detecting circuit for the first edge detecting circuit. A determination circuit for determining an edge position based on a signal from the edge detection circuit and a signal from the second edge detection circuit; 19, a vertical edge position signal; and 20, a sample signal for generating a sample signal for delaying a vertical synchronization signal The generator 21 is a signal selection circuit for selecting a signal for delaying the vertical synchronization signal. Components operating in the same manner as FIG. 1 of the configuration example of the first embodiment and FIG. 9 of the conventional example are denoted by the same reference numerals,
The description of the operation is omitted.

First, an interlaced signal will be described with reference to FIGS. The I / P discriminating unit creates a signal twice as large as the horizontal synchronization signal shown in FIG. 5B from the horizontal synchronization signal shown in FIG. 5A based on the information that the input signal is an interlace signal.

Next, a method for detecting the reference edge position of the vertical synchronizing signal will be described. First, by driving the PLL circuit 3 from the horizontal synchronization signal shown in FIG. 5A, a reference pulse and a clock signal synchronized with the horizontal synchronization signal are obtained. The signal thus obtained is converted to an edge detection signal generator 1
5, (c) in FIG. 5 in which the phase of the horizontal synchronization signal is shifted by 1/8 phase, and (e) in FIG. 5 in which the phase is shifted by 3/8.
5 (g) of FIG. 5 in which the phase is shifted by 5/8, and FIG. 5 (i) in which the phase is shifted by 7/8. In the sample signal generating section, the signal shown in FIG. 5D shifted by 2/8 phase, the signal shown in FIG. 5F shifted by 4/8 phase, and the signal shown in FIG. 5H shifted by 6/8 phase are generated. I do.

Next, when there is a vertical synchronizing signal having almost the same phase as the reference position shown in FIG. 5 (b) of a signal twice as large as the horizontal synchronizing signal as shown in FIGS. 5 (j) and (k), In the first edge detection circuit 16, the vertical synchronizing signal is supplied from the edge detection signal generation unit 15 in FIG.
By sampling the synchronizing signal from the signal (c), it is possible to detect a change of 0 or 1 in the vertical synchronizing signal, and it is possible to detect that the reference edge of the vertical synchronizing signal is substantially in the same phase as the horizontal synchronizing signal.

Since the signal is an interlace signal, a horizontal synchronizing signal as shown in FIG.
Since the vertical synchronization signal has a phase shifted by １ ／ from the reference position, the second edge detection circuit 17 outputs the signal from the edge detection signal generation unit 15 in FIG. (G) By sampling the synchronizing signal from the signal, it is possible to detect a change of 0 or 1 of the vertical synchronizing signal, and it is possible to detect that the edge of the vertical synchronizing signal is located at a position shifted by half from the horizontal synchronizing signal.

The reference edge position of the vertical synchronizing signal is a clock signal for generating a vertical pulse in the edge position discriminating circuit 18 based on the detection information from each of the edge detectors.
5D and FIG. 5H that the sampling pulse in the delay circuit 12 is determined by the sampling signal generation unit 20 by determining that it is near the edge of the signal twice as large as the horizontal synchronization signal shown in FIG. And the delay circuit 12 delays the vertical synchronizing signal by the amount of tH / 4. When the edge position is not detected by the edge position detection circuit 18, the sampling pulse of the delay circuit 12 is
FIG. 5B, which is a vertical pulse generation clock, is selected by the signal selection circuit 21, and the vertical synchronization signal is not delayed with respect to the clock signal. Jitter at the time of an interlace signal of the vertical synchronization signal can be canceled by sampling the vertical synchronization signal 2 at the maximum position where the jitter is not affected by the delay circuit 12 according to the phase of the input signal.

The operation at the time of the progressive signal is the same as that at the time of the interlace signal, except that the edge detection is performed only by the result of the edge detection circuit 16, and the vertical pulse generation clock is the horizontal synchronization signal shown in FIG. Also delay
FIG. 5F shows that the sampling pulse of the circuit 12 is such that the delay amount of the vertical synchronizing signal is tH / 2.

According to this configuration, since the horizontal PLL circuit 3 creates an edge detection signal and detects the vertical edge position, even if the horizontal frequency or the vertical frequency changes, the position of the reference edge of the vertical synchronizing signal is determined by the horizontal period. %, And the reference edge position of the vertical synchronization signal can be accurately detected even if the phase of the vertical synchronization signal changes. Also, by detecting the reference edge position and first sampling the vertical synchronization signal with the optimal sampling signal created by the horizontal PLL circuit, a stable maximum delay of the vertical synchronization signal can be realized, and the horizontal frequency and the vertical frequency have changed. Thus, the jitter of the reference edge of the vertical synchronization signal can be accurately and stably canceled.

(Embodiment 3) An embodiment of the present invention described in claim 3 of the present invention will be described below with reference to FIG.

FIG. 6 is a block diagram of an I / P determination circuit according to the third embodiment of the present invention. In FIG. 6, 2
4 is an input signal, 25 is a synchronization type discrimination circuit, 26 is a frequency discrimination circuit for detecting horizontal and vertical synchronization signals, 27 is a polarity discrimination circuit for detecting polarities of horizontal and vertical synchronization signals, 28
Is an external signal, 29 is a SW discriminating circuit for discriminating a switcher number, 30 is a control panel for external control, 31 is a CPU as a microprocessor, and 32 is a nonvolatile memory. Embodiment 1 and Embodiment 2
1 and 3 showing the configuration of FIG. 1 and those of FIG. 9 of the conventional embodiment which are operated in the same manner as those of FIG. 9 are denoted by the same reference numerals and their description is omitted.

First, the input signal determination will be described with reference to FIG. In particular, since signals input to a television receiver called a multi-scan display are various and various, all kinds of information of the signals are required to determine various input signals. Therefore, the synchronization mode of the input signal is first determined by the synchronization mode determination circuit 25 to be sync-onG, separate SY.
NC, composite SYNC, etc. are detected. Next, the frequencies of the horizontal synchronization signal and the vertical synchronization signal are detected by a synchronization frequency determination circuit. Further, the synchronization polarity discrimination circuit discriminates whether the horizontal synchronization signal and the vertical synchronization signal at the time of the separate SYNC are positive polarity / negative polarity, and determines the details of the input signal. However, when the information is all the same but different input signals are present, the external signal 28 is used and the information of the external switcher or the like in which the input signal is switched is also determined by the SW determination circuit 29 to further determine the signal. Do.

The result of the input signal and the setting of the I / P switching from the control panel 30 are determined by the CPU according to each signal.
Preset in the non-volatile memory via 31. Here, when a preset signal is inputted, the input signal is discriminated by detecting the input signal information, and the CPU 31 reads out the I / P discrimination data from the nonvolatile memory and sets it in the jitter cancel circuit.

According to such a configuration, even if various signals are input, signal discrimination is performed and the previously stored I / P
By setting the discrimination signal in the jitter cancel circuit, a stable delay of the vertical synchronization signal can be realized, and the jitter of the reference edge of the vertical synchronization signal can be accurately and stably canceled.

(Embodiment 4) An embodiment of the invention described in claim 4 of the present invention will be described below with reference to FIGS.

FIG. 7 is a block diagram of an I / P determination circuit according to the fourth embodiment of the present invention.

FIG. 8 is used for a timing signal diagram for explaining the operation of the fourth embodiment of the present invention.

In FIG. 7, reference numeral 33 denotes an I / P detection circuit for detecting whether the signal is an interlace signal or a progressive signal. Embodiment 1, Embodiment 2, Embodiment 3
1 and 4 showing the structure of FIG. 1 and those of FIG. 9 of the conventional embodiment which are operated in the same manner as those of FIG. 9 are denoted by the same reference numerals and the description thereof will be omitted.

First, the I / P determination circuit will be described with reference to FIGS. 8 (c) to 8 (c) as in the second embodiment.
From the horizontal synchronization signal up to (i), a signal delayed in phase from １ ／ to ／ is obtained from the edge detection signal generation unit 15. First, when the edge of the first vertical synchronizing signal is in phase with the horizontal synchronizing signal of FIG. 8A as shown in FIG.
The edge detection circuit 16 according to the signals (i) and (c) of FIG.
Detects the edge of the vertical synchronizing signal.

Next, the information on the detected edge position is determined by an edge position determination circuit 18 and this determination signal is
/ P detection circuit 33 and the edge detection circuit 17
The circuit 17 operates so that a signal delayed by ２ phase with respect to the signal detected by the edge detection circuit 16 becomes a signal for edge detection. Edge detection circuit 17 at this time
Are the 3/8 phase delay signal shown in FIG. 8 (e) and the 5/8 phase delay signal shown in FIG. 8 (g). If the input signal is an interlace signal, the edge of the vertical synchronizing signal is detected by the edge detecting circuit 17 because the vertical synchronizing signal comes to a position delayed by a half phase of the horizontal synchronizing signal as shown in FIG. Is detected and sent to the I / P detection circuit 33 through the edge position determination circuit 18.

The I / P discriminating circuit 33 discriminates an interlaced signal when the edge is shifted by a 1/2 horizontal phase period for each vertical synchronizing signal based on the result of the vertical synchronizing signal and the edge position discriminating circuit 18. A jitter cancel circuit is sent as the discrimination signal 23. Also, at the time of the progressive signal, when the edge of the vertical synchronization signal is detected by the edge detection circuit 16 and not detected by the edge detection circuit 17,
The I / P determination circuit 33 can easily determine the interlace signal.

Further, the edge detection of the edge detection circuit 16 is made the same phase as the horizontal synchronization signal. It goes without saying that edge detection is performed using a signal delayed by two horizontal phases. As described above, the I / P signal determination can be easily realized by making the edge detection circuits 16 and 17 shift to an edge detection signal shifted by 水平 horizontal period.

According to this configuration, even if various signals are input, an edge detection signal is created by the horizontal PLL circuit, and the horizontal frequency or the vertical frequency is changed to detect the vertical edge position for each vertical synchronization signal. By accurately detecting what percentage of the horizontal period the reference edge position of the vertical synchronization signal is, and automatically performing an I / P discrimination signal and setting the jitter cancellation circuit, a stable vertical synchronization signal delay can be achieved. It is possible to accurately and stably cancel the jitter of the reference edge of the vertical synchronization signal.

In the first, second, third, and fourth embodiments, the input synchronization signal of the television receiver has been described for easy understanding. However, the deflection synchronization inside the television receiver is described. It goes without saying that the signal is also effective.

[0052]

According to the present invention, even when the vertical synchronizing signal has a jitter with respect to the horizontal synchronizing signal and the phase of the vertical synchronizing signal is changed, the reference edge of the vertical synchronizing signal including the jitter is detected to determine the interlace signal / progressive signal. Then, the vertical synchronizing signal is sampled with an optimal horizontal sampling pulse signal, delayed, and then sampled with the horizontal synchronizing signal, thereby canceling the jitter of the vertical synchronizing signal. As described above, the vertical synchronizing signal is sampled by the horizontal synchronizing signal in accordance with the various signals, the jitter of the various vertical timing signals can be canceled, and a digital timing generating circuit that creates a more stable vertical pulse signal can be realized. is there.

The same can be realized when the horizontal and vertical frequencies change.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a timing generator in a television receiver according to a first embodiment of the present invention.

FIG. 2 is a timing signal diagram for explaining the operation of the block diagram.

FIG. 3 is a timing signal diagram for explaining the operation of the block diagram;

FIG. 4 is a block diagram illustrating a vertical synchronization reference edge position determination circuit according to a second embodiment of the present invention;

FIG. 5 is a timing signal diagram for explaining the operation of the block diagram.

FIG. 6 is a diagram showing a block diagram of I / P determination according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating an I / P determination circuit according to a fourth embodiment of the present invention.

FIG. 8 is a timing signal diagram for explaining the operation of the block diagram.

FIG. 9 is a diagram showing a timing generation circuit diagram in a conventional television receiver.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 horizontal synchronization signal 2 vertical synchronization signal 3 PLL circuit 4 horizontal address counter 5 horizontal pulse generation circuit 6 vertical address counter 7 vertical pulse generation circuit 8 horizontal / vertical pulse synthesis circuit 9 horizontal pulse 10 vertical pulse 11 horizontal / vertical pulse 12 delay circuit 13 Sampling signal generation circuit 14 Edge detection circuit 15 Edge detection signal generation unit 16 Edge 1 detection circuit 17 Edge 2 detection circuit 18 Edge position determination signal 19 Determination signal 20 Sample signal generation unit 21 Signal selection circuit 22 I / P determination circuit 23 I / P discrimination signal 24 input signal 25 synchronization form discrimination circuit 26 synchronization frequency detection circuit 27 synchronization polarity detection circuit 28 external signal 29 external control detection circuit 30 control panel 31 CPU 32 nonvolatile memory 33 I / P detection circuit

Claims (4)

[Claims] 1. A means for sampling a vertical synchronizing signal of a video signal with a horizontal synchronizing signal; a means for detecting a reference edge of the vertical synchronizing signal; Means for delaying the vertical synchronizing signal, means for determining whether the video signal is an interlace signal or a progressive signal, means for generating a signal for delaying the vertical synchronizing signal based on the result of the determination, Means for generating a timing signal based on the signal. 2. The means for delaying generates a horizontal sampling signal from a pulse obtained by dividing one cycle of a horizontal synchronization signal whose phase is shifted from a reference edge of the horizontal synchronization signal,
2. The television receiver according to claim 1, wherein the vertical synchronization signal is delayed by sampling a vertical synchronization signal by the horizontal sampling signal. 3. A means for determining whether a video signal is an interlace or a progressive signal reads and determines data stored in a memory inside a receiver for each input signal based on a result of the input signal determination. Claim 1
The television receiver as described. 4. The television according to claim 1, wherein the means for determining whether the video signal is an interlace or a progressive signal determines an edge of the vertical synchronization signal by a pulse obtained by dividing one cycle of the horizontal synchronization signal. Receiver.