JP2846858B2 - 2D / 3D video converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
More particularly, the present invention relates to a two-dimensional / three-dimensional video converter that generates a three-dimensional video signal at twice the normal speed from a two-dimensional video.

[0002]

2. Description of the Related Art From a two-dimensional video, a first video signal serving as a reference and a second video signal delayed with respect to the first reference video signal are generated, one of which is used as a left-eye video signal, Is used as the right-eye video signal, so that the two-dimensional
2. Description of the Related Art A two-dimensional / three-dimensional video conversion device for converting a video into a two-dimensional video is known.

As the first video signal, an original two-dimensional video signal is generally used as it is. The amount of delay of the second video signal with respect to the first video signal is determined according to the speed of the video motion of the two-dimensional video signal. The second video signal is generated as follows.

That is, a predetermined number of past fields from the latest field of the two-dimensional video signal input to the two-dimensional / three-dimensional video conversion are stored in a plurality of field memories on a field-by-field basis. Then, from the two-dimensional video signals stored in each field memory, a two-dimensional video signal corresponding to the delay amount determined according to the speed of the video motion of the two-dimensional video signal is read. The two-dimensional video signal read from the field memory is the second video signal. The left-eye video signal and the right-eye video signal obtained in this way are converted to a speed twice as fast as the normal speed in order to prevent flicker.

FIG. 4 shows a configuration of a conventional two-dimensional / three-dimensional video converter for generating a double-speed three-dimensional video signal from a two-dimensional video signal.

[0006] The two-dimensional / three-dimensional video converter is an integrated circuit (L) for converting a two-dimensional video signal into a three-dimensional video signal.
SI) 100, a plurality of delay field memories 200 connected to the integrated circuit 100, and a speed-doubling circuit 300 for doubling the frequency of the left-eye video signal and the right-eye video signal output from the integrated circuit 100. It is composed of

FIG. 4 shows only components related to writing data to the delay field memory 200 and reading data from the delay field memory 200 as components of the integrated circuit 100. That is, the components of the integrated circuit 100 include the write-side data path 101 and the write-system timing generator 10.
2, a read-side data path 103 and a read-system timing generator 104 are shown. The integrated circuit 100
In addition to these components, a motion vector detection unit, an interface connected to the CPU, and the like are provided.

The write timing generator 102 and the read timing generator 104 have a reference clock signal CLK generated based on a horizontal synchronization signal HSYNC of a two-dimensional video signal and a vertical synchronization signal VSY of a two-dimensional video signal.
NC, a horizontal synchronizing signal HD generated by the reference clock signal CLK based on the horizontal synchronizing signal HSYNC is input. Frequency f _CLK of the reference clock signal CLK, when the frequency of the horizontal synchronizing signal HD and f _H, and has a frequency expressed by the following Equation 1.

[0009]

(Equation 1)

The integrated circuit 100 receives a luminance signal (Y signal) and a color difference signal (RY signal and BY signal) constituting a two-dimensional video signal. The integrated circuit 100 outputs a right-eye video signal and a left-eye video signal having a relative time difference. The right-eye video signal includes a right-eye luminance signal Y (R), a right-eye color difference signal RY (R), and a right-eye color difference signal BY (R). The left-eye video signal includes a left-eye luminance signal Y (L) and a left-eye color difference signal RY.
(L) and a left-eye color difference signal BY (L).

One of the right-eye video signal and the left-eye video signal is based on a signal obtained by transmitting a two-dimensional video signal input to the integrated circuit 100 to the read data path 103 via the write data path 101. Generated. The other of the right-eye video signal and the left-eye video signal is a signal obtained by transmitting the two-dimensional video signal input to the integrated circuit 100 to the read-side data path 103 via the write-side data path 101 and the delay field memory 200. Generated based on

Field memory 2 for Y, RY, and BY signals input to write-side data path 101
Writing to 00 is performed according to the reference clock signal CLK. That is, the delay field memory 200
The frequency of the write clock to the reference clock signal C
It is the frequency f _CLK of LK.

The reading of the signal stored in the field memory 200 is also performed according to the reference clock signal CLK. That is, the frequency of the read clock of the delay field memory 200 is also the frequency f _CLK of the reference clock signal CLK.

Therefore, the right-eye luminance signal Y (R) and the right-eye color difference signal RY output from the integrated circuit 100 are output.
(R), the horizontal and vertical frequencies of the right-eye color difference signal BY (R), the left-eye luminance signal Y (L), the left-eye color difference signal RY (L), and the left-eye color difference signal BY (L) Is the same as the horizontal and vertical frequencies of the two-dimensional video signal.

The speed doubling circuit 300 outputs a right-eye luminance signal Y (R) and a right-eye color difference signal R output from the integrated circuit 100.
-Y (R), right-eye color difference signal BY (R), left-eye luminance signal Y (L), left-eye color difference signal RY (L), and left-eye color difference signal BY (L), respectively. Double-speed field memories 301 to 306 for storing, double-speed field memory write timing generation circuit 307 for controlling writing of data to these double-speed field memories 301 to 306, and double-speed field memory 30
A double-speed field memory read timing generation circuit 308 for controlling reading of data from 1 to 306 is provided.

When the right-eye video signal is read,
From the double-speed field memory 301, the right-eye luminance signal Y
(R) is read, the right-eye color difference signal RY (R) is read from the double-speed field memory 302, and the right-eye color difference signal BY (R) is read from the double-speed field memory 303.
Is read. When the left-eye video signal is read, the left-eye luminance signal Y (L) is read from the double-speed field memory 304, and the double-speed field memory 305 is read.
, The left-eye color difference signal RY (L) is read from the double-speed field memory 306.
(L) is read.

A reference clock signal CLK is input to the double-speed field memories 301 to 306 and the double-speed field memory write timing generation circuit 307 as a write clock. Field memory 30 for double speed
1 to 306 and the double-speed field memory read timing generation circuit 308 receive a clock signal C having a frequency twice as high as the reference clock signal CLK as a read clock.
LKa is input.

[0018] That is, the frequency f _CLKa of the read clock signal CLKa, as shown in Equation 2 is twice the frequency f _CLK of the write clock signal CLK.

[0019]

(Equation 2)

Therefore, the video signal output from the speed doubling circuit 300 is a signal whose horizontal and vertical frequencies are twice that of the two-dimensional video signal.

Four delay field memories are provided, and the left-eye video signal corresponds to the right-eye video signal.
FIG. 5 shows signals of the respective units when the signals are delayed by two fields.

[0022]

In the conventional two-dimensional / three-dimensional video conversion apparatus, a double-speed circuit having a field memory is required to generate a double-speed three-dimensional video signal. Problem.

An object of the present invention is to provide a two-dimensional / three-dimensional video converter capable of reducing the number of field memories and reducing the cost as compared with the prior art.

[0024]

According to the present invention, a two-dimensional /
The three-dimensional video converter converts the input two-dimensional video signal into
A plurality of field memories for storing a predetermined number of past fields from the latest field, and two video signals having a relative time difference are read from the plurality of field memories, and one is output as a left-eye video signal,
Means for outputting the other as a right-eye video signal.
In the three-dimensional / three-dimensional video converter, the frequency of the read clock of each field memory is set to twice the frequency of the write clock of each field memory.

Since the frequency of the read clock of each field memory is set to twice the frequency of the write clock of each field memory, the left-eye video signal and the right-eye video signal read from the field memory are 2 The horizontal and vertical frequencies are twice as high as the two-dimensional video signal.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a two-dimensional / three-dimensional video converter.

The two-dimensional / three-dimensional video conversion device is an integrated circuit (L) for converting a two-dimensional video signal into a three-dimensional video signal.
SI) 10 and a plurality of delay field memories 20 connected to the integrated circuit 10.

FIG. 1 shows only components related to writing data to the delay field memory 20 and reading data from the delay field memory 20 as components of the integrated circuit 10. That is, as the components of the integrated circuit 10, the write-side data path 11, the write-system timing generator 12, the read-side data path 13, and the read-system timing generator 14 are illustrated. The integrated circuit 10 includes a motion vector detecting unit, an interface connected to the CPU, and the like, in addition to these components.

The integrated circuit 10 receives a luminance signal (Y signal) and a color difference signal (RY signal and BY signal) constituting a two-dimensional video signal. The integrated circuit 10 outputs a right-eye video signal and a left-eye video signal having a relative time difference. The right-eye video signal includes a right-eye luminance signal Y (R), a right-eye color difference signal RY (R), and a right-eye color difference signal BY (R). The left-eye video signal includes a left-eye luminance signal Y (L) and a left-eye color difference signal RY.
(L) and the left-eye color difference signal BY (L).

The two-dimensional / three-dimensional video conversion device has two
There are the following three modes as the three-dimensional / three-dimensional video conversion mode.

(1) First Normal Speed Conversion Mode The first normal speed conversion mode is a mode for generating a three-dimensional video signal having the same horizontal and vertical frequencies as a two-dimensional video signal. In this mode, one of the left-eye video signals is generated based on the two-dimensional video signal sent to the read-side data path 13 without passing through the field memory.

(2) Second Normal Speed Conversion Mode The second normal speed conversion mode is a mode for generating a three-dimensional video signal having the same horizontal and vertical frequencies as the two-dimensional video signal. Both of the left-eye video signals are supplied to the read-side data path 13 via the field memory.
Is a mode generated based on the two-dimensional video signal sent to the.

(3) Double-speed conversion mode The double-speed conversion mode is a mode for generating a three-dimensional video signal whose horizontal and vertical frequencies are twice that of a two-dimensional video signal. In this case, both the right-eye video signal and the left-eye video signal are generated based on the two-dimensional video signal sent to the read-side data path 13 via the field memory.

The integrated circuit 10 has a first reference clock signal CLK1 generated based on the horizontal synchronization signal HSYNC of the two-dimensional video signal, and a horizontal synchronization signal HS of the two-dimensional video signal.
Second reference clock signal CL generated based on YNC
K2, a vertical synchronization signal VSYNC of a two-dimensional video signal, a first horizontal synchronization signal HD1 generated by a first reference clock signal CLK1 based on a horizontal synchronization signal HSYNC of a two-dimensional video signal, and a horizontal synchronization signal HSYNC of a two-dimensional video signal
, A second horizontal synchronization signal HD2 generated based on the second reference clock signal CLK2.

FIG. 2 shows a phase synchronization circuit (PLL circuit) for generating the first reference clock signal CLK1 and the first horizontal synchronization signal HD1.

The input of the phase synchronization circuit is a horizontal synchronization signal HSYNC of a two-dimensional video signal, and the output of the phase synchronization circuit is a first horizontal synchronization signal HD1. The phase comparison result between the horizontal synchronization signal HSYNC, which is the input of the phase synchronization circuit, and the first horizontal synchronization signal HD1, which is the output of the phase synchronization circuit, is converted into a voltage by the phase comparison unit 31. The output voltage of the phase comparison section 31 is sent to a voltage controlled oscillator (VCO) 33 after being smoothed by a low pass filter (LPF) 32. The voltage controlled oscillator 33 outputs a signal having a frequency corresponding to the input voltage.

The output (signal a) of the voltage controlled oscillator 33 is
The signal is taken out as the first reference clock signal CLK1 and sent to the divide-by-2 circuit 34. The frequency of the output signal a of the voltage controlled oscillator 33 is １ ／
The signal b is output. The output signal b of the ２ divider circuit 34 is sent to the 910 divider circuit 35. From the 910 frequency dividing circuit 35, a signal HD1 in which the frequency of the output signal b of the 2 frequency dividing circuit 34 is reduced to 1/910 is output.

The frequency f _CLK1 of the signal (first reference clock signal CLK1) output from the voltage controlled oscillator 33 is
When the phase difference between the input and output of the phase synchronization circuit is 0, the frequency f _H of the horizontal synchronization signal HSYNC (15.75 [kHz
z]) 1820 times. That is, the frequency f _CLK1 of the first reference clock signal CLK1 is 1820F _H,
It is about 28.6 [MHz].

In the first reference clock signal CLK1, one cycle of the horizontal synchronization signal HSYNC of the two-dimensional video signal is 1820.
It becomes a signal divided into clocks. 2D video signal is V
If the video is reproduced by TR, the horizontal synchronization signal H
The frequency of SYNC may fluctuate. The frequency of the first reference clock signal CLK1 is equal to the horizontal synchronization signal HSYNC.
Fluctuates according to the fluctuation of the frequency of

The second reference clock signal CLK2 and the second
The horizontal synchronizing signal HD2 is also generated by the same phase synchronizing circuit as in FIG.
Is generated. Frequency of second reference clock signal CLK2
Number f _CLK2Is that the phase difference between the input and output of the phase locked loop is 0
In this case, the frequency f of the horizontal synchronization signal HSYNC is used._H(1
5.75 [kHz]), which is 1820 times. That is,
2 Frequency f of reference clock signal CLK2_CLK2Is 182
0f_H, Which is about 28.6 [MHz].

The second reference clock signal CLK2 and the second
In the phase synchronization circuit for generating the horizontal synchronization signal HD2, the cut-off frequency of the low-pass filter (LPF) is set lower than the cut-off frequency of the low-pass filter (LPF) 32 in FIG. For this reason, the second reference clock signal CLK2 is a signal with little frequency fluctuation even if the frequency of the horizontal synchronization signal HSYNC changes.

Referring to FIG. 1, first reference clock signal C
LK1 is frequency-divided by two by the frequency-dividing circuit 15. Third clock signal CLK3 output from divide-by-2 circuit 15
Is sent to the write timing generator 12 and the first selector 16. Frequency f of third clock signal CLK3
_CLK3 is the frequency f _{CLK1 of} the first reference clock signal _CLK1.
It is 1/2 of.

The second reference clock signal CLK 2 is sent to the first selector 16 and to the divide-by-2 circuit 17. The fourth clock signal CLK4 output from the divide-by-2 circuit 17 is sent to the first selector 16. The frequency f _{CL K4} of the fourth clock signal CLK4 is の of the frequency f _CLK2 of the second reference clock signal CLK2.

The vertical synchronization signal VSYNC is supplied to the write timing generator 12 and the read timing generator 14.
Sent to The first horizontal synchronizing signal HD1 is sent to the write timing generator 12 and the second selector 18
Sent to The second horizontal synchronizing signal HD2 is supplied to the second selector 1
8

The first selector 16 selects one of the third clock signal CLK3, the second reference clock signal CLK2 and the fourth clock signal CLK4 according to the set two-dimensional / three-dimensional video conversion mode. The selection is sent to the read timing generator 14.

The second selector 18 selects one of the first horizontal synchronizing signal HD1 and the second horizontal synchronizing signal HD2 according to the set two-dimensional / three-dimensional video conversion mode, and selects the read system. This is sent to the timing generator 14.

As the 2D / 3D video conversion mode, the first
If the normal speed conversion mode is set, the first selector 16 selects the third clock signal CLK3 and sends it to the read timing generator 14. In this case, the write clock and the read clock of the field memory 20 are the third clock signal CLK3 obtained by dividing the first reference clock signal CLK1 by two. Therefore, the operation of the integrated circuit 10 is exactly the same as the operation of the integrated circuit 100 of FIG.

As the 2D / 3D video conversion mode, the second
When the normal speed conversion mode is set, the first selector 16 selects the fourth clock signal CLK4 and sends it to the read timing generator 14. In this case, the write clock for the field memory 20 is the third clock signal C obtained by dividing the first reference clock signal CLK1 by two.
LK3, and the read clock of the field memory 20 is the fourth clock obtained by dividing the second reference clock signal CLK2 by two.
This becomes the clock signal CLK4. Therefore, even if the frequency of the horizontal synchronization signal HSYNC of the two-dimensional video signal changes,
Jitter is absorbed.

When the double speed conversion mode is set as the 2D / 3D video conversion mode, the first selector 1
6 selects the second reference clock signal CLK2 and sends it to the read timing generator 14. In this case, the write clock of the field memory 20 is the third clock signal CLK obtained by dividing the first reference clock signal CLK1 by two.
3, and the read clock of the field memory 20 becomes the second reference clock signal CLK2.

That is, when the double speed conversion mode is set as the two-dimensional / three-dimensional video conversion mode, the frequency of the read clock of the field memory 20 is twice the frequency of the write clock. Therefore,
The three-dimensional video signal output from the integrated circuit 10 is a signal whose horizontal and vertical frequencies are twice those of the two-dimensional video signal. Even if the frequency of the horizontal synchronization signal HSYNC of the two-dimensional video signal changes, the jitter is absorbed.

FIG. 3 shows signals of the respective parts when the double-speed conversion mode is set as the two-dimensional / three-dimensional video conversion mode. FIG. 3 shows an example in which four delay field memories are provided and the left-eye video signal is delayed by two fields from the right-eye video signal.

In this embodiment, the conventional 2 shown in FIG.
Since a speed-doubling circuit is not required as compared with the three-dimensional / three-dimensional video converter, the circuit can be simplified and the cost can be reduced.

[0054]

According to the present invention, the number of field memories can be reduced as compared with the prior art, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a 2D / 3D video conversion device.

FIG. 2 is an electric circuit diagram showing a phase synchronization circuit for generating a first reference clock CLK1 and a first horizontal synchronization signal HD1.

FIG. 3 is a time chart showing signals of respective parts in FIG. 1 when a double speed conversion mode is set as a two-dimensional / three-dimensional video conversion mode.

FIG. 4 is a block diagram showing a configuration of a conventional two-dimensional / three-dimensional video converter for generating a double-speed three-dimensional video signal from a two-dimensional video signal.

FIG. 5 is a time chart showing signals of respective units in FIG. 4;

[Explanation of symbols]

 Reference Signs List 10 integrated circuit 11 write-side data path 12 write-system timing generator 13 read-side data path 14 read-system timing generator 15 frequency-dividing circuit 16 first selector 17 frequency-dividing circuit 18 second selector 20 delay field memory

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Haruhiko Murata 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 13 / 00-15/00

Claims (1)

(57) [Claims] 1. A plurality of field memories for storing input two-dimensional video signals for a predetermined number of past fields from the latest field, and a plurality of field memories,
Means for reading out two video signals having a relative time difference, outputting one as a left-eye video signal, and outputting the other as a right-eye video signal.
A two-dimensional / three-dimensional video converter, wherein a frequency of a read clock of each field memory is set to twice a frequency of a write clock of each field memory.