JP2663484B2 - Memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for writing an input video signal to a memory and reading data from the memory in synchronization with a predetermined synchronization signal to obtain an output video signal.

[Summary of the Invention]

According to the present invention, an input video signal is written to a memory in synchronization with an input synchronization signal, and data is read out from the memory in synchronization with a predetermined output synchronization signal to obtain an output video signal. In a memory device in which the phase difference between the vertical synchronizing signals of the output synchronizing signals is controlled to be within a predetermined range, the phase control is stopped when the input video signal is a continuous signal of odd or even fields. By doing so, the image distortion caused by the phase control is avoided.

[Conventional technology]

There is a type in which an input video signal is written into a memory, data is read out from the memory in synchronization with a predetermined synchronization signal, and an output video signal is obtained, for example, to absorb jitter of the input video signal. In this case, since the horizontal frequency (line frequency) of the input video signal is different from the horizontal frequency of the output video signal, there is a possibility that passing may occur between writing and reading. When such an overtaking occurs,
In the case of a moving image, when an discontinuous point is visible in an image or when there is only a field memory, inversion of an odd field and an even field occurs.

To prevent such inconveniences caused by overtaking,
Conventionally, it has been proposed to compare the phases of the vertical synchronization signals of the input and output synchronization signals and perform phase control (overtaking control) so that the phase difference falls within a predetermined range. FIG. 4 shows an example of a memory device in which such phase control is performed.

In the figure, an input video signal supplied to a terminal (1)
S _IN is converted into a digital signal by the A / D converter (2),
For example, it is supplied to a memory (3) composed of a field memory.

Further, the input video signal S _IN from the terminal (1) is supplied to a sync separator (4), the synchronizing signal SYNC1 obtained from the synchronizing separating circuit (4) is supplied to the AFC circuit (5).
Then, the write clock WCLK obtained from the AFC circuit (5) is supplied to the clock terminal W · CK of the memory (3). The vertical and horizontal synchronization detection signals VD and HD obtained from the AFC circuit (5) are supplied to a write address control circuit (6), and the control circuit (6) supplies the address terminals W.AD of the memory (3). Then, an address signal is supplied in synchronization with the synchronization detection signals VD and HD, that is, the synchronization signal SYNC1. Thus the memory (3), the input video signal S _IN in synchronism with the sync signal SYNC1 are sequentially written.

Reference _numeral (7) denotes an output synchronizing signal generating circuit. The horizontal synchronizing signal _Hsync obtained from the generating circuit (7) is supplied as a reference signal to a PLL circuit (8), and is obtained from the PLL circuit (8). The clock synchronized with the horizontal synchronizing signal _Hsync is supplied to the generation circuit (7), and is also supplied to the clock terminals R and CK of the memory (3) as the read clock RCLK. The synchronizing signal SYNC2 obtained from the generating circuit (7) is supplied to the read address control circuit (9), and the control circuit (9) synchronizes the synchronizing signal SYNC2 with the address terminal R · AD of the memory (3). As a result, an address signal is supplied. As a result, data is sequentially read from the memory (3) in synchronization with the synchronization signal SYNC2, and an output video signal _SOUT is obtained.

The output video signal S obtained from the memory (3)
_OUT is supplied to a synthesizer (10), where the synchronizing signal SYNC2 obtained from the generation circuit (7) is synthesized by the synthesizer (10), and then output to a terminal (12) via a D / A converter (11). ).

A phase comparator (13) is supplied with a vertical synchronization detection signal VD from an AFC circuit (5) and a vertical synchronization signal VD from a generation circuit (7).
_sync is supplied and compared. The comparison error signal from the phase comparator (13) is supplied as a control signal to the generation circuit (7) via the driver (14), and the phase difference between the vertical synchronization detection signal VD and the vertical synchronization signal _Vsync is calculated. The generation phase of the vertical synchronization signal _Vsync is controlled so as to be within a predetermined range. The comparison error signal from the phase comparator (13) is
It is supplied as a control signal to the oscillator of the PLL circuit (8) via the driver (14), and fine phase control is performed.

The example of FIG. 4 shows the basic configuration.
Although omitted, actually, the phase of the vertical synchronization detection signal VD obtained from the AFC circuit (5) and the horizontal synchronization signal _Hsync obtained from the generation circuit (7) are also compared, and the horizontal synchronization signal is obtained by the comparison error signal. The generation phase of the signal _Hsync is also controlled. That is, FIGS. 5 and 7 show a specific configuration example of a main part of the phase comparator (13) and the generation circuit (7) in the example of FIG.

First, the example in FIG. 5 will be described. The example of FIG.
3 shows a generation unit of the vertical synchronization signal _Vsync . In the figure, (21V) is a counter for generating a vertical synchronization signal,
The counter (21 V) has a horizontal synchronization signal H (not shown).
_sync is supplied as a clock and is counted up sequentially. The count output of this counter (21V) is supplied to a decoder (22V). If the count output of the counter (21V) to one period of the vertical synchronization signal V _sync as shown in FIG. 6 A changes the 0~4n-1, the decoder (22V)
Of the first, second, third and fourth output terminals, respectively, while the count output becomes 2n-3n-1, 3n-4n-1, 0-n-1 and n-2n-1. As shown in FIGS. B, C, D, and E, a high-level "1" signal is output, and first, second, third, and fourth windows are formed. First through signal obtained to the fourth output terminal of the decoder (22V) is supplied to the input side of the respective AND circuits _{(23V 1) ~ (23V 4} ), these AND circuits (23V ₁₎ ~ ( 23V ₄ ) on the input side
Vertical sync detection signal V from AFC circuit (5) (see Fig. 4)
D is supplied. In this case, the vertical synchronization detection signal VD
When present in correspondence with to fourth window, each AND circuits _{(23V 1) ~ (23V 4} ) on the output side to the high level "1"
Is output. In addition, this AND circuit (23V ₁ )
The (23V ₄ ) output signal is latched by the latch circuits (24V ₁ ) to (24V ₄ ) at the timing of the vertical synchronization detection signal VD.

The latch circuit (24V ₁₎ output signals of ~ (24V ₄₎ is
Each of the AND circuits (25V ₁ ) to (25V ₄ ) is supplied to the input side of the AND circuits (25V ₁ ) to (25V ₄ ). ), The signal is supplied as a load timing signal _SLD after being delayed for a predetermined period. This load timing signal S _LD
If There supplied to the AND circuit _{(25V 1) ~ (25V 4} ), when the vertical sync detection signal VD is present in correspondence to the first to fourth windows, each AND circuits (25V ₁₎ ~ (25V ₄ )
Outputs a high-level "1" signal. The output signal of the AND circuit _{(25V 1) ~ (25V 4} ) is a terminal SEL of the multiplexer (27V), is supplied as 4-bit switching control signal, the load value N _V1 to N _V4 by the multiplexer (27V) Either is selected and supplied to the counter (21V). In this case, when the vertical sync detection signal VD is present in correspondence to the first to fourth window, the load values N _V1 to N _V4 are each selected. And AND circuit (25V ₁ )
The output signal of ~ (25V ₄₎ are supplied to an OR circuit (28V),
The output signal of the OR circuit (28V) is supplied to the load terminal LOAD of the counter (21V). Therefore, at the timing of the load timing signal S _LD, the load value N _V1 to N _V4 counter (21V) is loaded. Thus, the counter (21
The V), every time the vertical sync detection signal VD is supplied, the load value N corresponding to the position of the vertical sync detection signal VD _V1 to N _V4
Is loaded. Therefore, the vertical sync detection signal VD is controlled to fit within a predetermined window, the counter (21V) vertical synchronization signal V _sync output from the carry
And the phase difference between the vertical synchronization detection signal VD and the vertical synchronization detection signal VD fall within a predetermined range.

Next, the example of FIG. 7 will be described. The seventh illustrated example shows the generation of the horizontal synchronizing signal H _sync, the parts corresponding to FIG. 5 in the FIG. 7 are denoted by reference numerals obtained by replacing the "V" to "H" Is shown. In the figure, (21H) is a counter for generating a horizontal synchronization signal,
The counter (21H) is supplied with a clock from a PLL circuit (8), not shown, and is sequentially counted up. The count output of the counter (21H) is supplied to the decoder (22H). If the count output of the counter (21H) in one period of the horizontal synchronizing signal H _sync as shown in FIG. 8 A changes the 0~4m-1, decoder (22H),
The first, second, third, and fourth output terminals output count outputs of 2m to 3m-1, 3m to 4m-1, 0 to m-1, and m to 2 respectively.
During the period of m-1, a high-level "1" signal is output as shown in FIGS. B, C, D, and E to form first, second, third, and fourth windows. The following is configured and operates similarly to the example of FIG. Therefore, the counter (21H)
Each time the vertical synchronization detection signal VD is supplied, a load value N _{H1 to} N _H4 corresponding to the position of the vertical synchronization detection signal VD is loaded so that the vertical synchronization detection signal VD falls within a predetermined window. Is controlled. That is, the counter (21H)
Phase difference between the phase and the vertical sync detection signal VD of a horizontal synchronizing signal H _sync is output as more carry is made to be within a predetermined range.

[Problems to be solved by the invention]

As described above, in the example of FIG. 4, the phase of the vertical synchronization signal _Vsync is controlled such that the phase difference between the vertical synchronization detection signal VD and the vertical synchronization signal _Vsync falls within a predetermined range. In this case, the input video signal S _IN and the output video signal S
There is no problem when there is no large frequency difference with _OUT . However, for example, one vertical cycle is 262 as an input video signal S _IN like a video signal from a game computer.
Supply line, and output video signal S _OUT
When a vertical cycle of 262.5 lines is obtained, the vertical frequency difference becomes large and a large phase control is performed on a line basis, which causes inconvenience such as distortion of an image.

By the way, when the input video signal S _IN is one in which the vertical cycle from the game computer is 262 lines and the signal of the odd field or the even field is continuous (video signal of the non-interlace system), it overtakes writing and reading. Even if there is, there is no inversion of the odd field and the even field, and the deterioration of the image quality is small.

The present invention, in consideration of such a point, when the input video signal is a continuous signal of the odd or even field, to stop the phase control to prevent overtaking between writing and reading, The purpose is to prevent image quality deterioration.

[Means for solving the problem]

In the present invention, the memory (3) is synchronized with the input synchronization signal SYNC1.
Together with the input video signal S _IN is written to, the memory (3) from a predetermined output synchronization signal SYNC2 synchronization with the data is read out to the output video signal S _OUT is obtained, the input and output synchronization signals SYNC1 and SYNC2 A memory device in which the phases of respective vertical synchronizing signals are compared, a comparison error signal is supplied to an output synchronizing signal generation circuit, and a phase control is performed so that a phase difference falls within a predetermined range. S
_IN detection circuit for detecting (15) is provided that is intended to successive odd or even field signals, when the input video signal S _IN is intended to successive odd or even field of the signal, the detection circuit ( The phase control is stopped by the detection signal of 15).

[Action]

In the above configuration, when the input video signal S _IN is a continuous signal of the odd or even field,
Since phase control for preventing overtaking between writing and reading is stopped, for example, the input video signal S _IN
As well as a video signal from a game computer with one vertical cycle of 262 lines,
Output video signal even when the S 1 vertical period as _OUT obtain what is 262.5 lines, since phase control is not performed, image distortion due to significant phase control will not occur.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the figure, reference numeral (15) denotes a detection circuit for detecting that the input video signal S _IN is a continuous signal of an odd or even field signal (a video signal of a non-interlace type in which the number of lines in one vertical period is even). It is. The detection circuit (15), is supplied synchronization signal SYNC1 obtained from sync separator (4), the input video signal S _IN whether those consecutive odd or even field of the signal is detected.

In this example, a driver (14) having an enable terminal (14a) is used. And
The detection signal _SD of the detection circuit (15) is supplied to the enable terminal (14a) of the driver (14), and the input video signal S _IN
Is a continuous signal of the odd or even field, the comparison error signal from the phase comparator (13) is not obtained at the output of the driver (14).

The present example is configured as described above, and the rest is configured in the same manner as the example in FIG.

In this example, when the input video signal _SIN is a continuous signal of odd or even fields, the comparison error signal from the phase comparator (13) is not obtained at the output side of the driver (14), vertical synchronizing signal V _sync for a phase difference within a predetermined range of the synchronization detection signal VD and the vertical synchronization signal V _sync
Is no longer controlled. That is, the memory (3)
The phase control for preventing the overtaking between the writing and reading of the data is stopped.

FIGS. 5 and 7 show, for example, FIG. 2 and FIG. 7 in order to stop the phase control when the input video signal S _IN is a continuous signal of the odd or even field. It is configured as shown in FIG. That is, the AND circuit _{(25V 1) ~ (25V 4} ) [(25
H ₁₎ ~ and (25H _4)] Multiplexer (27V) [(27H)]
A gate circuit (29V) [(29H)] is provided between the gate circuit and the gate circuit (29V) [(29H)], and the detection signal _SD from the detection circuit (15) is supplied to the gate circuit (29V) [(29H)]. Then, the input video signal S _IN is a gate is opened when not a continuum of odd or even field signals fifth illustrated example Seventh
In the case of a continuous circuit, the gate is closed and the gate circuit (29 V)
The output side of the [(29H)], for example signals of four bits which all bits are low level "0" is obtained, the multiplexer (27V) in [(27H)] load value N _V1 to N _V4 [N _H1 ~
N _H4 ], for example, N _V1 [N _H1 ] is always selected. D flip-flop (26V)
[(26H)] and the AND circuit _{(25V 1) ~ (25V 4} ) [(25
H ₁₎ ~ (changeover switch circuit between 25H _4)] (30 V)
[(30H)] is arranged and this changeover switch circuit (30V)
[(30H)] and the other perpendicular to the input side is obtained from the counter (21V) synchronizing signals V _sync of the supplied. The detection signal _SD from the above-described detection circuit (15) is supplied to the changeover switch circuit (30V) [(30H)], and the input video signal
When S _IN is not a continuous signal of odd or even fields, D flip-flop (26V) [(26H)]
The obtained load timing signal S _LD is output to be in a state similar to that of the example of FIG. 5 (the example of FIG. 7), while when the load is continuous, the vertical synchronization signal V _sync is output,
At the timing of this vertical synchronization signal _Vsync , the counter (21
V) [(21H)] is loaded with a load value, for example, N _V1 [N _H1 ].

Therefore, in the example of FIG. 2 (the example of FIG. 3),
At the timing of the vertical synchronization signal _Vsnyc obtained from the counter (21V), a constant load value is loaded into the counter (21V) [(21H)] regardless of the position of the vertical synchronization detection signal VD. _{Since the sync} [H _sync ] is generated irrespective of the phase of the vertical synchronization detection signal VD, the phase control is stopped.

As described above, according to this example, when the input video signal S _IN is a continuous signal of the odd or even field, the phase control for preventing the overtaking between the writing and the reading is stopped. For example, input video signal
With one vertical period as the video signals from the computer gaming as S _IN supplies what is 262 lines, even when the one vertical period is obtained what is 262.5 lines as the output video signal S _OUT, the phase No control is performed, and image distortion due to significant phase control does not occur.

2 and 3 show an example in which four windows are respectively formed for the sake of simplicity of explanation, but in reality, finer windows are formed and phase control is performed. You.

〔The invention's effect〕

According to the present invention described above, when the input video signal is a continuous signal of the odd or even field, the phase control for preventing the overtaking between the writing and the reading is stopped. It is possible to avoid image distortion caused by.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the embodiment, FIG. 4 is a block diagram of a conventional example,
FIG. 5 to FIG. 8 are illustrations for the explanation. (3) is a memory, (4) is a synchronization separation circuit, (7) is an output synchronization signal generation circuit, (13) is a phase comparator, and (14) is a driver.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Katsuhiko Ueno Inventor, Sony Corporation, 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo (56) References JP-A-58-208905 (JP, A)

Claims (1)

(57) [Claims] An input video signal is written to a memory in synchronization with an input synchronization signal, and data is read from the memory in synchronization with a predetermined output synchronization signal to obtain an output video signal. In the memory device, the phases of the vertical synchronization signals of the output synchronization signals are compared, and the comparison error signal is supplied to the output synchronization signal generation circuit, and the phase is controlled so that the phase difference falls within a predetermined range. A detection circuit for detecting that the input video signal is a continuation of odd or even field signals is provided, and when the input video signal is a continuation of odd or even field signals, the detection circuit A memory device, wherein the phase control is stopped by a detection signal.