JP2000224550A - Television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field discrimination circuit that generates a stable field signal by detecting a total dot clock number for a horizontal period with a horizontal synchronizing signal and a dot clock signal to generate a horizontal pulse signal for field discrimination. SOLUTION: A horizontal address generating section 4 generates a horizontal address signal. A horizontal dot number detection circuit 10 receives this horizontal address signal to hold the address signal with a reference edge of a horizontal synchronizing signal 1 thereby detecting a total dot clock number for one horizontal period. Address data equally dividing the horizontal synchronizing signal are calculated by using the horizontal synchronizing signal 1 and a clock signal from the total dot clock number for the one horizontal period. A horizontal pulse signal required to detect an edge of a vertical synchronizing signal is generated from the data to discriminate a vertical reference edge and to obtain a field signal even when a horizontal frequency division ratio of an input signal is unknown.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field discriminating circuit for a color television receiver (International Patent Classification H).
04N9 / 28).

[0002]

2. Description of the Related Art In recent color television receivers, in order to perform advanced digital video signal processing such as conversion from an interlace signal to a progressive signal,
When an interlace signal is input, a signal used to determine whether the current field is an odd field or an even field is used. In order to generate these signals, various phases of pulses having different phases are generated using an analog delay element based on the horizontal synchronization signal of the video. Although the odd field and the even field are determined by detecting the edge of the vertical synchronization signal using the pulse signal, there are problems in frequency correspondence, accuracy, stability, and circuit scale. Therefore, as a method of solving the above-mentioned problems, it operates stably with high accuracy,
In addition, a field discriminating circuit using a digital circuit capable of reducing a circuit scale by high integration has been proposed.

An example of the conventional field discriminating circuit will be described below with reference to the accompanying drawings when the signal input to the television receiver is an interlace signal. FIG. 6 shows a block diagram of a conventional field discriminating circuit. This is a circuit for generating a field discrimination signal used inside the television receiver from a horizontal synchronization signal and a vertical synchronization signal of a video signal.

In FIG. 6, 1 is a horizontal synchronizing signal, 2 is a vertical synchronizing signal, 3 is a horizontal synchronizing PLL circuit, 4 is a horizontal address generating circuit, 5 is a horizontal pulse circuit, 6 is a vertical edge discriminating circuit, and 7 is a field. A discrimination circuit 8 is a field discrimination signal. FIG. 7 is a timing signal diagram for explaining the operation of the conventional example when an interlace signal is input.

[0005] An operation example of the conventional field discriminating circuit thus configured will be described below. First, a horizontal synchronizing signal 1 synchronized with an input video signal as shown in FIG. 7A is input to a horizontal PLL circuit 3 in which a horizontal frequency dividing ratio is set in advance, whereby the horizontal synchronizing signal 1 is output from the horizontal PLL circuit. The clock signal and the horizontal reference signal synchronized with the clock signal are output, and the horizontal address generation circuit 4 is driven by the clock signal and the horizontal reference signal.

The horizontal address signal output from the horizontal address generating circuit 4 is supplied to the horizontal pulse signal generating circuit 5 to synchronize with the horizontal synchronizing signal, and accurately and constantly in clock units generated from the horizontal PLL circuit 3. The stable horizontal pulse signals of FIGS. 7B and 7C with the clock width shifted in phase are created and supplied to the vertical edge detection circuit. Here, FIG. 2B shows a pulse synchronized with the horizontal synchronization signal and surrounding the horizontal reference position, and FIG.
This is a horizontal pulse signal surrounding two horizontal synchronization positions.

[0007] In the vertical edge detection circuit 6,
By using a horizontal pulse signal having a constant width surrounding the horizontal reference position shown in FIG. 7B, the vertical synchronization signal 7 at the time of odd-number feed synchronized with the horizontal synchronization signal as shown in FIG. By supplying the signal to the field discriminating circuit 7, an odd field signal is output in real time into the television receiver. 7 / (c) of FIG.
By using a horizontal pulse signal having a constant width surrounding two horizontal synchronization positions, the vertical synchronization signal 2 at the even-number feed synchronized with a half position of the horizontal synchronization signal as shown in FIG. . This discrimination signal is sent to the field discrimination circuit 7
To output an even-numbered field signal into the television receiver in real time.

As described above, the horizontal synchronizing signal used in the television receiver and the field signal synchronized with the vertical synchronizing signal are generated by a circuit using a horizontal PLL circuit, so that even if the synchronizing frequency changes, it is generated stably with high accuracy. can do. Further, since the digital circuit is used, high integration can be easily performed and the circuit scale can be reduced.

[0009]

However, in the above-mentioned conventional configuration, it is preferable that the horizontal PLL circuit always exists and the total number of dot clocks in the horizontal period can be known in advance from the horizontal frequency division ratio. However, it has recently been increasing. In the case of a digital signal connection of a video signal, a dot clock signal synchronized with the horizontal synchronization signal is input in addition to the horizontal synchronization signal and the vertical synchronization signal.

In this case, since there is a stable dot clock synchronized with the input signal, a PLL circuit, which is difficult to realize a stable operation, becomes unnecessary. Accordingly, the total dot clock of the input signal during the horizontal synchronization period is not known, and the horizontal pulse signal surrounding the horizontal reference position and the position of the 1/2 horizontal reference period synchronized with the horizontal synchronization signal necessary for the field determination described in the conventional example is obtained. Since it cannot be created, there is a problem that it is difficult to determine the field using a digital circuit.

[0011]

In order to solve this problem, in a field discriminating circuit according to the present invention, a total number of dot clocks in a horizontal period of an input signal is determined from a horizontal synchronizing signal, a vertical synchronizing signal, and a dot clock signal of an input signal. And the horizontal period is set to ４, 3 or 4 based on the total number of dot clocks.
The address data to be divided into / 4 is calculated.

A horizontal pulse signal surrounding a horizontal reference position and a 1/2 horizontal reference position synchronized with a horizontal synchronization signal is created from the address data, and an edge position of the vertical synchronization signal is determined. Even if the total number of dot clocks is not known, a field signal can be generated stably.

[0013]

A field discriminating circuit according to a first aspect of the present invention is a device for generating an internal field signal of a television receiver, comprising: a horizontal synchronizing signal and a clock signal; , The address data for equally dividing the horizontal is calculated. By generating a horizontal pulse signal necessary for edge detection of a vertical synchronizing signal from the data, field discrimination can be stably realized.

According to a second aspect of the present invention, in the circuit for detecting the total number of dot clocks in the horizontal period according to the first aspect of the present invention, a signal obtained by delaying the vertical synchronization signal is avoided from the vertical synchronization reference position. The total number of horizontal dot clocks at the position
Even if the horizontal synchronization frequency becomes unstable in the vicinity of the reference position of the vertical synchronization signal, the field can be stably determined.

According to a third aspect of the present invention, in the circuit for detecting the total number of dot clocks in the horizontal period according to the first aspect of the present invention, the detected data are all averaged during the vertical period to calculate the total number of dot clocks. Is detected, and even if the horizontal synchronization frequency and the clock frequency become unstable, the influence on the data can be reduced and the field determination can be stably realized.

According to a fourth aspect of the present invention, in the timing generator of the third aspect, the detected data is further stabilized in a vertical period in the circuit for detecting the total number of dot clocks in one horizontal period of the input signal. It is characterized by detecting the total number of dot clocks by averaging only the period, avoiding the vertical period in which the horizontal synchronization frequency and clock frequency become unstable, and using the average value of the data, It is possible to stably perform field discrimination.

(Embodiment 1) An embodiment of the invention described in claim 1 of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram of a field signal generator in a television receiver according to a first embodiment of the present invention. FIG. 2 is a timing signal diagram for explaining the operation of the first embodiment of the present invention. In FIG. 1, 9 is a dot clock signal synchronized with the horizontal synchronizing signal,
Reference numeral 10 denotes the total number of dot clocks in the horizontal period,
And a horizontal dot number detecting circuit for detecting the horizontal dot number based on the horizontal address signal, a horizontal division data calculating section 11 for calculating data for dividing the horizontal period into 1/4 and 3/4, and a horizontal pulse data calculating section 12 based on the data and the horizontal address signal. A horizontal division pulse generation circuit that generates signals. Components operating in the same manner as in FIG. 6 of the conventional embodiment are denoted by the same reference numerals, and description thereof is omitted. FIG. 2 is a timing signal diagram for explaining the operation of the first embodiment of the present invention when an interlace signal is input.

The operation of the field discriminating circuit in the television receiver according to the present embodiment thus constructed will be described below. First, in the horizontal address generator 4, the horizontal address counter is reset by the horizontal synchronization signal 1 shown in FIG. 2A, and then the horizontal address counter is incremented by the dot clock signal 9 and the horizontal address signal shown in FIG. generate.

The horizontal address signal shown in FIG. 2B generated by the above circuit is supplied to the horizontal dot number detection circuit 10, and the horizontal address signal shown in FIG.
By holding the address signal of (b) from the reference edge of the horizontal synchronization signal 1 of FIG. 2A, the total number N of dot clocks in one horizontal period is detected. Next, the total dot clock number data N is supplied to the horizontal division data calculation unit 11, and the horizontal period is calculated from the total dot clock number data N by 1/4 and 3/4.
The address data (N / 4) and (3N / 4) to be divided into are divided by an arithmetic circuit.

Next, the above-mentioned two data are supplied to a horizontal division pulse generation circuit 12, and the horizontal address signal shown in FIG.
(C) and (d) are generated. Here, FIG.
Is a pulse synchronized with the horizontal synchronization signal and surrounding the horizontal reference position, and FIG. 3D is a pulse signal surrounding the half horizontal period position. Therefore, by using the horizontal pulse signal of FIG. 2C in the vertical edge detection circuit 6 as in the conventional example, the vertical synchronization at the time of odd feed synchronized with the horizontal synchronization signal as shown in FIG. By discriminating the signal 2 and supplying this discrimination signal to the field discrimination circuit 7, an odd field signal is output in real time into the television receiver. Also, by using the horizontal pulse signal shown in FIG. 2D, the vertical synchronization signal 2 at the time of the even-number feed synchronized with the horizontal synchronization signal as shown in FIG. By supplying the signal to the circuit 7, the even field signal is output in real time into the television receiver.

According to this configuration, there is no PLL circuit,
Even if the horizontal division ratio of the input signal is unknown, the vertical reference edge is determined by detecting the total number of dot clocks in the horizontal period and creating a horizontal pulse signal for field determination using the horizontal synchronization signal and dot clock signal. Then, a field signal can be obtained.

(Embodiment 2) An embodiment of the invention described in claim 2 of the present invention will be described below with reference to FIG.

FIG. 3 is a block diagram of a detector for detecting the total number of dot clocks in the horizontal period.

In FIG. 3, reference numeral 13 denotes a delay circuit for delaying the vertical synchronizing signal, and reference numeral 14 denotes a data holding circuit for holding data at a reference edge position of the vertical pulse signal. Components that operate in the same manner as FIG. 1 of the configuration example of the first embodiment and FIG. 6 of the conventional example are denoted by the same reference numerals, and the description of the operations will be omitted.

The operation of the field discriminating circuit in the television receiver according to the present embodiment thus constructed will be described below. First, in the delay circuit 13,
The vertical synchronizing signal 2 is delayed by the horizontal synchronizing signal 1 for each scanning line for a vertical blanking period or more. The vertical pulse signal delayed by the delay circuit 13 is supplied to the data holding circuit 14, and the horizontal dot number detection circuit 1
The horizontal total dot clock number data input from 0 is held in the vertical period. The held data is input to a horizontal division data calculation unit 11 to obtain horizontal division data, and is input to a horizontal gate pulse generation circuit 12. Field discrimination is performed by creating the gate pulse and detecting the reference edge position of the vertical synchronization signal 2. Therefore, it is possible to detect the total number of horizontal dot clocks during periods other than the vertical blanking period and hold one vertical period data.

According to this configuration, the total number of horizontal dot clocks in a stable horizontal period is determined by determining the total number of horizontal dot clocks in periods other than the vertical blanking period in which the horizontal synchronizing signal and the clock signal may be unstable. Can be detected, the horizontal gate pulse signal for determining the vertical edge position can be stably generated, and the field can be stably determined.

(Embodiment 3) An embodiment of the invention described in claim 3 of the present invention will be described below with reference to FIG.

FIG. 4 is a block diagram of a detector for detecting the total number of dot clocks in a horizontal period according to the third embodiment of the present invention. In FIG. 4, reference numeral 15 denotes an average value calculator for averaging the number of horizontal dots, and reference numeral 16 denotes a vertical period detector for detecting one vertical period. 1 and 3 showing the configuration of the first and second embodiments and those which operate in the same manner as the configuration of FIG. 6 of the conventional example are denoted by the same reference numerals, and description thereof will be omitted.

Here, the determination of the total number of dot clocks in the horizontal period will be described with reference to FIG. First, the vertical period detector 1
6, one vertical period is detected from the vertical synchronizing signal 2 and the vertical period signal is supplied to the average value calculating unit 15. Next, in the average value calculating unit 15, the data input from the horizontal dot number discriminating circuit 10 is calculated by the vertical period signal from the vertical period detecting unit 16 to calculate the average value of the data for one vertical period, and the horizontal total dot clock is calculated. Find the number.

According to this configuration, by averaging the total number of dot clocks in the horizontal period in all the vertical periods, an accurate total number of horizontal dot clocks can be detected even when the horizontal synchronizing signal and the clock signal become unstable. , A horizontal gate pulse for determining a vertical edge can be generated stably, and more accurate field determination can be realized.

(Embodiment 4) An embodiment of the invention described in claim 4 of the present invention will be described below with reference to FIG.

FIG. 5 is a block diagram of a detector for detecting the total number of dot clocks in a horizontal period according to the fourth embodiment of the present invention.

In FIG. 5, reference numeral 17 denotes a vertical scanning line number detecting circuit for detecting the number of vertical scanning lines, and reference numeral 18 denotes a vertical gate pulse generating circuit for generating a pulse signal having a certain width during a vertical period.

1, 3, and 4 showing the structure of the first, second, and third embodiments, and those which operate in the same manner as the structure of the conventional example are denoted by the same reference numerals. And its description is omitted.

Here, determination of the total number of dot clocks in the horizontal period will be described with reference to FIG. First, the vertical scanning line number detecting circuit 17 determines the number of scanning lines of the input signal based on the horizontal synchronizing signal 1 and supplies it to the vertical gate pulse generating circuit 18. A vertical gate pulse signal which excludes a blanking period in the vertical period is generated based on the scanning line number data and supplied to the average value calculation unit 15. In the average value calculation unit 15,
Only during the pulse signal period, the horizontal dot number determination circuit 10
The average value of the total number of horizontal dot clocks input from is calculated to determine the total number of horizontal dot clocks.

According to such a configuration, a stable and accurate total number of horizontal dot clocks can be detected by averaging the total number of dot clocks in the horizontal period in a period other than vertical blanking where the synchronization signal is stable. Therefore, a horizontal gate pulse for determining a vertical edge can be generated stably, and more accurate field determination can be realized.

In the first, second, third and fourth embodiments, the input synchronization signal of the television receiver has been described for easy understanding. Needless to say, there is.

Although the field discrimination has been described, it is needless to say that other timing signals are also effective.

[0040]

According to the present invention, by stably and accurately determining the total number of dot clocks in the horizontal period of an input signal, a horizontal gate pulse signal for determining a vertical synchronization edge can be generated stably, and a more stable field can be obtained. It is possible to realize a field discriminating circuit for generating a signal. The same can be realized when the horizontal / vertical frequency and the dot clock frequency change.

[Brief description of the drawings]

FIG. 1 is a block diagram of a field discriminating device in a television receiver according to a first embodiment of the present invention.

FIG. 2 is a timing signal diagram for explaining the operation of the block diagram.

FIG. 3 is a block diagram of a circuit for determining the total number of dot clocks in a horizontal period according to a second embodiment of the present invention;

FIG. 4 is a block diagram of a circuit for determining the total number of dot clocks in a horizontal period according to a third embodiment of the present invention;

FIG. 5 is a block diagram of a circuit for determining the total number of dot clocks in a horizontal period according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of a field discrimination circuit in a conventional television receiver.

FIG. 7 is a timing signal diagram for explaining the operation of the block diagram.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 horizontal synchronization signal 2 vertical synchronization signal 3 horizontal address generation circuit 5 horizontal pulse generation circuit 6 vertical edge determination circuit 7 field determination circuit 8 field determination signal 9 dot clock 10 horizontal dot number detection circuit 11 horizontal division data calculation unit 12 horizontal gate pulse Generating circuit 13 Delay circuit 14 Data holding circuit 15 Average value detecting section 16 Vertical period detecting section 17 Number of scanning lines detecting circuit 18 Vertical gate pulse generating circuit

Claims (4)

[Claims] A means for generating a horizontal address signal by a dot clock based on a horizontal synchronization signal of a video signal;
Means for detecting the number of dot clocks during one cycle of the horizontal synchronization signal based on the address signal and the horizontal synchronization signal; means for calculating address data for dividing the horizontal synchronization signal based on the number of horizontal dot clocks; A television signal comprising: means for generating a pulse signal for dividing the reference signal; means for detecting a reference position of the vertical synchronization signal based on the pulse signal and the vertical synchronization signal; and field determination means based on the detection result. John receiver. 2. The apparatus according to claim 1, further comprising: means for generating a pulse signal obtained by delaying the vertical synchronizing signal, and means for holding data of the number of dot clocks during one cycle of the horizontal synchronizing signal by the signal. 2. The television receiver according to 1. 3. The apparatus according to claim 1, further comprising means for detecting one period of the vertical synchronization signal and means for averaging the number of dot clocks for one period of the horizontal synchronization signal based on the detected signal. The television receiver as described. 4. A means for detecting the number of vertical scanning lines, means for generating a constant vertical gate pulse signal synchronized with a vertical synchronization signal based on the detection result, and one cycle of a horizontal synchronization signal based on the generated signal. 2. The television receiver according to claim 1, further comprising means for averaging the number of dot clocks in the period.