JP3906788B2 - Video signal processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a time axis conversion technique when a field memory is used to synchronize an input video signal with a reference display-side synchronization signal, and in particular, data writing to a memory when both synchronization signal frequencies are close to each other. The present invention relates to the resolution of a read control defect.
[0002]
[Prior art]
In recent years, with the diversification of video signal sources at home, a function of simultaneously displaying a plurality of images on one large display screen is desired. Normally, when two or more video signals are displayed on one screen, it is necessary to synchronize all the signals with a reference display-side synchronization signal, but recently it is relatively easy to use a digital memory. This is now possible.
As a general synchronization method, when writing image data to the field memory, a clock created based on the synchronization signal on the image data side is used, and reading from the memory is performed on the reference display side. By reading using a clock generated based on the synchronization signal, a means for matching the image data with the synchronization signal on the display side is taken.
However, the problem with this method is that when there is a speed difference between the two clocks, a situation occurs in which one of the write address and the read address always overtakes the other. A phenomenon occurs in which the image quality is significantly deteriorated within one screen. Therefore, usually, a workaround is taken so that address overtaking does not occur in the same memory.
Hereinafter, a method for avoiding address overtaking in a conventional example will be described with reference to the accompanying drawings.
[0003]
FIG. 4 shows an example of a conventional technique for avoiding address overtaking. First, an input video signal to be displayed is digitized (not shown), enters image data from the input terminal 1, and is connected to the selection switch 3 in the memory circuit 2. The memory circuit 2 has two field memories of the same memory blocks (A) 4 and (B) 5 and selection switches 3 and 6 at the input / output portions of the memory blocks (A) and (B), respectively. Furthermore, a “write address” and a “read address” are connected from the outside. In the selection switches 3 and 6, selection of the memory blocks (A) and (B) is defined by the upper 1 bit (MSB) of the write address and the read address, respectively.
[0004]
The image data connected to the selection switch 3 is alternately written in predetermined areas of the memory blocks (A) 4 and (B) 5 sequentially for each field according to the write address. At this time, the write address is generated by the write address generator 10 with the vertical synchronization signal (VD-W) and the horizontal synchronization signal (HD-W) on the image data side input to the terminals 8 and 9 as inputs. .
The image data once written in the memory blocks (A) and (B) is then selected by the selection switch 6 according to the read address, read from the memory, and taken out from the output terminal 7. At this time, the read address is generated by the read address generator 18 with the display-side vertical synchronization signal (VD-R) and horizontal synchronization signal (HD-R) input to the terminals 19 and 20 as inputs. The upper 1 bit (MSB) for operating the selection switch 6 is created by a circuit provided separately in order to avoid the address overtaking described above. The operation of this portion will be further described with reference to the waveform diagram of FIG.
[0005]
In FIG. 5, (a) is a diagram showing a write address area, and shows to which of the memory blocks (A) and (B) the image data is written. In the figure, subscripts 0, 1 and 2 after (A) and (B) indicate the order of writing. (A) is a waveform diagram of the vertical pulse W, which is generated by the write address generator 10 based on the vertical synchronization signal (VD-W) input to the terminal 8 of FIG. The rising edge of this pulse corresponds to the start point of the field of image data. Next, this pulse triggers the area 1 generator 13, and the area 1 generator 13 generates (1) an area 1 pulse having a predetermined width. This area 1 pulse is connected to one input of the detection 1 circuit 14.
Next, (e) is a waveform diagram of the vertical pulse R, which is generated by the read address generating unit 18 based on the vertical synchronizing signal (VD-R) on the display side connected to the terminal 19, and the detection 1 circuit. 14 is the other input. The detection 1 circuit 14 compares the phases of the two pulses and detects whether the rising timing of the vertical pulse R is within the pulse width of the area 1 pulse. If it exists, a high level is output as shown in the waveform diagram of the detection 1 signal of (f). (K) shows a read address area, and image data is output from the memory blocks (A) and (B) in the order shown.
(Co) is a waveform diagram showing the relative relationship between the write address and the read address, the vertical axis indicates the address position of the memory area of one field, and the horizontal axis indicates the passage of time.
[0006]
FIG. 5 shows, as an example, a case where the frequency of the synchronization signal on the display side is higher than that on the image data side, and this conventional example will be described. Here, the address overtaking occurs at the location (A) 1 in the (a) write address area diagram. In (A) 1, in the waveform diagram showing the relative relationship of the address (co), as shown in (co) a, the address crosses in the middle, and overtaking of the address is predicted. Appears in the output result of the detection 1 circuit 14 in advance, and the output changes from the low level to the high level at this time, as shown in FIG.
In order to avoid overtaking of the address, reading should be switched from the current write memory area to the memory area one field before, and this is performed when the output of (f) becomes high level. This switching is performed by the memory selection address generator 12. This circuit has a delay of one field to indicate the upper 1 bit (MSB) of the write address indicating the current write memory area and the bit one field before. When the bit passed through the circuit 11 is input and the output of (f) is low level, the former bit is selected, and when the output is high level, the latter bit is selected.
With the above configuration, the overtaking problem between the write address and the read address is avoided, so that the image data can be matched with the synchronization signal on the display side without image quality deterioration.
[0007]
The following Patent Documents 1 and 2 are known as conventional techniques for avoiding the problem of overtaking write addresses and read addresses.
[0008]
[Patent Document 1]
JP-A-9-116874 [Patent Document 2]
JP-A-9-97041 [0009]
[Problems to be solved by the invention]
According to the above-described conventional configuration, the overtaking problem between the write address and the read address can be avoided, but when the input video signal or the display-side synchronization signal has jitter (time fluctuation), or a vertical synchronization signal is generated. When the processing circuit generates jitter at a stage, the memory selection bit of the read address is not stable, and the image quality may be deteriorated such that the motion is temporarily repeated, such as temporarily repeating the image. This problem will be further described with reference to FIG.
[0010]
As described in the prior art, the memory selection bit of the read address is generated from the vertical synchronization signal on the display side during the period of (c) area 1 pulse generated from the vertical synchronization signal of the input video signal. It is determined by the detection result of whether or not the pulse R exists. FIG. 3 shows the case where (e) the vertical pulse fluctuates due to jitter of the synchronization signal on the display side. (E) Since the vertical pulse at the location a is delayed in time, What has entered the range of the pulse indicates that it is out of here again. Therefore, (f) The output of the detection 1 signal becomes low level, and the memory selection selects the memory in the current write address area (B) 1 as shown in FIG. Will come to do. As a result, (A) 1 is skipped and (B) 1 is repeated.
This malfunction of memory selection due to the jitter occurs frequently especially when the frequency of the input video signal and the vertical sync signal on the display side are very close, and a phenomenon called so-called chattering occurs, causing the screen to be skipped or repeated. It becomes an unnatural movement.
As described above, in the conventional circuit for avoiding overtaking of the address, when the frequency of the input video signal and the vertical synchronization signal on the display side are close, it is inevitable that chattering occurs in the read memory selection due to jitter, There was a problem of an unnatural display screen.
Accordingly, the present invention has an object to provide a means for preventing chattering in reading memory selection in a circuit that synchronizes an input video signal with a reference display-side synchronization signal in view of such a problem in the conventional example. There is to do.
[0011]
[Means for Solving the Problems]
As a means for achieving the above object, the present invention writes the input video signal to the memory in accordance with the write clock, reads the written input video signal in accordance with the read clock, performs time axis conversion, and becomes a reference In a video signal processing circuit for obtaining a video signal synchronized with a synchronization signal on the display side,
A circuit for generating a first address signal for controlling writing to a plurality of memories and switching between the plurality of memories based on horizontal and vertical synchronization signals of the input video signal;
A circuit for generating a first area pulse having a predetermined width starting from a memory switching point of the address signal;
A circuit for generating a second area pulse having a predetermined width starting from the end point of the first area pulse;
A circuit for generating a second address signal for controlling reading from a plurality of memories and switching between the plurality of memories based on the horizontal and vertical synchronization signals on the display side;
A first detection circuit for detecting whether a memory switching point of the second address signal is within a pulse width range of the first area pulse;
A second detection circuit for detecting whether a memory switching point of the second address signal is within a pulse width range of the second area pulse;
When selecting the read memory, if the first detection circuit detects that the memory switching point of the second address signal is within the pulse width range of the first area pulse, the write memory one field before If the memory switching point of the second address signal is detected within the pulse width range of the second area pulse in the second detection circuit, the memory read out immediately before is read out. The video signal processing circuit is characterized in that the memory to be read is selected in the order that is continued , and the same memory as the writing side is selected in cases other than the above result.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings by way of preferred examples. For simplification of description, the same reference numerals are given to the same components as those in the conventional example, and the description thereof is omitted.
[0013]
FIG. 1 is a configuration diagram of a video signal processing circuit including a circuit for preventing chattering due to jitter according to the embodiment. FIG. 2 is a waveform diagram for complementing the explanation of the operation of each part in FIG.
Referring to FIG. 1, a circuit for preventing the problems described in the prior art will be described. In this embodiment, the vertical synchronizing signal (VD-W) on the input video signal side connected to the terminal 8 is the write address generator 10. 2 generates a vertical pulse W, which triggers the area 1 generator 13 and also triggers the area 2 generator 15 to generate the area 2 pulse of FIG. This area 2 pulse is set to a predetermined pulse width in consideration of the maximum fluctuation amount expected by jitter starting from the end point of the area 1 pulse, and becomes one input of the next detection 2 circuit 16. . Further, the display-side vertical synchronization signal (VD-R) connected to the terminal 19 generates a vertical pulse R in the read address generator 18, and this vertical pulse R becomes the other input of the detection 2 circuit. When the phase is compared with the area 2 pulse and within the pulse width of the area 2 pulse, a high level is output as shown in (2) detection 2 signal. Next, the output of the detection 2 signal is connected to one of the input terminals of the determination circuit 17. On the other hand, the (f) detection 1 signal from the detection 1 circuit 14 by the operation described in the conventional example is connected to another input terminal of the determination circuit 17.
[0014]
Based on the input of the two detection results, the determination circuit 17 outputs a determination signal to the memory selection address generation unit 12 from the following two conditions.
1. When the detection 1 signal is at a high level, a high level is output.
2. When the detection 2 output is at a high level, the previous determination output (one field before) is continuously output.
Next, the memory selection address generation unit 12 selects the current write memory area by the determination signal from the determination circuit 17 in the case of the low level, and 1 in the case of the high level, similarly to the operation described in the conventional example. The upper 1 bit (MSB) of the read address is sent to the memory circuit 2 so as to select the write memory area before the field.
[0015]
Next, the operation in the configuration of the present embodiment will be described with reference to FIG. 2. In the waveform diagram of (E) vertical pulse R in which discontinuity occurred in the conventional example, (E) ) The detection 1 signal is at the low level as in the conventional case, but the (2) detection 2 signal of the newly provided detection 2 circuit 16 is at the high level, and from the above conditions, the (c) determination signal is the previous level (high level). ) Is output. Therefore, (A) 1 is selected for the read memory area as indicated by the (K) read address area, and the field is not skipped due to fluctuation due to jitter.
Note that the (2) detection 2 signal becomes a high level at (4) b. However, in this case as well, since the previous determination signal level is output, no detection error occurs.
[0016]
In this embodiment, since means for solving the problem that occurs when the input video signal and the display-side synchronization signal frequency are close to each other is described, the memory circuit 2 is described with the minimum number of memories necessary for the present invention. However, an apparatus that displays an input video signal in synchronization with a synchronization signal on the display side often handles an input signal that is greatly different from the display side at the same time. In this case, for example, if the synchronization signal frequency of the two is 1.5 times different In order to synchronize, the memory area is required for 3 fields or more. In addition, there is a case where a design using a memory area of three fields or more is made for other purposes, but the present invention is not limited to the case where the two memories of this embodiment are used, and three or more memory areas are used. It is clear that the same effect can be achieved even if the memory area is used.
[0017]
【The invention's effect】
As described above, according to the video signal processing circuit of the invention of the present application, the amount of variation is added to the phase detection circuit when the input video signal is close to the reference display-side sync signal frequency and the sync signal fluctuates due to jitter. By adding another phase detection circuit that takes into account and using the detection result for determination and control of memory area switching addresses, chattering that causes discontinuous switching can be prevented, so image quality is less degraded There is an effect that a video signal can be displayed.
[Brief description of the drawings]
FIG. 1 is an overall schematic configuration diagram according to an embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the operation of FIG. 1;
FIG. 3 is a waveform diagram for explaining a conventional problem.
FIG. 4 is an overall schematic configuration diagram showing a conventional example.
5 is a waveform diagram for explaining the operation of FIG. 4; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Memory circuit, 3 ... Selection switch, 4 ... Memory block (A), 5 ... Memory block (B), 6 ... Selection switch, 7 ... Output terminal, 10 ... Write address generation part, 11 ... Delay circuit, 12 ... Memory selection address generator, 13 ... Area 1 generator, 14 ... Detection 1 circuit, 15 ... Area 2 generator, 16 ... Detection 2 circuit, 17 ... Decision circuit, 18 ... Read address generator

Claims (1)

Video signal that writes the input video signal to the memory according to the write clock, converts the time axis by reading the written input video signal according to the read clock, and obtains the video signal synchronized with the reference display-side synchronization signal In the processing circuit,
A circuit for generating a first address signal for controlling writing to a plurality of memories and switching between the plurality of memories based on horizontal and vertical synchronization signals of the input video signal;
A circuit for generating a first area pulse having a predetermined width starting from a memory switching point of the address signal;
A circuit for generating a second area pulse having a predetermined width starting from the end point of the first area pulse;
A circuit for generating a second address signal for controlling reading from a plurality of memories and switching between the plurality of memories based on the horizontal and vertical synchronization signals on the display side;
A first detection circuit for detecting whether a memory switching point of the second address signal is within a pulse width range of the first area pulse;
A second detection circuit for detecting whether a memory switching point of the second address signal is within a pulse width range of the second area pulse;
When selecting the read memory, if the first detection circuit detects that the memory switching point of the second address signal is within the pulse width range of the first area pulse, the write memory one field before If the memory switching point of the second address signal is detected within the pulse width range of the second area pulse in the second detection circuit, the memory read out immediately before is read out. The video signal processing circuit is characterized in that the memory to be read is selected in the order that is continued , and the same memory as the writing side is selected in cases other than the above result.

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